Abstract
The degradation of 100-nm effective channel length pMOS transistors with 14 /spl Aring/ equivalent oxide thickness Jet Vapor Deposition (JVD) Si/sub 3/N/sub 4/ gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 /spl Aring/ Si/sub 3/N/sub 4/ transistors is compared to reliability of 16 /spl Aring/ SiO/sub 2/ transistors.
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Schedule a callMore From: IEEE transactions on device and materials reliability : a publication of the IEEE Electron Devices Society and the IEEE Reliability Society
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