Isotropic Dry Etching Research Articles

Development of a Highly Selective Etching Process for SiO2 over Si and SiNx Using F/H-Based Remote Plasmas and a Vapor Phase Solvent

Isotropic etching is traditionally performed using liquid-based wet etching techniques. However, with the increasing integration of devices, achieving conformal etching in high aspect ratio patterns becomes difficult, as liquid chemicals are limited in their ability to penetrate deep into these structures. Moreover, during the drying phase following chemical treatment, surface tension can lead to pattern collapse. Consequently, there is a growing need for dry isotropic etching methods to replace conventional wet etching in advanced device manufacturing.In cases where high selectivity for SiO2 isotropic dry etching is required, mixtures of fluorine-based and hydrogen-based gases are typically used to generate HF, which acts as the etchant for SiO2. SiO2 can be etched through two main mechanisms. The first mechanism involves the direct reaction of HF with H2O or alcohol to etch SiO2. The second mechanism involves the formation of (NH4)2SiF6 salt through the reaction of HF with NH3, which occurs in a plasma containing NH3 and NF3. This (NH4)2SiF6 salt is then sublimated and removed in a subsequent heating process at temperatures above 100°C.The reaction of HF with NH3 to form (NH4)2SiF6 can lead to the generation of ammonium salts that may act as contaminants within the etching chamber. Additionally, this approach necessitates an extra thermal treatment step to eliminate the (NH4)2SiF6 salt. HF can be supplied either directly as vapor or generated through plasma containing fluorine and hydrogen. Plasma-based methods generally offer advantages in terms of safety and process efficiency compared to direct HF vapor usageIn this study, we investigated an isotropic dry etching process in which HF etchant is generated by discharging fluorine-based and hydrogen-based gas mixtures. A vapor-phase solvent is supplied outside the discharge region to ionize HF and directly etch SiO2. When using H2O vapor as the solvent, we achieved the etch selectivity of SiO2 over SiNx and poly Si higher than 100 and 600, respectively, was obtained while having SiO2 EPC of ~30 nm/min by optimized conditions. The etching mechanism was clarified through gas-phase and surface analyses using optical emission spectroscopy (OES), quadrupole mass spectrometry (QMS), and X-ray photoelectron spectroscopy (XPS). To assess pattern collapse, we compared the wet phase and vapor phase processes applied to the Si trench pattern. The results suggest that using fluorine and hydrogen-based remote plasmas with a vapor-phase solvent is promising for highly selective isotropic SiO2 etching in the fabrication of next-generation 3D devices.

(Invited) Low Energy Methods for Highly Selective Etching and Surface Treatment of Advanced Nanodevices

In the pursuit of higher performance semiconductors, device length scales continue to shrink down to nanometer dimensions with emerging chip designs increasingly dependent on 3D structures to maintain scaling. Memory manufacturers have already deployed 3D NAND devices with ongoing development for 3D DRAM devices. Advanced logic manufacturers have already deployed 3D FinFET devices and are beginning to deploy more complex GAA (Gate-All-Around) 3D devices as well. Building 3D structures has increased the need for more sophisticated selective etching. As these selective etches have become critical to the formation of the device, atomic precision material loss is required with low contrast materials. We review several materials systems where insufficient selectivity control in plasma-based radical etch necessitates innovative approaches such as atomic layer passivation, low energy metastable activated radicals and plasma-less low energy thermal chemical etching.Dummy polysilicon removal requires full removal of the polysilicon with minimal film loss to dielectric films such as silicon oxide and silicon nitride. While polysilicon can be removed by either wet etch or dry etch, each approach has certain limitations that narrow the overall process window. Wet etch chemistries such as TMAH (tetramethyl ammonium hydroxide) anisotropically etch polysilicon preferentially along crystalline planes which can result in silicon residues at the bottom corners of trenches. Highly isotropic dry etch radical chemistries minimize silicon residues but have greater tendency to damage the underlying epitaxial silicon layer due to either excessive film loss or halogen radical penetration through the encapsulating film. We show that the introduction of atomic layer passivation modifies the top monolayer of an oxide encapsulation layer and consequently widens the epi damage-free window.Selective mask removal requires full removal of the organic mask with high selectivity to exposed epitaxial silicon surfaces. While plasma-generated radicals have been effectively used for some time, it has become increasingly difficult for both advanced FinFET and GAA devices as the epi film loss requirements lower to a single atomic layer. We propose the tail energy distribution of reactive species formed in the plasma region is the driving factor for epitaxial film loss. To reduce these effects, we apply MARS (Metastable Activated Radical Source) technology where reactive species are indirectly formed outside the plasma region though collisions with metastable intermediates. The result is a significant reduction in higher energy species flux to the surface corresponding to a lower epi loss than conventional radical approaches.GAA device integration relies on depositing and subsequently removing SiGe layers to form Si-nanowires or nanosheets. Fluorine radical-based chemistries have limited selectivity to silicon because the bond strength difference between Si-Si and Si-Ge is exceedingly narrow and about 0.3 eV. We show a thermal chemical etching approach that achieves substantially higher SiGe:Si selectivity than radical etching on both blanket films and test structures. In addition, we highlight the strict film loss requirements that require highly selective native oxide removal prior to removing SiGe layers. We describe a thermal chemical etching approach that applies wet etch mechanisms in a vacuum environment to achieve high selectivity to both silicon and silicon nitride.

Selective Isotropic Dry Etching of SiO2 Using F/H-Based Pulsed Remote Plasma and a Vapor Phase Solvent

Isotropic etching generally employs liquid-based wet etching techniques. However, due to the high integration of devices, conformal etching is challenging in patterns with a high aspect ratio because liquid chemicals struggle to penetrate inside the pattern. Additionally, during the drying process after chemical treatment, pattern collapse is observed due to surface tension. Therefore, there is a need for dry isotropic etching techniques to replace wet etching techniques in next-generation device manufacturing processes.Typically, when high selectivity SiO2 isotropic dry etching is required, F-base/H-based gas mixtures are utilized to form HF, which serves as an etchant for SiO2. SiO2 can be dry etched through two different mechanisms. First, HF reacts directly with H2O or alcohol, etching SiO2. The other way is to produce (NH4)2SiF6 salt from the reaction of NH3, which can be formed in a plasma containing NH3 and NF3. This (NH4)2SiF6 salt is sublimated and removed by a following heating process at a temperature over 100ºC.The process above has some disadvantages, such as lowering the etch selectivity of SiO2 over Si and Si3N4 because Si and Si3N4 can be etched by F radicals remaining in the plasma. This study aimed to overcome these disadvantages by controlling the F radical through pulsing the remote plasma during the discharging of F-based/H-based gas mixtures for the formation of HF. By pulsing the remote plasma, SiO2 could be selectively etched at a higher etch rate relative to those of Si and Si3N4. Additionally, various types of H/F-based gas mixtures that do not contain nitrogen while producing HF were investigated to prevent the formation of ammonium powders, which can be a source of contamination in the chamber. Futhermore, the etching mechanisms were identified through gas phase anlysis and surface analysis. Also, any possible surface damage during the etching process was investigated.

Ordered silicon nanocone fabrication by using pseudo-Bosch process and maskless etching

Nanocone arrays are widely employed for applications such as antireflection structures and field emission devices. Silicon nanocones are typically obtained by an etching process, but the profile is hard to attain because anisotropic dry etching generally gives vertical or only slightly tapered sidewall profiles, and isotropic dry plasma etching gives curved sidewalls. In this work, we report the fabrication of cone structures by using masked etching followed by maskless etching techniques. The silicon structure is first etched using fluorine-based plasma under the protection of a hard metal mask, with a tapered or vertical sidewall profile. The mask is then removed, and maskless etching with an optimized nonswitching pseudo-Bosch recipe is applied to achieve the cone structure with a sharp apex. The gas flow ratio of C4F8 and SF6 is significantly increased from 38:22 (which creates a vertical profile) to 56:4, creating a taper angle of approximately 80°. After subsequent maskless etching, the sidewall taper angle is decreased to 74°, and the structure is sharpened to give a pointed apex. The effect of an oxygen cleaning step is also studied. With the introduction of periodic oxygen plasma cleaning steps, both the etch rate and surface smoothness are greatly improved. Lastly, it was found that the aspect ratio-dependent etching effect becomes prominent for dense patterns of cone arrays, with a greatly reduced etch depth at a 600 nm pitch array compared to a 1200 nm pitch array.

Silicon flow stop frame for encapsulation of CMOS microsensor chips by wet anisotropic etching in KOH

Bulk micromachining in silicon is governed by the etching process where anisotropic (wet) etching in KOH can yield complex structures beyond that achievable with isotropic (dry) etching techniques. One example is the miniaturised frame reported herein with an area of 2.9 to 7.5 mm2, walls that are 1/10 mm thick, a height of 525 μm equipped with sloping walls that takes advantage of the 54.7° angle of the (111) planes to the horizontal (100) top surface of the wafer. Convex corners liable to damage are protected by sacrificial bridge structures which are etched thin to a point where the frame can be easily removed from the bulk substrate material. Frames made from isotropic (dry) etching processes have been made for comparison. Although the frame structure has different applications in microfabrication, the intended use is a flow stop barrier preventing liquid resins from entering the active area of a CMOS chemical sensor chip during encapsulation for use in aqueous or gaseous media. Beyond this specific proof-of-concept, the strategy is expected to be of general interest for all who treasures KOH etching and wants to explore new avenues based on this process.

A high-precision method for manufacturing tunable solid microneedles using dicing saw and xenon difluoride-induced dry etching

Numerous fabrication techniques have been employed to produce solid microneedles (MNs); yet precise manufacturing of MNs with adjustable features (height, aspect ratio, and array number) remains the main limitation. Developing tunable MNs holds immense promise for personalized and efficient drug delivery systems. In this study, we utilized a combination of dicing saw and XeF2 isotropic dry etching processes to fabricate solid MNs with tunable characteristics. We herein created rectangular arrays using a dicing saw with desired geometry followed by dry etching to form MN arrays without further processing. Employing optimized parameters, the average heights of the MNs were 522 ± 15 µm, 614 ± 42 µm, and 698 ± 22 µm for initial pattern depths of 500 µm, 600 µm, and 700 µm, respectively. Moreover, we achieved an aspect ratio as high as 3.7, a radius of curvature less than 10 µm, and a tip angle as low as 6.4o. The mechanical and surface properties of the MNs were enhanced through magnetron sputtering with titanium. An ex vivo penetration test conducted on porcine skin demonstrated the significant potential of these MNs for transdermal drug delivery in future investigations. Overall, a cost-effective production of a single solid MN patch, featuring 400 MN arrays per cm2, can be achieved within a remarkably short timeframe (approximately 2 h). Investigating fundamental principles, this study addresses the persistent challenge in manufacturing solid MNs with adjustable features, such as height, aspect ratio, and array number. This presents a substantial advantage over alternative fabrication techniques.

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Nanosheet gate-all-around devices have demonstrated several advantages in device performance and area scaling over finFET devices with higher device density and improved electrostatic control. Robust inner spacer (IS) and channel formation is critical for high performance, reduced variability and good yield. An isotropic dry etch of the sacrificial SiGe layer with extremely high selectivity to gate spacer, IS and Si channels is necessary for high-quality channel formation over a wide range of sheet widths. Furthermore, the nFET Si:P and pFET SiGe:B source-drain (S/D) epitaxy must be isolated using inner spacers or buffers to prevent damage during Channel Release (CR). The damage can be further mitigated with optimized CR etch chemistry, enabling IS scaling. We highlight S/D damage mechanisms during CR, then demonstrate reduced S/D damage by co-optimization of the IS, CR chemistry and S/D epitaxy.

Highly selective etching of SiNx over SiO2 using ClF3/Cl2 remote plasma

Highly selective etching of silicon nitride over silicon oxide is one of the most important processes especially for the fabrication of vertical semiconductor devices including 3D NAND (Not And) devices. In this study, isotropic dry etching characteristics of SiN x and SiO2 using ClF3/Cl2 remote plasmas have been investigated. The increase of Cl2 percent in ClF3/Cl2 gas mixture increased etch selectivity of SiN x over SiO2 while decreasing SiN x etch rate. By addition of 15% Cl to ClF3/Cl2, the etch selectivity higher than 500 could be obtained with the SiN x etch rate of ∼8 nm min−1, and the increase of Cl percent to 20% further increased the etch selectivity to higher than 1000. It was found that SiN x can be etched through the reaction from Si–N to Si–F and Si–Cl (also from Si–Cl to Si–F) while SiO2 can be etched only through the reaction from Si–O to Si–F, and which is also in extremely low reaction at room temperature. When SiN x /SiO2 layer stack was etched using ClF3/Cl2(15%), extremely selective removal of SiN x layer in the SiN x /SiO2 layer stack could be obtained without noticeable etching of SiO2 layer in the stack and without etch loading effect.

Xenon Difluoride Dry Etching for the Microfabrication of Solid Microneedles as a Potential Strategy in Transdermal Drug Delivery.

Although hypodermic needles are a "gold standard" for transdermal drug delivery (TDD), microneedle (MN)-mediated TDD denotes an unconventional approach in which drug compounds are delivered via micron-size needles. Herein, an isotropic XeF2 dry etching process is explored to fabricate silicon-based solid MNs. A photolithographic process, including mask writing, UV exposure, and dry etching with XeF2 is employed, and the MN fabrication is successfully customized by modifying the CAD designs, photolithographic process, and etching conditions. This study enables fabrication of a very dense MNs (up to 1452 MNs cm-2 ) with height varying between 80 and 300µm. Geometrical features are also assessed using scanning electron microscopy (SEM) and 3D laser scanning microscope. Roughness of the MNs are improved from 0.71 to 0.35µm after titanium and chromium coating. Mechanical failure test is conducted using dynamic mechanical analyzer to determine displacement and stress/strain values. The coated MNs are subjected to less displacement (≈15µm) upon theapplied force. COMSOL Multiphysics analysis indicates thatMNs are safe to use in real-life applications with no fracture. This technique alsoenables the production of MNs with distinct shape and dimensions. The optimized process provides a wide range of solid MN types to be utilized for epidermis targeting.

(Digital Presentation) Stacked Nanosheet FETs and Beyond

Si FinFETs have been used in the industry for mass production of advanced technology nodes [1-3]. Recently, the horizontal gate-all-around (GAA) transistors are considered as promising candidates to replace FinFETs due to the excellent electrostatics and short channel control [4-6]. The GAA architecture with vertically channel stacking can further enhance the drive current for a given footprint to achieve high performance and area scaling [7]. Moreover, high mobility channel is an attractive option to boost the drive current thanks to its intrinsic higher mobility as compared with Si [8]. Furthermore, a novel TreeFET architecture [9] as a combination of stacked nanosheets and additional fin interbridges (IBs) between nanosheets can enhance ION per footprint.In this work, we demonstrate the 8 stacked Ge0.75Si0.25 nanosheets with high inter-channel uniformity and the 7 stacked Ge0.95Si0.05 nanowires with record ION per channel footprint for nFETs [10, 11]. The highly stacked 8 Ge0.9Sn0.1 nanosheet pFET with ultrathin bodies and thick bodies are demonstrated for low power and high performance [12, 13], respectively. Furthermore, TreeFETs can increase Weff per footprint for high performance devices beyond FinFETs and nanosheets.The epilayers with 8 undoped and fully strained Ge0.75Si0.25 layers sandwiched by 9 P-doped Ge sacrificial layers (SL) were grown on the Ge buffer by CVD epitaxy. The S/D and channels of the 8 stacked Ge0.75Si0.25 nanosheets are fabricated by the same epilayer structures without S/D regrowth. The doping of S/D is obtained by the heavily P-doped Ge SLs by annealing, while the channel is undoped to reduce the impurity scattering. H2O2 wet etching was used to etch the Ge SLs in channel region. The etching selectivity of Ge over Ge0.75Si0.25 is attributed to the Si content in GeSi layers and the enhanced etching rate of Ge SLs by heavily doped phosphorus [14]. To further improve the drive current, [Si] in GeSi channels is decreased to 5% to ensure the electrons populated in L4 valleys with small mt. In addition to channel stacking, TreeFET combining with FinFETs and stacked nanosheets is demonstrated to enhance Weff per footprint. IBs of TreeFETs were formed by well-controlled H2O2 wet etching. With adequate etching selectivity and optimized etching time, the SLs were partially removed to form the IBs between the nanosheets for extra conduction channels.Strained GeSn has higher hole mobility than Ge to increase ION for pFET [15] due to the hole effective mass reduction under compressive strain. Recently, the radical-based highly selective isotropic dry etching (HiSIDE) was reported to form the stacked GeSn nanosheets [16-18]. However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [15-20]. Ultrathin body device can effectively reduce the IOFF [21], but the mobility degradation is observed as the channel thickness decrease below 5nm due to surface roughness scattering [22]. However, the high mobility GeSn can afford some mobility loss due to the ultrathin body. By combining the high mobility channel and the large number of stacked nanosheets, the ION can be further improved with the suppression of IOFF by the ultrathin body. The 11nm Ge0.9Sn0.1 channel layers sandwiched by 8nm Ge0.97Sn0.03 caps, 3nm Ge caps, and 24nm Ge:B SLs were grown repeatedly on the Ge buffer. The thin double Ge0.97Sn0.03 caps can provide sufficient etching selectivity and prevent the channel bending. The heavily B-doped Ge SLs are used to reduce the S/D resistance. The significant IOFF reduction of the GeSn ultrathin bodies is attributed to the quantum confinement effects. The quantum confinement energy of 170meV in 3nm Ge0.9Sn0.1 ultrathin body is simulated by TCAD. The enlarged bandgap results in the suppression of IOFF and yields the record high ION/IOFF~107 of 8 stacked GeSn ultrathin bodies among GeSn/Ge 3D pFETs.Simple wet etching can reach the sufficient selectivity to fabricate the highly uniform Ge0.75Si0.25 nanosheets and the Ge0.95Si0.05 nanowires. The 3nm Ge0.9Sn0.1 ultrathin bodies with high inter-channel uniformity are demonstrated to reduce the IOFF. Highly stacked Ge0.9Sn0.1 thick nanosheets can improve the ION. TreeFET with the process flow similar to stacked nanosheets are the promising candidates for technology node scaling. Even higher number of stacked channels (>8) and extremely scaled ultrathin bodies (<3nm) are expected to further enhance the ION and to increase the ION/IOFF for advanced CMOS scaling. Acknowledgements- This work is supported by MOST (110-2218-E-002-030-, 110-2622-8-002-014-, 110-2218-E-002-034-MBK, and 110-2218-E-002-042-MBK) and MOE (NTU-CC-111L892001), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated. Figure 1

Compressive Strained Si1-XGex Channel for High Performance Gate-All-Around Nanosheet Transistors

As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. Exploring performance improvement techniques, such as channel strain engineering, is important for next generation CMOS technologies. It is difficult, however, to effectively induce strain into the channel region using source/drain stressors in scaled GAA NS structures due to reduction of the stressor (embedded SiGe in source/drain region) volume as transistor dimension shrinks. In addition, strain relaxation of source/drain stressors caused by introduction of crystalline defects decreases effectiveness to induce strain into the channel region. This is more pronounced by the fact that achieving superior epitaxial growth is more difficult on the GAA NS device structure due to the presence of inner spacer dielectric. Therefore, we proposed a stacked GAA NS pFET device with compressively strained SiGe channel. The SiGe channel NS devices were fabricated using Si NS channel trimming by selective isotropic dry etch and selective SiGe epitaxial growth techniques after the Si NS channel release (Fig. 1). This is the preferable scheme in terms of strain retention in the SiGe channel NS region since there are no patterning processes that cause strain relaxation during downstream processing.To investigate the device characteristics of SiGe NS devices, we fabricated strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET and investigated the crystallinity and strain in the channel region. Fig. 2 contains cross-sectional TEM images across the gate after Si0.7Ge0.3 channel formation. We observed no visible crystalline defects in the 4 nm-thick Si0.7Ge0.3 layer grown on the 2 nm-thick trimmed Si NS, indicating superior crystallinity of Si0.7Ge0.3 layer. To investigate strain in the nanoscale strained SiGe NS channel structures, Precession Electron Diffraction (PED) characterization was performed to evaluate lattice deformation of the stacked SiGe NS channel with 4 nm-thick Si0.7Ge0.3 epitaxial growth. Lattice deformation values are defined as the difference between in-plane lattice constants and the Si lattice constant, normalized by the Si lattice constant. Fig. 3 shows in-plane lattice deformation contour maps in the region of the stacked SiGe NS channel obtained from both X-cut (across the gate) and Y-cut (along the gate) for the SiGe NS structure with sheet width of 20 nm. The in-plane lattice deformation values were extracted from the middle of the SiGe NS channel as shown in Fig. 4. Preservation of half the amount of strain along the channel direction ([110]) was confirmed whereas strain along the NS width direction ([1-10]) was found to be almost fully relaxed due to elastic relaxation. This results in the Si0.7Ge0.3 channel being uniaxially stressed. The compressive stress along the channel direction estimated from the [110] lattice deformation is ~1 GPa.Normalized hole mobility in the representative Si1-xGex channel NS pFET as a function of inversion carrier density (Ninv) is shown in Fig. 5. The hole mobility of Si1-xGex channel (x = 0.35) with Si cap is almost 100% higher than that of Si NS channel. The mobility benefit of Si1-xGex channel is attributed to reduced effective hole mass along the transport direction caused by a high compressive strain in the Si1-xGex channel.The technique demonstrated in this study for forming compressively strained SiGe channel NS has great potential to improve pFET device performance for next generation of CMOS logic in GAA Nanosheet technology. Figure 1

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this , we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys.On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added.The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel.These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics.Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”.

(Digital Presentation) Advanced Process Control of Dual Patterns for FinFET Mass Production

ABSTRACT Advanced Process Control (APC) has been widely applied in state-of-the-art semiconductor industries for the everlasting pursuit of cycle time reduction, higher yield and zero scrap. Inline metrology is thus valuable input feeds for the improvement of wafer-to-wafer and within-wafer CD variations originated from either abnormality or noise of different processes. Implementing a suitable APC scheme to process flow remains a challenging task for engineers. In most cases, it is enough to implement the APC to only one single pattern on Chip. However, for multi-purpose chip design, the CD control of multiple patterns is becoming important. In this paper, we presented a workflow of APC to control the CD of two different patterns. It is shown that, with the same amount of APC process layers, we were able to improve from single pattern CD control to dual pattern CD control. The final process variations of two patterns can be controlled within ±0.5 nm. INTRODUCTION Abnormality and noise are two inevitable root causes of systematic yield loss and mis-process during semiconductor manufacturing processes [1]. Within-wafer uniformity is another important indication of process control capability. Lam tools implement Hydra Electro Static Chuck (ESC) combining the 4 radially-tunable zones with grid-heating elements, where additional CDU tuning is made possible for radial and non-radial uniformity [2].APC schemes are normally applied to a single pattern as the anchor point to control the CD and CDU. However, for multi-purpose chip layouts, areas of different CDs and pitches are designed. For instance, CD controlling of both Logic and SRAM are important for yield improvement and device performance. When APC is implemented to different processes across the production flow, it is possible to utilize properly the inline metrology data of different patterns across processes for a dual pattern control. For this purpose, The APC CD control scheme of dual patterns is demonstrated in this work. SETUP The process flow is divided into 4 stages. In stage 1, a hard mask (HM) is patterned with a Lithograph-Etching (LE) process. An added CD trimming process of stage 2 is added to cover the LE etch bias (EB) incapability. Pattern B is covered by photoresist materials to trim the CD of pattern A HM to the target value. In stage 3, a thin Atomic Layer Deposition (ALD) layer is deposited on the HM of both patterns A and B for etching protection. In stage 4, the final etch process is completed with the HMs of target CDs. RESULTS and DISCUSSIONS For single pattern APC, pattern A is designated as the anchor pattern for this scheme. For stage 1, the Hydra function is applied to pattern A to improve its CDU. Here we assume that the Hydra function barely improves the CD or CDU of pattern B, due to the fact that pattern A and pattern B have different line CDs and Pitches. In stage 2, APC is turned on using inline data of pattern A from stage 1. Pattern A is exposed for the isotropic plasma dry etching process until target CD is reached. Pattern B is covered in photoresist materials, and its CD is not changed during this process. And the photoresist materials are removed afterward. In stage 3. Fixed-amount ALD process is applied for HM protection on both Pattern A and B. In stage 4, HM is used to etch the pattern into substrate Si with Hydra function turned on for pattern A only. During this process flow, CD and CDU APC are applied to pattern A only. The process variation of stage 1 on pattern B is transferred all the way down to the final stage 4 without any APC functioning on Pattern B.Figure 1 shows the new APC flow. In stage 1, HM of pattern A and pattern B are etched with Hydra function working on pattern A only. However, inline metrology is applied to pattern B for APC of stage 3. In stage 2, Pattern A trimming changed from APC-mode to fixed time mode. The APC function is turned on for stage 3 for a global CD control of both pattern A and pattern B using ALD. And Hydra function is turned on for stage 4 for a CDU control on pattern A. It is shown that the CD variation originated from stage 1 is compensated on stage 3. With the same amount of APC stages, the effect of the APC can be improved from pattern A CD/CDU only, to pattern A CD/CDU and pattern B CD control. Figure 1

Highly Stacked GeSn Nanosheets by CVD Epitaxy and Highly Selective Isotropic Dry Etching

The eight stacked Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.9</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.1</sub> ultrathin bodies down to 3 nm with high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}/I_{\text {OFF}}$ </tex-math></inline-formula> and eight stacked Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.9</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.1</sub> thick nanosheets with high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}$ </tex-math></inline-formula> per stack are demonstrated. For the eight stacked Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.9</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.1</sub> ultrathin bodies, the 50 epilayers, including Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.9</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.1</sub> channels, double Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.97</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.03</sub> /Ge (8 nm/3 nm) caps, heavily B-doped (~2E21 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> ) Ge sacrificial layers (SLs), and undoped Ge buffer were epitaxially grown to reach high inter-channel uniformity with the co-optimization of epitaxy and radical-based highly selective isotropic dry etching (HiSIDE). The thin double Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.97</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.03</sub> caps can provide sufficient etching selectivity and stabilize the channel to prevent the channels from bending and buckling. The neutral radicals can isotropically etch the Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.97</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.03</sub> /Ge caps, Ge:B SLs, and Ge buffer to form the highly uniform eight stacked Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.9</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.1</sub> ultrathin bodies. The record <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}/{I}_{\text {OFF}}$ </tex-math></inline-formula> of 1.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{7}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}} \,\,=\,\,-0.05$ </tex-math></inline-formula> V is achieved among GeSn 3-D pFETs due to the quantum confinement. For the eight stacked Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.9</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.1</sub> thick nanosheets, the record <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}$ </tex-math></inline-formula> of 92 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> per stack at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {OV}} = {V}_{\text {DS}} = -0.5$ </tex-math></inline-formula> V is achieved among GeSn 3-D pFETs. Thick nanosheets can provide higher mobility than ultrathin bodies due to the reduced surface roughness scattering.

Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance

We propose that the use of tightly stacked three-dimensional (3D) diamond-shaped Ge nanowire (NW) gate-all-around field-effect transistor (Ge-NW GAAFET) is a feasible approach to continuous scaling. The proposed devices with the Al₂O₃ dielectric exhibit high I_SAT of 1200 <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (pFET) and 1100 <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (nFET), high I_ON/I_OFF ratio of approximately <inline-formula> <tex-math notation="LaTeX">${1} \times {10}^{{5}}$ </tex-math></inline-formula>, and steep subthreshold swing (SS) close to 70mV/dec. Superior gate control of the Ge-NW GAAFET was confirmed by the 3D TCAD simulation for the sub-3nm node applications. The formation of the tightly stacked Ge NWs is fully compatible with the complementary metal oxide semiconductor (CMOS) technology platform using only alternating isotropic and anisotropic dry etching, thus showing promising potential for extending CMOS scaling in the vertical direction.

Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.

Cyclic etching of silicon oxide using NF3/H2 remote plasma and NH3 gas flow

AbstractSelective isotropic cyclic dry etching of silicon oxide (SiO2) was investigated using a three‐step cyclic process composed of hydrogen fluoride (HF) adsorption by NF3/H2 remote plasma and reaction with NH3 gas flow to form ammonium fluorosilicate ((NH4)2SiF6), and desorption by heating. The variation of the ratio of NF3:H2 (2:1 to 1:3) and adsorption time (10–180 s) showed the highest etch selectivity of SiO2 over Si3N4 at 1:2 ratio of NF3:H2 and with the adsorption time of 20 s. The etch selectivity higher than 40 was observed with 20 s of adsorption time with a 1:2 ratio of NF3:H2 remote plasma and the total etch depth was linearly increased with the increase of cycles with the SiO2 EPC of ~7.5 nm/cycle.

Ultrasensitive Molecule Detection Based on Infrared Metamaterial Absorber with Vertical Nanogap (Small Methods 8/2021)

Inside Front Cover In article number 2100277, Lee, Jung, and co-workers develop an ultrasensitive molecule detection platform for surface-enhanced infrared absorption spectroscopy. Based on using a metamaterial absorber with 10 nm-thick vertical nanogap processed via nanoimprint lithography and isotropic dry-etching, a record-high reflection difference detection signal for a 1-octacanethiol monolayer molecule is achieved.

Enhancement of refractive index sensing for an infrared plasmonic metamaterial absorber with a nanogap.

An infrared plasmonic metamaterial absorber with a nanogap was numerically and experimentally investigated as a refractive index sensor. We experimentally demonstrated large enhancements of both sensitivity (approximately 1091 nm/refractive index unit) and figure of merit (FOM*; approximately 273) owing to the nanogap formation in the metamaterial absorber to achieve perfect absorption (99%). The refractive index sensing platform was fabricated by producible nanoimprint lithography and isotropic dry etching processes to have a large area and low cost while providing a practical solution for high-performance plasmonic biosensors.

Ultrasensitive Molecule Detection Based on Infrared Metamaterial Absorber with Vertical Nanogap.

Surface-enhanced infrared absorption (SEIRA) spectroscopy is a powerful methodology for sensing and identifying small quantities of analyte molecules via coupling between molecular vibrations and an enhanced near-field induced in engineered structures. A metamaterial absorber (MA) is proposed as an efficient SEIRA platform; however, its efficiency is limited because it requires the appropriate insulator thickness and has a limited accessible area for sensing. SEIRA spectroscopy is proposed using an MA with a 10nm thick vertical nanogap, and a record-high reflection difference SEIRA signal of 36% is experimentally achieved using a 1-octadecanethiol monolayer target molecule. Theoretical and experimental comparative studies are conducted using MAs with three different vertical nanogaps. The MAs with a vertical nanogap are processed using nanoimprint lithography and isotropic dry etching, which allow cost-effective large-area patterning and mass production. The proposed structure may provide promising routes for ultrasensitive sensing and detection applications.