Isolated Dc Voltage Sources Research Articles

A new fault-tolerant converter for renewable energy applications with improved reliability

With power converters consisting of several components, the reliability of a power converter becomes a major concern. With a switched-capacitor (SC) integrated into multilevel inverter (MLI) topologies, the chances of faults is more due to a much larger number of components than the MLI topologies with multiple isolated dc voltage sources. In this article, several SC-based 5L-MLI topologies have been analyzed for their performance with open-circuit fault (OCF), and based on the analysis, three 5L fault-tolerant MLI topologies have been proposed. The analysis for the proposed topologies have been carried out in terms of power loss analysis using PLECS software and power quality analysis using MATLAB software for different fault case scenarios. Further, the proposed 5L topologies have been compared with a similar state-of-the-art. A hardware prototype has been developed, and results have been discussed for various operating conditions.

Active Voltage Balancing Control of a Seven-Level Hybrid Multilevel Converter Topology

The series connection of a standard three-level active neutral-point-clamped (ANPC) inverter and two cascaded H-bridge (CHB) modules comprising the flying capacitors (FCs) instead of the isolated dc voltage sources forms a seven-level hybrid topology that is referred to as improved ANPC (I-ANPC) converter. This article proposes an active voltage balancing technique for control of this hybrid multilevel inverter. The suggested method is based on a set of effortless logic equations that aim to stabilize the FC voltages within the CHB modules at their requisite reference values as well as to control the output voltage of the overall hybrid converter based on the phase-shifted-carrier pulsewidth modulation strategy. The experimental results obtained from a single-phase I-ANPC inverter's prototype are presented to validate the proposed control technique and its simple logic equations.

Optimization of a New Extended Cascaded Multilevel Inverter Topology to Reduce DC Voltage Sources and Power Electronic Components

This work proposes a new multilevel inverter consisting of basic and submultilevel units. The basic unit is made-up of four isolated dc voltage sources, two bidirectional switches and ten unidirectional switches. To increase the number of the output voltage levels, a cascaded architecture based on series connection of sub-multilevel is proposed. The proposed inverter utilizes two algorithms to determine the values of dc voltage sources. Number of IGBTs, dc voltage sources, gate driver circuits, variety of dc voltage sources and peak standing voltage on the switches are calculated and their optimization to produce maximum number of levels in output voltage is investigated. To examine advantages of the proposed inverter, the topology is compared with other topologies. The results show superiority of proposed topology over most conventional topologies, in number of circuit components. Finally, to confirm the performance of the proposed multilevel inverter, experimental results of a 25-level inverter prototype are provided.

A Universal Lookup Table-Based Direct Torque Control for OW-PMSM Drives

For open-winding permanent magnet synchronous motor (OW-PMSM) system with two isolated dc voltage sources, the distribution of voltage vectors (VVs) is different under different dc-link voltage ratios. In this letter, a universal lookup table (LUT) based direct torque control (DTC) strategy is proposed for OW-PMSM drives under different conditions of the dc-link voltage ratio. The distribution criterion of VVs under various dc-link voltage ratios is analyzed and the VVs are assigned to different regions by designing a generalized region division scheme. A universal LUT is established to realize the selection of required VV in the DTC strategy. Experimental results validate the effectiveness of the proposed universal LUT-based DTC strategy for the OW-PMSM system with different voltage ratios.

Modelling and Simulation of an Asymmetrical Modular Multilevel Inverter with Less Number of Components

ABSTRACT This paper presents a modified topology for asymmetric modular multilevel inverter as a fundamental block. It consists of eight switches (including six bidirectional-conducting unidirectional-blocking switches and two bidirectional-conducting bidirectional-blocking switches) and four DC sources with unequal magnitudes, which generates 13-level output voltage. The proposed topology offers special features such as reduced number of switches, isolated DC sources, economical and less complexity with modular structure as compared to other contemporary topologies. Moreover, significant reduction in switch voltage can be achieved. The comparative study of proposed topologies with the conventional and recent topologies have been presented in terms of power switches, gate drivers, isolated DC voltage sources and total standing voltage on the switches. A multicarrier-based sinusoidal pulse width modulation scheme is adopted for generating the gate pulses using real-time simulation with dSPACE DS 1104. The proposed topology offers a fewer number of ON-state switches which lead to the reduction in power loss. The feasibility of proposed multilevel inverter, the simulation and experimental results are analysed under steady state and dynamic states.

Dual input switched‐capacitor‐based single‐phase hybrid boost multilevel inverter topology with reduced number of components

A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched-capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

Harmonic cancellation in a Multi-level Inverter Configuration Suitable for PV Applications

Multi-level inverters are playing a major role in PV based systems because of numerous advantages like low dv/dt, better harmonic profile so on. But, conventional multi-level inverters consist of some drawbacks like capacitor balancing issues, greater requirement of capacitor banks and clamping diodes. To address these issues, a novel multi-level inverter has been presented in this paper, which can function as a seven-level, five-level and three-level inverter. The inverter circuit utilizes six switching devices and two isolated DC voltage sources. Moreover, when it is operated as a three-level inverter, a unipolar PWM technique is applied to the circuit which shifts all the lower order harmonics to twice of switching frequency whereas in conventional multi-level inverters, all the harmonics of lower order are present around switching frequency. In addition, proposed inverter can operate even if some switching devices of the circuit fails. Also, the behavior of the inverter during the failure of some switching devices and DC source is analyzed. The proposed inverter is simulated in MATLAB/Simulink and the results are also discussed.

A New Boost Switched-Capacitor Multilevel Converter With Reduced Circuit Devices

In this paper, a novel platform for the single phase switched-capacitor multilevel inverters (SCMLIs) is presented. It has several advantages over the classical topologies, such as an appropriate boosting property, higher efficiency, lower number of required dc voltage sources, and other accompanying components with less complexity and lower cost. The basic structure of the proposed converter is capable of making nine-level of the output voltage under different kinds of loading conditions. Hereby, by using the same two capacitors paralleled to a single dc source, a switched-capacitor (SC) cell is made that contributes to boosting the value of the input voltage. In this case, the balanced voltage of the capacitors can be precisely provided on the basis of the series-parallel technique and the redundant switching states. Afterward, to reach the higher number of output voltage levels, two suggested SC cells are connected to each other with a new extended configuration. Therefore, by the use of a reasonable number of required power electronic devices, and also by utilizing only two isolated dc voltage sources, which their magnitudes can be designed based on either symmetric or asymmetric types, a 17- and 49-level of the output voltage are obtained. Based on the proposed extended configuration, a new generalized version of SCMLIs is also derived. To confirm the precise performance of the proposed topologies, apart from the theoretical analysis and a complete comparison, several simulation and experimental results are also given.

New Topology for Asymmetrical Multilevel Inverter: An Effort to Reduced Device Count

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.

A Unified Space Vector Pulse Width Modulation for Dual Two-level Inverter System

This letter proposes a unified space vector pulse width modulation (SVPWM) for a dual two-level inverter system with two isolated dc voltage sources. The gate pluses for the dual inverter are generated by the concept of one unified SVPWM in accordance with the voltage-second integral principle and the ratio of the two dc-link voltages can be an arbitrary positive value. This proposed technique also simplifies the region identification in sectors and reduces total switching frequency of the dual inverter. The beneficial performance of this proposed technique is verified experimentally.

Cascaded multilevel inverter using series connection of novel capacitor‐based units with minimum switch count

This paper presents a new family of cascaded multilevel inverters (CMLIs) which can generate a considerable number of output voltage levels with minimum number of required accompanying switching devices. Conceptually, each stage of proposed CMLI is composed of using a novel capacitor-based unit including two floating capacitors, one embedded dc voltage source and three power switches. In this case, the balanced voltage of integrated capacitors can be precisely provided as self-voltage balancing without using any auxiliary circuits, close loop systems and intricate modulation techniques. In addition, to reach different number of output voltage levels, four different algorithms pertaining to the symmetrical, binary asymmetrical, trinary asymmetrical and also hybrid patterns for determining the magnitude of isolated dc voltage sources are presented. Hereby, proposed hybrid structure is capable of working under mixed switching frequency without aiming the conventional full H-Bridge cell. Therefore, a high quality of output waveforms with reduced switching devices as well as power loss dissipation can be alternatively achieved. To confirm the validity of proposed CMLI, a complete comparison with several recently presented topologies besides several simulation and experimental results based on trinary asymmetrical and hybrid evolved structures will be also given.

Phase-Shifted Carrier Pulse Width Modulation Based on Particle Swarm Optimization for Cascaded H-bridge Multilevel Inverters with Unequal DC Voltages

High-voltage cascaded H-bridge multilevel (CHBML) inverters usually include many isolated dc voltage sources. Some dc source faults result in a drop in the dc voltage, thereby leading to unequal cell dc voltages. On the other hand, the differences in cell dc source parameters result in unequal dc voltages too. At present, riding through the faults of dc sources and operating under the condition of unequal dc voltages are required to improve the reliability of CHBML inverters. Unfortunately, the conventional phase-shifted carrier pulse width modulation (PSCPWM), which is widely used for CHBML inverters, cannot eliminate low-frequency sideband harmonics when cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM based on the particle swarm optimization algorithm. This modulation technique eliminates low-frequency sideband harmonics by calculating and regulating the carrier phases according to different cell dc voltages. The proposed PSCPWM enhances the reliability of the CHBML inverter and extends the range of its application. Simulation and experimental results obtained from the prototype of the CHBML inverter verify the theoretical analysis and the achievements made in this paper.

New Three-Phase Symmetrical Multilevel Voltage Source Inverter

This paper presents a new design and implementation of a three-phase multilevel inverter $(MLI)$ for distributed power generation system using low frequency modulation and sinusoidal pulse width modulation $(SPWM)$ as well. It is a modular type and it can be extended for extra number of output voltage levels by adding additional modular stages. The impact of the proposed topology is its proficiency to maximize the number of voltage levels using a reduced number of isolated dc voltage sources and electronic switches. Moreover, this paper proposes a significant factor $(F_{C/L})$ , which is developed to define the number of the required components per pole voltage level. A detailed comparison based on $F_{C/L}$ is provided in order to categorize the different topologies of the $MLI$ s addressed in the literature. In addition, a prototype has been developed and tested for various modulation indexes to verify the control technique and performance of the topology. Experimental results show a well-matching and good similarity with the simulation results.

Hybrid Multilevel Inverter Using Switched Capacitor Units

In this paper, two new topologies are proposed for multilevel inverters. The proposed topologies consist of a combination of the conventional series and the switched capacitor inverter units. The proposed topologies reduce the number of switches and isolated dc voltage sources, the variety of the dc voltage source values, and the size and cost of the system in comparison with the conventional topologies. In addition, the proposed topologies can double the input voltage without a transformer. There is no need for complicated methods to balance the capacitor voltage. The simulation and experimental results of single-phase 25- and 17-level inverters are given to prove the correct operation of the proposed topologies.

Three‐phase hybrid multilevel inverter with less power electronic components using space vector modulation

This study presents a new design and implementation of a three-phase hybrid multilevel inverter (MLI) using space vector modulation. The proposed MLI consists of a reduced number of dc sources and switches to minimise the control complexity. The developed topology consists of two stages: main stage and auxiliary stage. The main stage is a conventional three-phase inverter with one high-voltage input dc source and six switches. The auxiliary stages contain three individual cells. Each cell consists of two switches and one low-voltage input dc source. This topology is a modular type and without changing the previous connection it can be extended for more number of output voltage levels by adding certain number of auxiliary stages. A space vector modulation control technique has been utilised in order to generate different switching sequences. The special feature of the proposed system is its capability to maximise the number of voltage levels using a reduced number of isolated dc voltage sources and electronic switches. A prototype has been developed and tested for various modulation indexes to verify the control technique and performance of the topology. Experimental results validate the simulation results and the experimental results show a good similarity with the simulation results.

Carrier‐based pulse‐width modulation techniques for asymmetrical six‐phase open‐end winding drives

The study discusses development, implementation and performance of carrier-based pulse-width modulation (PWM) techniques for an asymmetrical six-phase open-end winding drive supplied by two two-level six-phase voltage source inverters (VSIs). The VSIs are fed from two equal and mutually isolated dc voltage sources, so that the same performance as with a three-level VSI in single-sided supply mode can be achieved. The considered modulation techniques are the in-phase disposition (PD-PWM) and the alternate phase opposition disposition, which are both classified as level-shifted PWM methods, and the phase-shifted PWM method. The performance is studied and compared using computer simulations and experiments undertaken on a laboratory prototype. It is shown that, in contrast to the three-phase and five-phase cases, the PD-PWM method does not offer the best performance.

Research on cascade multilevel inverter with single DC source by using three-phase transformers

One of the most significant recent advances in power electronics is the multilevel inverter. Using this concept the power conversion is performed with enhanced power quality. In this scenario cascade H-bridge multilevel inverter (CHBMLI) is an exceptional one and it has many inherent benefits like: (1) its modular structure, (2) it can be easily implemented through the series connection of identical H-bridges, (3) generate near sinusoidal voltages with only fundamental frequency switching and finally and (4) no electromagnetic interference or common-mode voltages. This flexibility has resulted CHBMLI topology in various applications like medium-voltage industrial drives, electric vehicles and the grid connection of photovoltaic-cell generation systems. But one of the major limitations of the cascade multilevel converters is requirement of isolated dc voltage sources for each H-bridge, this increases the converter cost and reduces the reliability of the system. This drawback is the key motivation for the present work. The present paper investigates different cascade multilevel inverter (CMI) based topologies with reduced dc sources and finally the proposed CMI with single dc source by employing low frequency transformers is presented. Proposed topology significantly reduces size when compared with conventional topologies and increases the reliability. To verify the performance of proposed architecture, prototype experiments are carried out and adequate results are presented.

A Voltage Space Vector Diagram Formed by Six Concentric Dodecagons for Induction Motor Drives

A new voltage space vector diagram consisting of six concentric dodecagons is proposed in this paper. The space vector diagram is developed for an open-end induction motor drive fed from two three-level neutral point clamped (NPC) inverters with asymmetric isolated dc voltage sources. As already reported in literature, a dodecagonal space vector diagram is advantageous over a hexagonal one, since the 6n ± 1 (n = odd) harmonics are absent in the phase voltage and the linear modulation range is extended. The present work further improves the existing dodecagonal space vector diagrams by dividing the space vector plane into six concentric dodecagons, while retaining the aforementioned advantages. A high-resolution pulsewidth modulation strategy is developed in this paper, which compared to existing schemes, reduces the harmonic content of the motor phase voltage without resorting to higher switching frequency. A comparative study of output voltage quality produced by the proposed topology and a five-level inverter shows substantial improvement in the present work. At the same time, the present topology does not require any special design of the inverter and uses two popular three-level NPC inverters. Experimental verification on a laboratory prototype indicates the possible application of this concept for high power drives.

A Novel Four-Level Voltage Source Inverter—Influence of Switching Strategies on the Distribution of Power Losses

In this paper, a novel four-level inverter will be presented and analyzed. The proposed inverter topology, which is composed of a conventional two-level and a three-level neutral-point clamped (NPC) inverter, is suitable for high-voltage and high-power applications. The proposed inverter, when it is compared with the conventional four-level NPC pulsewidth modulation inverter, exhibits the following advantages: a) ability of changing the power losses distribution profile among the devices by selecting a suitable switching strategy; b) reduction of total inverter power semiconductor device losses; c) ability of bidirectional operation for all power semiconductor switches; and d) easy implementation using existing power semiconductor modules. The effect of conduction and switching losses profiles of the proposed inverter for different switching strategies is examined under different loads, power factors, and modulation indices. The dc-link capacitors voltages are effectively balanced via a proposed self-voltage balancing topology, without the need of isolated dc voltage sources or additional voltage stabilizing circuits. Finally, the theoretical results are confirmed by simulation and experimental results