Hybrid Multilevel Inverter Using Switched Capacitor Units

This work proposes a new multilevel inverter consisting of basic and submultilevel units. The basic unit is made-up of four isolated dc voltage sources, two bidirectional switches and ten unidirectional switches. To increase the number of the output voltage levels, a cascaded architecture based on series connection of sub-multilevel is proposed. The proposed inverter utilizes two algorithms to determine the values of dc voltage sources. Number of IGBTs, dc voltage sources, gate driver circuits, variety of dc voltage sources and peak standing voltage on the switches are calculated and their optimization to produce maximum number of levels in output voltage is investigated. To examine advantages of the proposed inverter, the topology is compared with other topologies. The results show superiority of proposed topology over most conventional topologies, in number of circuit components. Finally, to confirm the performance of the proposed multilevel inverter, experimental results of a 25-level inverter prototype are provided.

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.

In this paper, two new topologies of multilevel inverters based on the series and parallel connection of dc voltage sources are proposed. The optimal topologies with minimum number of switches and dc voltage sources are computed to produce the maximum number of output voltage levels with minimum blocked voltage by switches. The proposed topologies are compared with some conventional topologies. The proposed topologies have been verified from viewpoint of the number of switches, number of dc voltage sources and the maximum blocked voltage by switches. Finally, to verify the theoretical issues, the simulation results for single-phase 17-level and 41-level inverters are presented. In addition, the experimental results of a single-phase 17-level inverter are given to prove the correctness operation of the proposed topologies.

A new switched‐capacitor‐based topology with features of boosting and self‐voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched‐capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

In this paper, a novel platform for the single phase switched-capacitor multilevel inverters (SCMLIs) is presented. It has several advantages over the classical topologies, such as an appropriate boosting property, higher efficiency, lower number of required dc voltage sources, and other accompanying components with less complexity and lower cost. The basic structure of the proposed converter is capable of making nine-level of the output voltage under different kinds of loading conditions. Hereby, by using the same two capacitors paralleled to a single dc source, a switched-capacitor (SC) cell is made that contributes to boosting the value of the input voltage. In this case, the balanced voltage of the capacitors can be precisely provided on the basis of the series-parallel technique and the redundant switching states. Afterward, to reach the higher number of output voltage levels, two suggested SC cells are connected to each other with a new extended configuration. Therefore, by the use of a reasonable number of required power electronic devices, and also by utilizing only two isolated dc voltage sources, which their magnitudes can be designed based on either symmetric or asymmetric types, a 17- and 49-level of the output voltage are obtained. Based on the proposed extended configuration, a new generalized version of SCMLIs is also derived. To confirm the precise performance of the proposed topologies, apart from the theoretical analysis and a complete comparison, several simulation and experimental results are also given.

Electrical energy plays a vital role in the life of mankind due to extensive use of electronic devices and electrical machinery. To provide green energy to user, renewable energy got more importance. Conventionally, renewable energy was used in standalone systems which need heavy capital investment along with high maintenance cost and separate infra-structure. Meanwhile the trend has been changed and the grid tie inverters got into the systems. There are many issues in finding a suitable grid tie inverter because it needs high power inverters. The latest technique for inverter of high power and low total harmonic distortion is Multilevel Inverter. There are many inverters designing topologies of Multilevel Inverters. One of the most popular among these topologies is Cascaded H-Bridge Multilevel Inverter. But this topology comes with a limitation that it needs isolated DC voltage sources. In our research, we have focused on the topology to overcome this issue in case when there is a single available DC voltage source. Our research shows that this DC source can easily be split into a number of isolated DC Sources as per desire by using less in system losses, small size and weight of the converter. The design has been demonstrated by simulation and verified by hardware implementation.

This paper presents a modified topology for asymmetric modular multilevel inverter as a fundamental block. It consists of eight switches (including six bidirectional-conducting unidirectional-blocking switches and two bidirectional-conducting bidirectional-blocking switches) and four DC sources with unequal magnitudes, which generates 13-level output voltage. The proposed topology offers special features such as reduced number of switches, isolated DC sources, economical and less complexity with modular structure as compared to other contemporary topologies. Moreover, significant reduction in switch voltage can be achieved. The comparative study of proposed topologies with the conventional and recent topologies have been presented in terms of power switches, gate drivers, isolated DC voltage sources and total standing voltage on the switches. A multicarrier-based sinusoidal pulse width modulation scheme is adopted for generating the gate pulses using real-time simulation with dSPACE DS 1104. The proposed topology offers a fewer number of ON-state switches which lead to the reduction in power loss. The feasibility of proposed multilevel inverter, the simulation and experimental results are analysed under steady state and dynamic states.

Multilevel inverter (MLI) topologies are popularly used in medium-voltage, high-power applications in recent years. This is because of effective advantages of multilevel inverter such as less Total Harmonic Distortion (THD) in output voltage, higher efficiency, less stress on semiconductor power switches. In this study, new structure of MLI that uses reduced number of controlled switches, power diodes, and DC voltage sources compared to conventional MLI topology has been simulated. Topology-I is capable of producing seven, nine and eleven levels of output voltage with seven switches and topology-II can produce seventeen levels with eight switches only. A comparison of this topology with the conventional topologies has been made in terms of controlled switches, power diodes, and DC voltage sources. Nearest level control technique has been used to generate the switching pulses. Simulation of the topologies has been carried out using MATLAB/Simulink.

This paper introduces a hybrid topology for multilevel inverter that operates in asymmetric manner. The proposed topology is generalized using series connection of basic module. It offers less number of switches and isolated dc voltage sources as compared to conventional and recent proposed topologies. Carrier based level shift sinusoidal pulse width modulation scheme is adopted for generating switching signals. To verify the performance of proposed topology, a prototype of single phase 11-level inverter has been developed and tested. Also 11-level and 23-level inverter are simulated using MATLAB/SIMULINK environment and validated experimentally.

This paper proposes a new hybrid nine-level inverter topology for IM drive. The nine-level structure is realized by using two three-phase two-level inverters fed by isolated DC voltage sources and six H-bridges fed by capacitors. The number of switches required in this topology is only 36 where as the conventional nine-level topologies require 48 switches. The voltages across the capacitors, feeding the H-bridges that operate at asymmetric voltages, are effectively balanced by making use of the switching state redundancies. In this topology, the requirement of DC link voltage is only half of the maximum magnitude of the voltage space vector. As the two-level inverters are powered by isolated voltage sources, the circulation of triplen harmonic current in the motor winding is prevented. The proposed drive system is capable of functioning in three-level mode in case of any switch failure in H-bridges. The performance of the proposed topology in the entire modulation range is verified by simulation study and experiment.

The interest in development of newer topologies of multilevel inverter has been increasing rapidly in past few years. Recently introduced topologies achieve higher number of output voltage steps with reduced number of switches, DC voltage sources, voltage stress across switches and losses as compared with the conventional topologies. In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers reduced number of controlled switches, power diodes and DC sources as compared with classical and recently proposed topologies in the literature. Reduction of switch count and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Proposed topology is capable of producing 7, 9 and 11 levels of output voltage with seven switches only. Moreover, significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topology with the conventional topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi‐carrier pulse‐width modulation strategy is adopted for generating the switching pulses. Simulation study of the proposed topology has been carried out using Matlab/Simulink and feasibility of topology has been validated experimentally.

In this paper, a new multilevel inverter topology which can be operated in both symmetrical and asymmetrical configurations has been proposed. In order to produce all steps of voltage at output, four different algorithms are proposed to find the value of DC sources. The proposed topology reduce switch count, gate driver circuits, total voltage blocking capability and isolated DC voltage sources which leads to reduction in installation space and cost. For switching purpose multiple carrier PWM strategy has been used. Simulation results have been presented for 9-level, 17-level and 53-level operation of proposed inverter using MATLAB/SIMULINK software and the feasibility of topology has been validated experimentally.

In the modern set up of generation, transmission, distribution and electric power utilization, dc to ac power conversion is a very important technology and multilevel inverter are the best choice for this converion as it has many advantages over two level inverter. In this paper, a new asymmetrical multilevel inverter topology for 7-level inverter is proposed which requires less number of switches, driver circuits and dc voltage sources as compared to other asymmetrical topologies and conventional multilevel inverter topologies. In the proposed topology, six power electronic switches and two dc voltage sources are required for generating 7-level in single phase output voltage. Performance of the proposed topology to generate positive, zero and negative level have been evaluated in terms of Total Harmonic Distortion (THD) in the output voltage using simulation in MATLAB environment. To validate the performance of proposed topology various waveforms and simulation results are presented in the paper. Fundamental switching control technique is used to operate the various switches.

High-voltage cascaded H-bridge multilevel (CHBML) inverters usually include many isolated dc voltage sources. Some dc source faults result in a drop in the dc voltage, thereby leading to unequal cell dc voltages. On the other hand, the differences in cell dc source parameters result in unequal dc voltages too. At present, riding through the faults of dc sources and operating under the condition of unequal dc voltages are required to improve the reliability of CHBML inverters. Unfortunately, the conventional phase-shifted carrier pulse width modulation (PSCPWM), which is widely used for CHBML inverters, cannot eliminate low-frequency sideband harmonics when cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM based on the particle swarm optimization algorithm. This modulation technique eliminates low-frequency sideband harmonics by calculating and regulating the carrier phases according to different cell dc voltages. The proposed PSCPWM enhances the reliability of the CHBML inverter and extends the range of its application. Simulation and experimental results obtained from the prototype of the CHBML inverter verify the theoretical analysis and the achievements made in this paper.

Multi-level inverters are playing a major role in PV based systems because of numerous advantages like low dv/dt, better harmonic profile so on. But, conventional multi-level inverters consist of some drawbacks like capacitor balancing issues, greater requirement of capacitor banks and clamping diodes. To address these issues, a novel multi-level inverter has been presented in this paper, which can function as a seven-level, five-level and three-level inverter. The inverter circuit utilizes six switching devices and two isolated DC voltage sources. Moreover, when it is operated as a three-level inverter, a unipolar PWM technique is applied to the circuit which shifts all the lower order harmonics to twice of switching frequency whereas in conventional multi-level inverters, all the harmonics of lower order are present around switching frequency. In addition, proposed inverter can operate even if some switching devices of the circuit fails. Also, the behavior of the inverter during the failure of some switching devices and DC source is analyzed. The proposed inverter is simulated in MATLAB/Simulink and the results are also discussed.