IR Drop Research Articles

32‐3: AMOLED IR Drop Compensation for Channel Length Modulation

This paper proposed a new approach to compensate IR‐Drop on AMOLED panel for CLM (channel length modulation). IR drop will cause the luminance non‐uniformity problem. Moreover, the interaction between IR‐Drop and CLM make the phenomenon worse. If we compensate IR‐Drop but ignore CLM, the color shift happened even though the brightness uniformity gets better. Therefore, CLM compensation value must be analyzed and applied to solve this problem. Experimental results show that our approach improve color shift and keep the brightness uniformity.

Nucleation of Tetrakis(4-chlorophenyl)borate at micro liquid-liquid interface

Micro Interface between Two Immiscible Electrolyte Solutions (micro-ITIES) has a sensitive detection capability and is suitable for measuring the fast kinetics of charge transfer according to its low IR drop and charging current. In most previous studies, some of extra hydrophobic salts including tetrakis(4-chlorophenyl)borate, tetrakis(pentafluorophenyl)borate and tetraphenylborate were often used as organic electrolytes as they were hardly transfer into aqueous solution and then provide a sufficiently stable potential windows. However, in this manuscript, it was discovered that intense spike-liked current signals appeared at high potential when hydrochloric acid and tetrakis(4-chlorophenyl)borate were served as the water and 1,2-dichloroethane phase electrolyte, respectively. The exceptional current spikes might belong to the heterogeneous nucleation at the interface, which surely interfered with related analysis on interface, i.e. single nano entity detection. Thus, the potential factors, which might affect the nucleation on micro-ITIES, including interface diameter, concentration and applied potential were investigated to prove that the current spikes were induced by the collision of nuclei produced by contact of hydrogen ion from aqueous phase and tetrakis(4-chlorophenyl)borate from organic phase. Moreover, lithium ion and potassium ion were also found to nucleate with tetrakis(4-chlorophenyl)borate at the positive end of potential window. In general, the potential nucleation problem on micro-ITIES was revealed and it was also suggested that appropriate conditions to avoid heterogeneous nucleation caused by ion transfer reaction of supporting electrolytes should be chosen for other researchers. • Single nucleation impact of tetrakis(4-chlorophenyl)borate at ITIES was discovered. • Factors of nucleation impact was investigated through single-entity analysis. • The potential mechanism of nucleation at interface was speculated. • The potential influences in micro interfacial electrochemical studies were proposed.

Cotton fabrics-derived flexible nitrogen-doped activated carbon cloth for high-performance supercapacitors in organic electrolyte

Activated carbon cloth, due to its excellent flexibility, good conductivity, and high surface area, is featured as a kind of promising material for energy storage devices. However, the non-optimized pore structures limit its application as electrode material in supercapacitors with organic electrolytes, which can provide both high energy density and power density due to the high applied cell voltage. In this paper, nitrogen-doped activated carbon cloth with hollow tubular fiber units, high surface area, controllable hierarchical porous structure, and beneficial surface functional groups, is synthesized via a simple ammonia treatment of commercial cotton fabrics. The resulting organic-electrolyte supercapacitors based on this hierarchical porous hollow carbon cloth exhibit a high specific capacitance (up to 215.9 F g−1 at 1 A g−1), extremely high rate capability (89% from 1 A g−1 to 200 A g−1), small IR drop (0.23 V at 100 A g−1), outstanding cycling stability (98% capacitance retention over 20 000 cycles), as well as good flexibility. This N-doped activated carbon cloth thus overcomes the drawbacks of presently available carbon cloths and opens up a new horizon toward energy storage devices with high energy density at high power density.

Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory

Resistive memory is promising to be constructed as a high-density storage-class memory. Multilevel cell, access-transistor-free cross-point array structure, and 3-D array integration are three approaches to scale up the density of resistive memory. However, composing the three approaches together strengthens the interactions between array-level and cell-level nonidealities (interconnect resistance-induced IR drop, sneak current, and device variability) of resistive memory arrays during write operations and significantly degrades write performance and reliability. In this article, we analyze the dynamic voltage-dividing effect along a selected write current path in 3-D cross-point memory arrays. We propose a nonideality-tolerant high-density resistive memory (HD-RRAM) architecture, that can weaken the interactions between nonidealities and mitigate their degradation effects on the performance and reliability of array multilevel write operations. HD-RRAM is equipped with a double-transistor array architecture with two-transistor- $n$ -resistor (2TnR) cell organization along pillars to reduce the current driving requirement and the large undesired voltage drop across each vertical pillar access transistor. Moreover, multiside asymmetric bias improves the resistive switching velocity by leveraging current-dividing effects. Variability-aware multilevel state partition reduces the worst-case write error rate by leveraging target state dependency of variability. Proportional-control multilevel state tuning reduces the average number of required write-and-verify iterations by leveraging pulse amplitude dependency of variability. Multilevel cell parallel writing improves the cell-level parallelism by leveraging the pass-through feature of intermediate resistance states. The evaluations show that HD-RRAM reduces both memory access latency and energy consumption over an aggressive baseline.

Estimation of Potential Distribution during Crevice Corrosion through Analysis of I-V Curves Obtained by LAPS.

Crevice corrosion is a type of local corrosion which occurs when a metal surface is confined in a narrow gap on the order of 10 μm filled with a solution. Because of the inaccessible geometry, experimental methods to analyze the inner space of the crevice have been limited. In this study, a light-addressable potentiometric sensor (LAPS) was employed to estimate the potential distribution inside the crevice owing to the IR drop by the anodic current flowing out of the structure. Before crevice corrosion, the I–V curve of the LAPS showed a potential shift, depending on the distance from the perimeter. The shift reflected the potential distribution due to the IR drop by the anodic current flowing out of the crevice. After crevice corrosion, the corrosion current increased exponentially, and a local pH change was detected where the corrosion was initiated. A simple model of the IR drop was used to calculate the crevice gap, which was 12 μm—a value close to the previously reported values. Thus, the simultaneous measurement of the I–V curves obtained using a LAPS during potentiostatic electrolysis could be applied as a new method for estimating the potential distribution in the crevice.

SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage

Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die that does not cause SRAM read and write failures, which are majorities of SRAM failures, under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, Vfail, that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM Vˆddmin on each die from the measured Vfail of SRAM monitor on the same die where Vfail-Vddmin correlation table is built-up in design infra development phase, and Vˆddmin can be directly derived from the measured Vfail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 10.45%, read energy by 4.99%, and write energy by 5.45% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint. In addition, the effect of IR drop and process variations of peripheral circuit on Vddmin prediction is taken into account by reflecting them on SRAM bitcell operation. We also solidify our Vddmin prediction methodology by considering the prevention of potential SRAM access failures for high-speed designs as well as the SRAM read and write failures.

Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage

Resistive cross-point memory arrays can be used to construct high-density storage-class memory. However, coupled IR drop and sneak currents cause multidimensional non-uniformity of cell effective voltage in cross-point arrays. The voltage non-uniformity significantly degrades write performance on cross-point memory if only adopting the worst-case write latency at partial dimensions. Furthermore, the non-uniformity of cell effective voltage in cross-point arrays depends on multidimensional dynamic write operation parameters: row, column as well as layer address, the number of selected cells, and the number of half-selected low-resistance state cells. In this article, we aim to improve the write performance by leveraging multidimensional non-uniformity of cell effective voltage. First, we analyze the impact of multidimensional write parameters on effective voltage and write latency. Then, we design the memory array write scheme that measures the write parameters and sets the write latency accordingly. We further analyze the features and effects of interlayer sneak currents and extend the scheme to 3D cross-point memory. The evaluation shows that the proposed memory array write scheme can reduce the memory access latency by 75.6 and 64.1 percent, and improve the system performance by 4.5 times and 3.4 times on average, compared with the baseline and the state-of-the-art approach, respectively.

Effect of IR Drop on Reinforced Concrete Corrosion Measurements

The ohmic voltage drop (IR) due to the high resistivity of concrete needs to be considered while monitoring the corrosion performance of rebar embedded in concrete. It helps to evaluate the corrosion condition precisely. Concrete mixes were contaminated with chlorides, sulphates, and a combination of chloride plus sulphate solutions as mix water. To assess the IR drop error in corrosion measurements caused by concrete with different salts, linear polarization resistance values were measured with and without IR compensation. The results indicate that the concrete contaminated with 5% of chloride has shown higher error as compared to 2% of sulphates, due to high corrosion current density. However, from the results of chloride and chloride plus sulphate contaminated concrete, it is also confirmed that the IR drop error is not absolute to determine the solution resistance. The higher corrosion in chloride contaminated concrete as compared to chloride plus sulphate contaminated concrete is also observed due to the availability of high chloride concentration. The results of the present study are suggested that the IR drop compensation should be considered when the reinforced structures are exposed to chloride and sulphate environment.

Signal Integrity Design and Analysis of 3-D X-Point Memory Considering Crosstalk and IR Drop for Higher Performance Computing

In this article, we, for the first time, used signal integrity (SI) to design and analyze 3-D X-Point memory, including a phase-change memory (PCM) cell, ovonic threshold switch (OTS) selector, interconnection lines, and peripheral circuits. With the narrow space and the long interconnection lines that come with 20-nm process technology, crosstalk and IR drop can degrade the voltage margin of the memory cell and affect the memory operation. For SI analysis considering crosstalk and IR drop, the unit size of the memory array tile was considered in designing the interconnection lines. Crosstalk and IR drop are analyzed using full 3-D electromagnetic and circuit simulations. To cover practical conditions, the PCM cell and OTS selector are modeled as behavior models using Verilog-A modules, respectively. Also, the word lines (WLs) and bit lines (BLs) of 3-D X-Point memory are modeled to resistance and capacitance by ANSYS Q3D extractor. The core peripheral circuits, such as decoder, sense amplifier, and analog-to-digital converter, are included in the circuit simulation. To verify the proposed design and analysis, a transient simulation was conducted considering crosstalk and IR drop of 3-D X-Point memory. A tradeoff relationship between crosstalk and IR drop in the interconnection designs was verified. Additionally, to suppress crosstalk and reduce IR drop, the new design of the interconnection lines considering the tradeoff between SI issues is proposed. The newly proposed interconnection design shows 30% improvement in the voltage margin considering the IR drop issues and under 10% enhancement of crosstalk noise. It is expected that the SI analysis and design methodologies could be widely applied in other new memory developments.

An AMOLED Pixel Circuit Based on LTPS Thin-film Transistors with Mono-Type Scanning Driving

Using low-temperature poly-silicon thin-film transistors (LTPS TFTs) as a basis, a pixel circuit for an active matrix organic light-emitting diode (AMOLED) with narrow bezel displays was developed. The pixel circuit features mono-type scanning signals, elimination of static power lines, and pixel-integrated emitting control functions. Therefore, gate driver circuits of the display bezel can be simplified efficiently. In addition, the pixel circuit has a high-resolution design due to an increase of the pulse width of the scan signal to extend the threshold voltage and internal–resistance drop (IR drop) detection period. Further, regarding the influences of process–voltage–temperature (PVT) variation in the pixel circuit, comparison investigations were carried out with the proposed circuit and other pixel circuits with mono-type scanning signals using Monte Carlo analysis. The feasibility of the proposed pixel circuit is well demonstrated, as the current variations can be reduced to 2.1% for the supplied power reduced from 5 V to 3 V due to IR drop, and the current variation is as low as 10.6% with operating temperatures from –40 degrees to 85 degrees.

EMSpice: Physics-Based Electromigration Check Using Coupled Electronic and Stress Simulation

In this article, a novel full-chip EM simulation tool, called EMSpice simulator is proposed. The new method starts from first principles and simultaneously considers two major interplaying physics effects in EM failure process: the hydrostatic stress and electronic current/voltage in a power grid network. The new tool starts by reading the power grid layout information from Synopsys IC Compiler. It then removes immortal interconnect wires by considering both nucleation phase immortality and incubation phase immortality for multi-segment interconnects. Thereafter, a finite difference time domain (FDTD) solver is employed for stress analysis for every mortal interconnect tree for both nucleation and post-voiding phases. At the whole power grid circuit level, the EM analysis is coupled with IR drop analysis of a whole power grid network at each time step so that we can consider the interaction among stress, void growth, resistance change and IR drop in a single simulation framework. Accuracy of EMSpice is validated by comparing with a published EM simulator, XSim, for nucleation phase, and finite element method based COMSOL for post-voiding phase. The comparison results show that EMSpice agrees well with both methods with. Experimental results on two practical processor chip designs show that the proposed coupled EM-IR drop analysis method can further reduce the overly conservative EM-aware power grid design as the number of the failed trees found by EMSpice simulator is up to 76.7% less than the Black's method and 66.7% less than a recently proposed full-chip EM analysis method respectively. Furthermore EMSpice simulator is the least conservative one for lifetime estimation of individual tree wires among the three methods.

위성용 전장품 탑재보드의 Power Integrity 및 Signal Integrity 설계 분석을 통한 노이즈 성능 개선

본 연구에서는 위성용 전장품 보드의 성능 요구조건과 설계 복잡도가 높아지면서 증가되는 노이즈 문제를 최소화하기 위해 전원 건전성(Power Integrity) 및 신호 건전성(Signal Integrity)의 설계분석이 수행되었고 이를 통해 적용된 설계 개선 내용을 기술하였다. 전원 건전성은 정전류 전압강하(DC IR drop) 해석을 통해 정적 전원의 특성을 분석하였고, 각 전원의 임피던스 해석을 통해 동적 전원의 특성을 분석하여 각 분석 결과를 이용한 설계 개선 방안들이 적용되었다. 신호 건전성 측면에서는 주요 데이터버스 신호에 대한 시간영역 파형 분석과 PCB(Printed Circuit Board) 설계수정을 통해 노이즈가 개선된 결과를 확인하였다. 또한 설계된 PCB 보드의 전원 층에 대한 공진모드를 분석하여 발생된 공진 영역들에 완화 조치를 적용하였고 조치결과를 시뮬레이션을 통해 확인하였다. 최종적으로 분석을 통해 설계 개선이 적용된 유닛에 대해 수정 전과 후의 EMC(Electro Magnetic Compatibility) RE(Radiated Emission) 노이즈 측정결과를 비교함으로써 방사성 노이즈가 감소되었음을 확인하였다.

“Wrapped” nitrogen-doped defective reduced graphene oxide (ND-rGO): A virtual electron bed for enhanced supercapacitive charge storage in stepped-surfaced-NiCo2O4/ND-rGO||Bi2O3 asymmetric device

In the context of low impedance electron transfer in electrochemical charge storage devices, stepped-surfaced solids are important because they provide low work function and suitable interface for electron transfer. Contextually, in this work, for the first time, a carbonate-assisted synthesis method is adopted to fabricate severely stepped-surfaced porous NiCo2O4. Further, N-doped defective rGO (ND-rGO) wrapped NiCo2O4 is assembled, and the electron bedding effect of ND-rGO on the supercapacitive charge storage performance of NiCo2O4 is thoroughly studied. The physicochemical studies authenticate restricted crystal growth of NiCo2O4 on ND-rGO and chemical bonding between ND-rGO and NiCo2O4. Detailed electrochemical studies using cyclic voltammetry (CV), galvanostatic charge-discharge (GCD) and electrochemical impedance spectroscopy (EIS) techniques show redox-mediated charge storage in NiCo2O4, ND-rGO-induced enhanced high-rate supercapacitive charge storage and lower charge-transfer resistance, equivalent series resistance and Warburg resistance in NiCo2O4/ND-rGO heteronanocomposite. Further, for the first time, Bi2O3 was used as a super compatible negative electrode material to fabricate asymmetric supercapacitor (ASC) devices based on pristine NiCo2O4 and NiCo2O4/ND-rGO, and in depth electrochemical characterizations show redox-capacitive charge storage behaviour in both the devices. The NiCo2O4/ND-rGO||Bi2O3 demonstrates 2-times more areal capacitance at extreme rate condition, lower iR drop, very low charge transfer resistance, solution resistance and ion-diffusion resistance, as compared to NiCo2O4||Bi2O3 ASC device. The NiCo2O4/ND-rGO||Bi2O3 ASC device also retains a very high 93.1% of specific capacitance after 5000 GCD cycles at an extreme applied current density of 32 mA cm−2. Further, the NiCo2O4/ND-rGO||Bi2O3 offers twice the energy density as compared to NiCo2O4||Bi2O3 ASC device, at elevated power density up to ∼10,000 Wh kg−1. The enhanced supercapacitive performance of NiCo2O4/ND-rGO||Bi2O3 ASC device is ascribed to electron bedding effect of wrapped ND-rGO which provides a continuous conducting network, ND-rGO induced improved wettability, activated NiCo2O4|ND-rGO interface, and excellent electromechanical properties of NiCo2O4/ND-rGO heteronanocomposite.

Closed bipolar electrochemical biosensor based on ohmic loss mechanism for noncontact measurements

Resistance is of great importance for controlling the current flow through bipolar electrodes (BPEs) and the electrochemiluminescence (ECL) signal at the BPE anode. In this work, we firstly studied the effect of the iR drop between the BPE cathode and anode on the electrochemical performance of a closed BPE device. Due to the significant iR loss between the two poles of the BPE, an increased external voltage, applied on the driving electrodes, was required to trigger the redox reactions at the BPE. Accordingly, the peak voltages (forward and reverse scan) shifted to larger values, whereas the current flow through the BPE was remarkably reduced. Moreover, these factors were closely dependent on the concentration of Fe(CN)63−/Fe(CN)64−, the scan rate, and the resistance wired between glassy carbon electrodes (GCEs). Principally, it was proven that the peak-to-peak separation was enlarged as the scan rate and the concentration of Fe(CN)63−/Fe(CN)64− increased, even when the resistance between the two BPE poles was zero, indicating that the ohmic effect of the electrochemical cell is significant. Excellent linear relationships could be observed between the peak voltages and the resistance, enabling the designation of novel biosensors by connecting sensing units with tunable resistance between the GCEs. The noncontact electrochemical measurement could therefore be promising in biosensing applications.

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS

A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core microprocessor to reduce errors due to IR drops. A voltage regulator controller (VREGC) compares the voltages at various points on the grid to a programmable reference and delivers a set of corrective 2-b up/down (UP/DN) codes (global feedback) to the distributed uREGs across the core. Inside each uREG, the UP/DN codes control a local charge pump that sets the reference for an asynchronous comparator that turns on and off a pMOS passgate with a sub-nanosecond response. To mitigate the self-generated ripple, hybrid fast/slow passgate control is employed, whereby a parallel pMOS passgate with a slew-rate-limited gate drive is used to supply the dc portion of the load current. The distributed regulator architecture includes a scheme for limiting the degree of load-sharing imbalances among its uREGs due to the VREGC comparator offsets. Adding a switched-capacitor (SC) accelerator to the charge pump of each uREG speeds up the output-voltage transitions by up to 17 $\times $ for greater dynamic voltage and frequency scaling (DVFS) savings. Line and load regulations are 9 mV/V and 1.1 mV/A, respectively. The regulator achieves a peak power efficiency of 95.2% and a peak current efficiency of 99.1%. It reaches a peak power density of 82.3 W/mm2.

Enhanced Power and Ground Mesh Structure for IR-Drop Reduction

New enhanced power/ground mesh structure is presented for voltage drop (IR drop) reduction on power distribution network in integrated circuits (ICs). The new structure focuses on the length of the overall power/ground mesh wire pattern, reducing it by using a complex dotted line wire pattern instead of the usual mesh straps, which brings to wire length reduction on almost 40%, while via count on changed metal layer remained the same. Measurements of the voltage drop prove that with proposed mesh structure IR drop reduced about 76% for power net compared to standard mesh structure but runtime for mesh creation is increased due to more complex patterns. Proposed structure can be used in advanced technology nodes where IR drop phenomenon has become critical for performance of the ICs.

IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays

Resistive Crossbar Arrays present an elegant implementation solution for Deep Neural Networks acceleration. The Matrix-Vector Multiplication, which is the corner-stone of DNNs, is carried out in $O(1)$ compared to $O(N^{2})$ steps for digital realizations of $O(log_{2}(N))$ steps for in-memory associative processors. However, the IR drop problem, caused by the inevitable interconnect wire resistance in RCAs remains a daunting challenge. In this article, we propose a fast and efficient training and validation framework to incorporate the wire resistance in Quantized DNNs, without the need for computationally extensive SPICE simulations during the training process. A fabricated four-bit Au/Al2O3/HfO2/TiN device is modelled and used within the framework with two-mapping schemes to realize the quantized weights. Efficient system-level IR-drop estimation methods are used to accelerate training. SPICE validation results show the effectiveness of the proposed method to capture the IR drop problem achieving the baseline accuracy with a 2% and 4% drop in the worst-case scenario for MNIST dataset on multilayer perceptron network and CIFAR 10 dataset on modified VGG and AlexNet networks, respectively. Other nonidealities, such as stuck-at fault defects, variability, and aging, are studied. Finally, the design considerations of the neuronal and the driver circuits are discussed.

Static IR Drop Estimation on the Power Network

This paper presents a power consumption estimation algorithm for static analysis. IR drop is being calculated for each separated node, which makes this algorithm favorable for IR drop calculation on infinite power network. The power consumption is being calculated using random walk algorithm, which includes Monte Carlo simulation method for increasing accuracy of estimation. For power mesh with 150 k power nodes, total IR drop calculation takes 152.17 seconds.

CMOS Backplane Pixel Circuit With Leakage and Voltage Drop Compensation for an Micro-LED Display Achieving 5000 PPI or Higher

Micro-displays based on micro-LEDs are becoming more and more attractive in AR/MR (Augmented/Mixed Reality) applications. A display size of 0.5 to 0.7-inch is preferred, with 5,000 PPI (Pixel Per Inch) or higher. Due to this pixel density and size, a CMOS (Complementary Metal-Oxide-Silicon) backplane is an ideal solution to drive these pixelized micro-LEDs. As the required pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging. The simplest 2T1C (2 transistors & 1 capacitor) pixel circuit has potential problems, due to the leakage current of the switch transistor and the voltage drop on the matrix array layout. In this paper, a pixel circuit is proposed as a solution to overcome these two issues. Our simulation results show that the variation of the driving current to the LED is improved by 95 %, and the IR drop error rate is around 2.2 % compared to the 2T1C circuit. The test results also show that the error rate of IPIXEL for the whole region of display is under 2.5 %. This work is verified using a test chip implementation with 180 nm CMOS process technology.

A novel diagnostic technique to detect the failure mode operating states of an air-breathing fuel cell used in fuel cell vehicles

The world is at a cusp of major transition to fuel cell technology. Water management is of prime importance in air-breathing fuel cells (ABFCs). Inadequate water management leads to the dehydration or flooding which affects the performance of fuel cell. The paper addresses the issues of water management in ABFC by a novel method. Understanding of flooding and dehydration states is presented through experimental investigations. Experiments are conducted at various operating conditions to identify dehydration, normal or flooding states using easily measurable parameters like cell temperature, voltage and current. Preliminarily, by considering iR drop as a distinguishing parameter, dehydration and flooding operating states are distinguished.