Processor IP Research Articles

Memory Efficient Hash-Based Longest Prefix Matching Architecture with Zero False +ve and Nearly Zero False -ve Rate for IP Processing

A novel hash-based hardware architecture for longest prefix match (LPM) scheme has been presented for IP processing.The main idea is to have zero false positive (+ve) rate with negligible false negative (-ve) rate. This has been achieved by implementing hardware-based simple hash functions for faster generation of routing table addresses. Prefix table has been designed using multiple read-port memory modules to deploy concurrent access of multiple memory words. Moreover, in this architecture, memory requirement has been reduced by maintaining next-hop address pointers instead of keeping actual next-hop address using global next-hop address memory. Prefix search time is fixed and restricts an LPM search operation within a single clock cycle irrespective of IPv4 and IPv6 address suits. This architecture can accommodate increased prefix growth trend of 40% – 100% with unchanged memory capacity. After rigorous testing, false -ve rate is found mostly zero and reasonably negligible (0.00512%) in worst-cases, however, false +ve rate is always zero. Lower bounds in memory requirements for four numerous schemes of the proposed LPM architecture with their probable failure-rates are analysed. System failure-rates are observed against incremental prefix growth with variable number of hash functions ranging from 6 to 8 to ensure future sustainability of the scheme.

Searching time operation reduced IPV6 matching through dynamic DNA routing table for less memory and fast IP processing

The internet technology needs high-speed (Internet Protocol) IP addressing system and IP matching in router. The IP addressing speed depends on the size of address and destination. Until now, IPV4 address matching performs with various algorithms such as binary trie, LC trie, prefix tree, priority trie, DTBM, and multi-prefix tree. The above algorithms suit for IPV4 address matching and never suit for IPV6 address matching. The IPV6 consists of 128 bits with different header structures when compared to IPV4. The IPV6 address matching needs a robust algorithm with high processing speed IP matching and uses low memory and high accuracy in IP address matching with less operation time. In this paper, we propose DNA-based sequence matching lookup (DSML) algorithm for IPV6 address matching with reduced searching time. The DSML algorithm performs better than existing algorithms such as disjoint prefix tree and multi-index suffix trie because of direct computation of IPv6 matching through DNA folding sequence. The proposed DSML algorithm does the direct computation due to hit score method and never splits the prefix of IPV6. The splitting of prefix in the existing algorithm consumes more time and reduces the accuracy in IPv6 matching. From the experimentation, when compared to existing algorithms the proposed DSML algorithm provides 80% result in terms of speed and scalability.

High-performance polyamide composite membranes via double-interfacial polymerizations on a nanofibrous substrate for pervaporation dehydration

A novel double-interfacial polymerizations (double-IP) strategy was demonstrated for the maneuverable fabrication of high-performance polyamide (PA) composite membranes based on nanofibrous substrates for efficient isopropanol dehydration by pervaporation. Firstly, an ultra-thin auxiliary polyamide layer (A-PA) was synthesized on a highly porous polyacrylonitrile (PAN) nanofibrous substrate by using low concentration ethylenediamine (EDA) and trimesoyl chloride (TMC) solution, which decreased the reaction rate and prolonged polymerization time to achieve a smooth, relatively loose but intact A-PA layer. Secondly, a more compact PA selective layer (S-PA) was fabricated with relatively high concentration EDA and TMC solution on A-PA surface. Benefiting from the A-PA layer, the amount and diffusion rate of adsorbed EDA solution through the layer to contact TMC solution were effectively controlled in second IP process. S-PA layers tended to be more uniform, and there was no marked void or detachment observed between two PA layers. Significantly, the pervaporation performance of as-prepared membranes were tuned by changing the structure of S-PA layers with the assistant of different A-PA layers. The optimized two-tier polyamide (Bi-PA) thin-film nanofibrous composite (TFNC) pervaporation membranes exhibited high permeate flux (6075 g/(m2 h)) and enhanced separation factor (1314) for dehydrating 90 wt% aqueous isopropanol solution at 70 °C. This work may suggest an efficient and facile approach to fabricate high performance pervaporation membranes.

Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform

The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.

Digital twins, the industrial Internet of Things and cyber security threats in connected industry

The industrial and manufacturing sector has already experienced significant transformation with the introduction of automation and is now being transformed due to connectivity. There is real potential for the sector to reinvent itself around the Industrial Internet of Things (IIoT) and smart technology as the benefits are numerous. However, this increased connectivity in manufacturing environments and industrial control systems also increases the attack surface for the software, IP and critical processes which could result in disastrous consequences if not properly addressed. The dangers are also actually more complex than you may at first imagine, particularly when you take into account technological advances such as digital twins — designed to provide business benefit in a predictive and operational context, but could actually add to an organisation’s vulnerabilities, if not properly secured. This paper analyses the specific considerations that are crucial with connectivity and smart technology in industrial environments and industrial control systems. Areas discussed include: how to understand how hackers may target your business; the role of digital twins in manufacturing and industry and the potential security risks; how to upgrade the cyber security of connected industry and manufacturing in the face of wider IIoT threats.

Porous metal–organic molecular cage: a promising candidate to highly improve the nanofiltration performance of thin film nanocomposite membranes

Novel PA/Fe-cage TFN membranes with improved nanofiltration performance were successfully fabricated by incorporating porous Fe-cages during the IP process.

Optimizing Sparse Matrix–Vector Multiplications on an ARMv8-based Many-Core Architecture

Sparse matrix–vector multiplications (SpMV) are common in scientific and HPC applications but are hard to be optimized. While the ARMv8-based processor IP is emerging as an alternative to the traditional x64 HPC processor design, there is little study on SpMV performance on such new many-cores. To design efficient HPC software and hardware, we need to understand how well SpMV performs. This work develops a quantitative approach to characterize SpMV performance on a recent ARMv8-based many-core architecture, Phytium FT-2000 Plus (FTP). We perform extensive experiments involved over 9500 distinct profiling runs on 956 sparse datasets and five mainstream sparse matrix storage formats, and compare FTP against the Intel Knights Landing many-core. We experimentally show that picking the optimal sparse matrix storage format and parameters is non-trivial as the correct decision requires expert knowledge of the input matrix and the hardware. We address the problem by proposing a machine learning based model that predicts the best storage format and parameters using input matrix features. The model automatically specializes to the many-core architectures we considered. The experimental results show that our approach achieves on average 93% of the best-available performance without incurring runtime profiling overhead.

Taking Intellectual Property Rights Seriously: Are We In or Out? (Phase 1: Intellectual Property Awareness Among Students and Faculty: Tracking Changing Attitudes and Awareness)

.

Bespoke Processors for Applications with Ultra-Low Area and Power Constraints

This article makes the case for bespoke processor design, an automated approach that tailors a general-purpose processor IP to a target application by removing all gates from the design that can never be used by the application. The resulting processors are more area- and energy-efficient without sacrificing performance.

Bespoke Processors for Applications with Ultra-low Area and Power Constraints

A large number of emerging applications such as implantables, wearables, printed electronics, and IoT have ultra-low area and power constraints. These applications rely on ultra-low-power general purpose microcontrollers and microprocessors, making them the most abundant type of processor produced and used today. While general purpose processors have several advantages, such as amortized development cost across many applications, they are significantly over-provisioned for many area- and power-constrained systems, which tend to run only one or a small number of applications over their lifetime. In this paper, we make a case for bespoke processor design, an automated approach that tailors a general purpose processor IP to a target application by removing all gates from the design that can never be used by the application. Since removed gates are never used by an application, bespoke processors can achieve significantly lower area and power than their general purpose counterparts without any performance degradation. Also, gate removal can expose additional timing slack that can be exploited to increase area and power savings or performance of a bespoke design. Bespoke processor design reduces area and power by 62% and 50%, on average, while exploiting exposed timing slack improves average power savings to 65%.

DO MATURE INNOVATION PLATFORMS MAKE A DIFFERENCE IN AGRICULTURAL RESEARCH FOR DEVELOPMENT? A META-ANALYSIS OF CASE STUDIES

SUMMARYInnovation Platforms (IPs) have become a popular vehicle in agricultural research for development (AR4D). The IP promise is that integrating scientific and local knowledge results in innovations that can have impact at scale. Many studies have uncovered how IPs work in various countries, value chains and themes. The conclusion is clear: IPs generate enthusiasm and can bring together stakeholders to effectively address specific problems and achieve ‘local’ impact. However, few studies focus on ‘mature’ IPs and whether or not these achieve impact at a ‘higher’ scale: address systems trade-offs to guide decision making, focus on integration of multiple commodities, reach a large number of beneficiaries and learn from their failures. This study evaluates the impact of mature IPs in AR4D by analysing the success factors of eight case studies across three continents. Although we found pockets of IP success and impact, these were rarely achieved at scale. We therefore critically question the use of IPs as a technology dissemination and scaling mechanism in AR4D programs that aim to benefit the livelihoods of many farmers in developing countries. Nevertheless, we do find that IPs can fulfil an important role in AR4D. If the IP processes are truly demand-driven, participatory and based on collective investment and action, they have the ability to bring together committed stakeholders, and result in innovations that are technically sound, locally adapted, economically feasible for farmers, and socially, culturally and politically acceptable. Several of our cases show that if these IPs are firmly embedded in other public and private extension mechanisms and networks, they can allow the technologies or other types of innovations to scale out beyond the original IP scope, geographical focus or target audience. We see a need for more rigorous, accurate and continuous measurement of IP performance which can contribute to adaptive management of IPs, better understanding of ‘what works’ in terms of process design and facilitation, as well as to cost-benefit analysis of IPs as compared to other approaches that aim to contribute to agricultural development.

A prototype scalable readout system for micro-pattern gas detectors**Supported by National Natural Science Foundation of China (11222552)

A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules: the ASIC card, the adapter card and the front-end card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array (FPGA)-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor (SiTCP) IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC (VA140) cards handling 512 detector channels, or 4 ASIC (AGET) cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels.

The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems

Embedded multicore systems are playing increasingly important roles in the design of consumer electronics. The objective of such systems is to optimize both performance and power characteristics of mobile devices. However, currently there are no power metrics supporting popular application design platforms (such as SID) that application developers use to develop their applications. This hinders the ability of application developers to optimize power consumption. In this article we present the design and experiments of a SID-based power-aware simulation framework for embedded multicore systems. The proposed power estimation flow includes two phases: IP-level power modeling and power-aware system simulation. The first phase employs PowerMixer IP to construct the power model for the processor IP and other major IPs, while the second phase involves a power abstract interpretation method for summarizing the simulation trace, then, with a CPE module, estimating the power consumption based on the summarized trace information and the input of IP power models. In addition, a Manager component is devised to map each digital signal processor (DSP) component to a host thread and maintain the access to shared resources. The aim is to maintain the simulation performance as the number of simulated DSP components increases. A power-profiling API is also supported that developers of embedded software can use to tune the granularity of power-profiling for a specific code section of the target application. We demonstrate via case studies and experiments how application developers can use our SID-based power simulator for optimizing the power consumption of their applications. We characterize the power consumption of DSP applications with the DSPstone benchmark and discuss how compiler optimization levels with SIMD intrinsics influence the performance and power consumption. A histogram application and an augmented-reality application based on human-face-based RMS (recognition, mining, and synthesis) application are deployed as running examples on multicore systems to demonstrate how our power simulator can be used by developers in the optimization process to illustrate different views of power dissipations of applications.

A Java Processor IP Design for Embedded SoC

In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.

Graphical Hardware Description as a High-Level Design Entry Method for FPGA-Based Data Acquisition Systems

Probably one of the most significant developments in the field of software-defined multifunction data acquisition systems and devices is the employment of FPGA (Field-Programmable GateArray) technology, resulting in a tremendous digital processing potential close to the I/O pin. FPGA technology is based on reconfigurable semiconductor devices which can be employed as processing targets in heterogeneous computing architectures for a variety of data acquisition applications. They can primarily be characterized by generic properties, such as deterministic execution, inherent parallelism, fast processing speed and high availability, stability and reliability. Therefore FPGAs areparticularly suitable for use in “intelligent” data acquisition applications that require either in-line digital signal co-processing or real-time system emulation in the field of advanced control, protocol aware communication, hardware-in-the-loop (HIL) as well as RF and wireless test. From the perspective of a domain expert however, primarily being focused on developing applications and algorithms, simple and intuitive design entry methods and tools are required that facilitate the FPGA configuration and design entry process. Traditional FPGA design entry methods and commercially available tools assume a comprehensive knowledge of hardware description languages (HDL),such as VHDL or Verilog®, and implement a process or function at register-level. In contrast, graphical hardware description languages for FPGAs, such as the integrated development environment NI LabVIEW® with FPGA module extension, abstract the design process by means of graphical objects, I/O nodes and interconnecting wires that represent the FPGA’s IP and implement processes, timing, I/O integration and data flow. This paper discusses the advantages of graphical system design for FPGAs over text-based alternatives, introduces interfaces for the integration of 3rd party IP, all backed up by a detailed illustration of a COTS FPGA-based multifunction DAQ target compared to a traditional DAQ architecture.

Between power and powerlessness – discourses in the individual plan processes, a Norwegian dilemma

The purpose of this article is to explore what may cause tensions in the work with IP processes and discuss this in the light of power and powerlessness. The project is designed as a multi-case study. Qualitative data were collected through semi-structured individual interviews and observations from group meetings. Quantitative data were collected through a questionnaire focusing on activities of daily living, as well as from documents such as the available individual plan itself and official minutes of the meetings. The analysis of the material is based on a sociological discourse analysis. The three power discourses disclosed were <em>power of knowledge</em>, <em>power of language, and power of definition. Power of knowledge</em> refers to the clients' expert knowledge of themselves as well as the professionals' knowledge whereas the informants experienced <em>power of language</em>, as a physical, psychological, and social instrument to present the client's case. The holder of power of knowledge and power of language possesses <em>the power of definition</em> regarding the individual plan process, but the study revealed nuances in this relationship. More attention and self-awareness should be paid to the relationship between the trust professionals are given by the clients and the position of power this entails when collaborating in IP processes.

ELEON3LP – Superscalar and low-power enhancements of single issue general purpose processor model

Low power consumption and high-performance are the most important factors in modern embedded System-on-Chip (SoC) designs. Increasing computation complexity and incessant growth of clock frequency reveals the necessity for dynamic and smart utilization of the available hardware resources. The paper presents the modified LEON3 processor IP core as an exemplary process of enhancing single issue general purpose processor with superscalar abilities and low-power features. The results of this work can be applied to many existing general purpose processor models to achieve low-power and high-performance systems suitable for modern embedded applications. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle and dynamically manage incorporated power domains. The Enhanced LEON3 IP core was synthesized for 500MHz using UMC 90nm CMOS technology. Performed gate level VCD-based (Value Change Dump) power estimation shows that combining superscalar and low-power techniques allows performing faster program execution with less energy consumption than the original design.

Performance Analysis of IEEE 802. 3 using IGRP and EIGRP Routing Protocols

With the growing need to distribute applications across multiple networks and the availability of high capacity, highperformance intermediate switching nodes and networks, an efficient routing mechanism has become the core requirement. This paper compares the performance of intra-domain routing protocols such as Enhanced Interior Gateway Protocol (EIGRP) and Interior Gateway Protocol (IGRP) of IEEE 802.3 LAN by evaluating various parameters including Network convergence time, End to End Delay, Delay Variation, Throughput, Utilization, Queuing Delay and IP Processing Delay. In addition to these metrics, we also compared the performance of video- and voice-data on the entire network under various constraints managed by routing protocols. Our simulation has been performed using the wellknown simulator OPNET.

A Virtual Simulation Environment for a Design and Verification of a GPGPU

STABLISHING a verification environment provides a debugging mechanism for correct results from a processor and also a foundation for sharing a developing project to participated developing engineers. To develop a processor, the design of processor IP must be accompanied with developing of a compiler and its applications. Proper commands should be defined for the compiler. These commands depend on the implementation of a processor. The application can be developed based on the design of a compiler and a processor. These applications are necessary to verify the design of a processor. A parallel development is needed for the efficiency. In order to develop a system in parallel, independent development platform must be constructed, so that each component can be developed without consideration of a whole system. In order words, a processor, a complier, and its applications should be developed at the same time. For the parallel development, unrelated independent jobs needs to be designated as a pre-proceed step. The design of a processor does not start from the design of HDL. The design of a compiler and its applications do not consider the design of the processor at the beginning stage.

A Redox Series of Aluminum Complexes: Characterization of Four Oxidation States Including a Ligand Biradical State Stabilized via Exchange Coupling

Electrophilic activation and subsequent reduction of substrates is in general not possible because highly Lewis acidic metals lack access to multiple redox states. Herein, we demonstrate that transition metal-like redox processes and electronic structure and magnetic properties can be imparted to aluminum(III). Bis(iminopyridine) complexes containing neutral, monoanionic, and dianionic iminopyridine ligands (IP) have been characterized structurally and electronically; yellow (IP)AlCl(3) (1), deep green (IP(-))(2)AlCl (2) and (IP(-))(2)Al(CF(3)SO(3)) (3), and deep purple [(IP(2-))Al](-) (5) are presented. The mixed-valent, monoradical complex (IP(-))(IP(2-))Al is unstable toward C-C coupling, and [(IP(2-))Al](2-)(μ-IP-IP)(2-) (4) has been isolated. Variable-temperature magnetic susceptibility and EPR spectroscopy measurements indicate that the biradical character of the ligand-based triplet in 2 is stabilized by strong antiferromagnetic exchange coupling mediated by aluminum(III): J = -230 cm(-1) for Ĥ = -2J(Ŝ(L(1))·Ŝ(L(2))). Coordination geometry-dependent (IP(-))-(IP(-)) communication through aluminum(III) is observed electrochemically. The cyclic voltammogram of trigonal bipyramidal 2 displays successive ligand-based oxidation events for the two IP(1-/0) processes, at -0.86 and -1.20 V vs SCE. The 0.34 V spacing between redox couples corresponds to a conproportionation constant of K(c) = 10(5.8) for the process (IP(-))(2)AlCl + (IP)(2)AlCl → 2(IP(-))(IP)AlCl consistent with Robin and Day Class II mixed-valent behavior. Tetrahedral 5 displays localized, Class I behavior as indicated by closely spaced redox couples. Furthermore, CV's of 2 and 5 indicate that changes in the coordination environment of the aluminum center shift the potentials for the IP(1-/0) and IP(2-/1-) redox couples by up to 0.9 V.