Processor IP Research Articles

차세대 모바일 단말 플랫폼을 위한 MIPI CSI-2 & D-PHY 카메라 컨트롤러 구현

본 논문에서는 차세대 모바일 단말 카메라 표준 인터페이스인 MIPI CSI-2 및 D-PHY를 설계하였다. 제안된 CSI-2는 레인별로 존재하는 버퍼를 하나로 통합하여 송수신단이 지원하는 레인의 개수가 다른 경우에도 유연하게 관리 될 수 있는 멀티레인관리계층을 가진다. 설계된 CSI-2 및 D-PHY는 테스트 벤치를 통해 RTL 검증되었다. 또한 FPGA로 합성된 후 테스트 베드를 통해 기능 검증이 이루어 졌으며, 실제 단말기에 적용하여 동작 여부를 확인 하였다. 설계된 CSI-2 및 D-PHY 모듈은 브리지 형태로 제공되어 기존의 카메라 센서와 호스트 프로세서와 오프 칩 형태로 사용할 수 있을 뿐 아니라, 차세대 모바일 카메라 컨트롤러와 온 칩 화 가능한 IP 형태로도 사용 가능하다. In this paper, we design a future mobile camera standard interface based on the MIPI CSI-2 and D-PHY specification. The proposed CSI-2 have the efficient multi-lane management layer, which the independent buffer on the each lane are merged into single buffer. This scheme can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. The proposed CSI-2 & D-PHY are verified under test bench. We make an experiment on CSI-2 & D-PHY with FPGA type test-bed and implement them onto a mobile handset. The proposed CSI-2 & D-PHY module are used as both the bridge type and the future camera processor IP for SoC.

A SystemC-only design methodology and the CINE-IP multimedia platform

The increasing complexity of modern System-on-Chip (SoC) platforms has revealed the need for methodologies that enable a rigorous engineering design process, based on a combination of Electronic System Level (ESL) description languages, and IP-core modeling and reuse. On the other hand, ESL modeling has faced designers with the same methodology problems encountered in the design of large computer programs. In this paper, we describe a SystemC-only IP-core design process, called IP PROCESS (IPP). IPP is inspired on two rigorous software engineering processes (RUP and XP), and on well-known hardware design standards (VSIA and RMM). The IPP Verification Methodology (IPV) is based on a careful refinement of the SystemC behavioral description towards RTL. Such approach enabled a continuous co-simulation against the behavioral reference model, while allowed for a SystemC-only environment. As a result, we have experienced a considerable reduction in design time and an improvement in early bug detection. The IPP process has been used by over 70 designers of the BrazilIP Network, a SystemC collaborative partnership, in the design of the Fenix system. An intermediate step in the Fenix design is a real-world multimedia platform called CINE-IP (demo available at http://www.brazilip.org.br/cine-ip), composed of MPEG4, MP3 decoders and an 8051 microcontroller. The application of the IPP methodology in the design of CINE-IP, and its impact in design productivity is thoroughly analyzed.

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

SUMMARY This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45–73% in comparison to cases with conventional

An IPv6 enabled packet engine design for home/SOHO routers

Due to the diversity of internet applications and services, traditional software-based networking devices may not be sufficient to afford the processing load imposed by the services. One example is the mixed-version IP environment in which routers must handle the IPv4/IPv6 translation while keeping the IP processing at the line speed. In this paper, we present our work for the design of a protocol optimised packet processing engine that provides common IP services and mixed-version translations. This silicon is written in VHDL and is tested in a Xilinx Vertex II FPGA development board.

Tracking set-expression cardinalities over continuous update streams

There is growing interest in algorithms for processing and querying continuous data streams (i.e., data seen only once in a fixed order) with limited memory resources. In its most general form, a data stream is actually an update stream, i.e., comprising data-item deletions as well as insertions. Such massive update streams arise naturally in several application domains (e.g., monitoring of large IP network installations or processing of retail-chain transactions). Estimating the cardinality of set expressions defined over several (possibly distributed) update streams is perhaps one of the most fundamental query classes of interest; as an example, such a query may ask “what is the number of distinct IP source addresses seen in passing packets from both router R1 and R 2 but not router R3?”. Earlier work only addressed very restricted forms of this problem, focusing solely on the special case of insert-only streams and specific operators (e.g., union). In this paper, we propose the first space-efficient algorithmic solution for estimating the cardinality of full-fledged set expressions over general update streams. Our estimation algorithms are probabilistic in nature and rely on a novel, hash-based synopsis data structure, termed ”2-level hash sketch”. We demonstrate how our 2-level hash sketch synopses can be used to provide low-error, high-confidence estimates for the cardinality of set expressions (including operators such as set union, intersection, and difference) over continuous update streams, using only space that is significantly sublinear in the sizes of the streaming input (multi-)sets. Furthermore, our estimators never require rescanning or resampling of past stream items, regardless of the number of deletions in the stream. We also present lower bounds for the problem, demonstrating that the space usage of our estimation algorithms is within small factors of the optimal. Finally, we propose an optimized, time-efficient stream synopsis (based on 2-level hash sketches) that provides similar, strong accuracy-space guarantees while requiring only guaranteed logarithmic maintenance time per update, thus making our methods applicable for truly rapid-rate data streams. Our results from an empirical study of our synopsis and estimation techniques verify the effectiveness of our approach.

Low power synthesizable register files for processor and IP cores

In this paper, low power architectures of register files on register-transfer level (RTL) are presented. The proposed architectures are implemented using a standard hardware description language (HDL) and can be synthesized within a commercial semi-custom design flow. The presented register file architectures are ideally suited for synthesizable processor cores or IP blocks. It is shown, that significant power savings of register files can be achieved, if a clock gating scheme for register files different from the one usually applied is used. As an alternative, an architecture with register isolation is presented. The third proposed register file architecture is based on interleaving known from signal processing implementations. Although, interleaving is usually applied to multichannel algorithms, it is shown that this architecture can also be applied to certain single channel cases. Experimental results of all three register file architectures prove that a significant power reduction can be achieved.

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.

The next challenge

We in the technology community and marketplace have experienced many events in 2001. The downturn of the IT industry’s economic boom became obvious to everybody, and sales figures for PCs and servers declined. The traditional demand for computers has reached a plateau, it seems. The bulk of new equipment purchases now comes from existing computer users and owners. We have seen the failures of many dotcoms in the broadband, mobile, and wireless fields. However, this seems to be a temporary situation, caused by overly optimistic investment and poor planning by the failed companies. We always need some adjustment—including (sadly) the failure of rushed business ventures— when a new technology appears and is accepted by the market and society, changing the technological infrastructure. Today, many people want a fast Internet connection that they can use everywhere. We have evolved past the phase when only technical geeks played with the broadband environment. In this new phase, many ordinary users choose broadband technology, even when they don’t possess much computer and technical knowledge. The need for faster connections is strong, and no end to technological progress is in sight. The current IT industry is not quite amenable to the short-time attention of investors. However, actually, this is the time for the really skilled engineers and developers to sit and develop the next-generation technology, and to do this while avoiding the influence from short-span market fluctuations. In this issue, we present selected articles from the Hot Interconnects 9 conference. IEEE Micro has featured Hot Interconnects as a special theme issue for the last several years, offering valuable content to Micro readers. The Guest Editors’ Introduction to this issue appears on page 8. The issue covers wide-ranging topics, including the network architecture of microprocessors, server interconnects, clustering technology, efficient compaction of routing tables, and IP processing layers for reconfigurable processors. I hope Micro readers find these articles as interesting as I did. Please enjoy.

3‐D nonisothermal flow simulation model for injected pultrusion processes

AbstractInjected pultrusion (IP) is an efficient process for high‐quality, low‐cost, high‐volume manufacturing of polymeric composites with relatively simple cross sections. This process was developed recently, and efforts to develop tools for model‐based design and optimization of this process have only just begun. This work focuses on developing a 3‐D nonisothermal computer simulation model for the IP process. First, the governing equations for transport of mass, momentum, and energy are formulated by using a local volume‐averaging approach. In turn, a computer simulation model of the IP process is developed using the finite‐element/control‐volume (FE/CV) approach. Specifically, the continuity equation and the conservation of momentum equation are solved using a Galerkin FE/CV technique. The chemical species balance equation is solved in the Lagrangian frame of reference, whereas the energy equation is solved using the streamline upwind Petrov‐Galerkin approach. Using the simulation model, the effect of fiber pull speed, reinforcement anisotropy, and taper of the die on the product quality was demonstrated. In addition a simple pulling‐force model was developed and integrated with the simulation model. Overall, the simulation model can be effectively used to design the die geometry and to optimize the operating conditions for a given product.

Modeling of injected pultrusion processes: A numerical approach

AbstractInjected pultrusion (IP) is an attractive process for high volume, high performance, and low cost manufacture of continuous fiber reinforced polymer matrix composites. In this work we focus our attention on development of a computer simulation model for the IP process. First, the governing equations for conservation of mass, momentum, and energy are developed using a local volume averaging approach. In turn, a computer simulation model of the IP process is developed using finite element/control volume (FE/CV) and finite difference techniques. Specifically, the equation of continuity and conservation of momentum are solved in 2‐D using a Galerkin FE/CV technique. The energy and chemical species balance equations are solved in 3‐D, where streamline upwind Petrov‐Galerkin (SUPG) or streamline upwind (SU) FE/CV are used to discretize the equations in two dimensions while finite differences have been used in the third dimension. The chemical species balance equation is solved in the Lagrangian frame of reference using finite differences. Different numerical formulations (Galerkin, Lagrangian, SU, and SUPG) are used to solve a number of benchmark problems to determine the best numerical formulation. It is shown that for coarse discretization, Streamline Upwind methods perform consistently better than the other methods. However, for refined meshes, the Lagrangian method produces the best solution for a given CPU time. Also, using the simulation model, the effect of fiber pull speed, reinforcement anistropy, and taper of the die on the quality of the product is studied. It is shown that the simulation model can be effectively used to design the die geometry as well as to optimize the operating conditions for a given product.

High-speed data paths in host-based routers

In networking today, host workstations are increasingly being used as routers. Host based routers offer a number of advantages, but they suffer from inefficient support for high bandwidth interfaces. The authors' work has focused on the technology's major drawback its inefficiency in supporting high bandwidth interfaces. Their approach is to optimize packet processing by applying techniques that transfer packets directly among host interfaces, thus removing an extra data copy. This technique increases data throughput by 45 percent while reducing the host's CPU load. They found that peer DMA forwarding can increase host based router throughput by up to 45 percent, supporting bandwidths of 480 Mbps. Peer DMA host based forwarding requires network interface cards with substantial shared memory resources, because packet queues are stored on the interfaces themselves, rather than in host RAM. The queuing algorithm remains in the host CPU, supporting advanced queue management. Current systems have limited packet processing. A combination of streamlined forwarding algorithms and aggregate interrupt processing should further increase host based capability. Moving some of the IP processing out to the NIC coprocessor may enable this. It is also apparent that as processor speeds increase, the advantages of peer DMA will aid throughput for small packet sizes.