Nowadays, the main challenge in front of system designers is to design power-efficient systems with reduced design turnaround time. It can be achieved in two ways, firstly, utilize off-shelf components (Intellectual Property cores) along with user-defined IPs. Secondly, estimate the power at an early stage of the design cycle. Therefore, this paper represents the power estimation of Cascaded and Non-Cascaded DSP blocks based on IP modeling. The DSP blocks are designed using a blend of embedded and user-defined IP cores. Curve-fitting and regression-based models for power evaluation have been created for each IP core. The power of the complete DSP block is estimated using identity projected by Elleouet et al. by incorporating the power values of each IP core obtained from the regression-based models. The models have been validated for accuracy using the power values gained from the commercial tool (Vivado design suite (2014.2)). From the analysis, it has been found that the identity is providing inaccurate results for cascaded DSP blocks. Therefore, in this work, a new identity has been proposed that has been estimating the power of the cascaded systems accurately and also in alignment with the results of a commercial tool.
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