IP Core Research Articles

Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

WITHDRAWN: Physical unclonable function based proof-carrying approximate circuits

Abstract Ensuring security without compromising the performance of a system and adaptability is fundamentally a very challenging task for approximate Circuits research groups and practitioners to trade off the computational precision against hardware, latency or energy consumption improvements. Internet protocol core suppliers who want to make such circuits have been able to persuade customers and of ability to origin the details of the accurate estimate. This paper Proposed a proof-carrying based on Physical Unclonable Function (PUF) as a response. The seller produces an estimated IP core combined with a certificate that shows the precision of the reliability of all the specific ratings. The proof certificate is packaged and shipped off to the buyer with the estimated IP heart. To activate such feature the PUF response from the chip will be used. The IP core approximation accuracy can be formally verified by the purchaser for formal verification at a portion of the usual computational cost.

AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.

The Design of High Precision Arbitrary Waveform Generator Based on DDS Technology and FPGA

Combining with the IP core advantage of FPGA, a signal generator which can generate arbitrary waveform is designed on the basis of direct digital synthesis technology in this paper. The INTEL company’s Cyclone IV series EP4CE6F17C8N is used as the control core and the front-end interface design is carried out by XMAL. The software control operation of the logical processing interface is realized through C#. The signal generator has the characteristics of single cycle waveform with 256 sampling points, clear spectrum analysis, higher purity and high precision. The arbitrary waveform displayed on oscilloscope is wonderful after filtering out high frequency signal by seven order butter worth filter.

High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators

Multiplication is one of the widely used arithmetic operations in a variety of applications, such as image/video processing and machine learning. FPGA vendors provide high-performance multipliers in the form of DSP blocks. These multipliers are not only limited in number and have fixed locations on FPGAs but can also create additional routing delays and may prove inefficient for smaller bit-width multiplications. Therefore, FPGA vendors additionally provide optimized soft IP cores for multiplication. However, in this work, we advocate that these soft multiplier IP cores for FPGAs still need better designs to provide high-performance and resource efficiency. Toward this, we present generic area-optimized, low-latency accurate, and approximate softcore multiplier architectures, which exploit the underlying architectural features of FPGAs, i.e., lookup table (LUT) structures and fast-carry chains to reduce the overall critical path delay (CPD) and resource utilization of multipliers. Compared to Xilinx multiplier LogiCORE IP, our proposed unsigned and signed accurate architecture provides up to 25&#x0025; and 53&#x0025; reduction in LUT utilization, respectively, for different sizes of multipliers. Moreover, with our unsigned approximate multiplier architectures, a reduction of up to 51&#x0025; in the CPD can be achieved with an insignificant loss in output accuracy when compared with the LogiCORE IP. For illustration, we have deployed the proposed multiplier architecture in accelerators used in image and video applications, and evaluated them for area and performance gains. Our library of accurate and approximate multipliers is opensource and available online at <uri>https://cfaed.tu-dresden.de/pd-downloads</uri> to fuel further research and development in this area, facilitate reproducible research, and thereby enabling a new research direction for the FPGA community.

A 3.3 Gbps CCSDS 123.0-B-1 Multispectral &amp; Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA

The explosive growth of data volume from next generation high-resolution and high-speed hyperspectral remote sensing systems will compete with the limited on-board storage resources and bandwidth available for the transmission of data to ground stations making hyperspectral image compression a mission critical and challenging on-board payload data processing task. The Consultative Committee for Space Data Systems (CCSDS) has issued recommended standard CCSDS-123.0-B-1 for lossless multispectral and hyperspectral image compression. In this paper, a very high data-rate performance hardware accelerator is presented implementing the CCSDS-123.0-B-1 algorithm as an IP core targeting a space-grade FPGA. For the first time, the introduced architecture based on the principles of C-slow retiming, exploits the inherent task-level parallelism of the algorithm under BIP ordering and implements a reconfigurable fine-grained pipeline in critical feedback loops, achieving high throughput performance. The CCSDS-123.0-B-1 IP core achieves beyond the current state-of-the-art data-rate performance with a maximum throughput of 213 MSamples/s (3.3 Gbps @ 16-bits) using 11 percent of LUTs and 27 percent of BRAMs of the Virtex-5QV FPGA resources for a typical hyperspectral image, leveraging the full throughput of a single SpaceFibre lane. To the bes t of our knowledge, it is the fastest implementation of CCSDS-123.0-B-1 targeting a space-grade FPGA to date.

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

Many digital signal processing applications require a channelizer capable of moving sections of the incoming spectrum to baseband quickly and efficiently with minimal spectral leakage and signal distortion. We report the design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC. The open-source design consists of only IP cores created using Vivado HLS (C++) and IP cores available in Vivado HLx and System Generator versions 2019.1+. The channelizer was tested using a PYNQ overlay and Jupyter Notebook (Python) hosted on the RFSoC embedded CPU. The design uses 24% of the LUTs, 9% of the DSP48s, and 11% of the BRAMs on the ZCU111 RFSoC evaluation board and meets timing constraints at 512 MHz. The oversampled polyphase channelizer suppresses spectral image components below -60 dB. This design provides the first example of an oversampled polyphase channelizer running on a system on a chip architecture created without direct use of hardware description language. The presented approach leverages high-level design tools and includes source code which can be readily adapted by other researchers and development teams without the need for specialist knowledge in high-performance FPGA design.

Review of Reconfigurable Virtual Instrumentation and It Implementation in Cameroon Labs

With the exponential evolution of the complexity of reconfigurable logic circuits, the Field Programmable Gate Array (FPGA) becomes an attractive element to realize reconfigurable virtual instruments, due to their inherent flexibility. The simple bus architecture allows us to use pre-exist IP Cores (IP Cores) in VHDL and interconnecting them, also allowed us to reuse code in all designs. Research on reconfigurable virtual instruments has continued to evolve and has become a real alternative for many research laboratories in developing countries such as Cameroon. In this paper, we present a review of the FPGA-Based Reconfigurable Virtual instrumentation and the experimental tools developed in our labs. The development of experimental sciences and engineering benefits from the ability to obtain reliable data from controlled situations and process as measurements and comparisons. This achievement invokes two parallel approaches: software development and hardware development. This has been demonstrated in our context with the implementation of a virtual oscilloscope. Indeed, with the processing of reconfigurable technological circuit, designing virtual instruments with multiple shapes is henceforth feasible. The advantages offered by this innovation are essentially the reduction of development times, the optimization of resources and the reduction of costs. Given the need for these instruments in research laboratories, their lack in universities in our countries poses a real problem. Fortunately, in recent years, research and technological innovation have largely developed to offer reconfigurable solutions in instrumentation based on SoCs. The oscilloscope described in this article can communicate directly with a PC, using a USB serial port that allows communication between the instruments and the PC.

ЗАХИСТ БЛОКІВ ІНТЕЛЕКТУАЛЬНОЇ ВЛАСНОСТІ У СПЕЦІАЛІЗОВАНИХ КОМП’ЮТЕРНИХ ЗАСОБАХ НА БАЗІ ПЛІС

The current evolutionary stage of the microchips’ architecture of programmable logic does precondition not only a rationale for but also desirability of its utilisation when developing specialised computer means or the combinatory part of devices of computing machines. The increase in complexity of digital computational devices, especially in the critical usage’ computer systems, dramas and focuses the attention of developers and OEMs of FPGA to the occurrence of events related to the devices’ correct operation’ interruption, that may be caused both by external factors and intrusion. If events that are caused by negative external impacts such as a Single-Event Effect, may be related to the transition to new technological norms of the semiconductor products manufacturing, e.g. FPGA microchips, then any intrusions to the devices’ operation have anthropological origins. Widespread use of FPGA to implement the specialised computer means prompts the use of the intellectual property blocks (intellectual property core, IP-core) since to create certain samples of hardware the broad functional capabilities have to be implemented, which is effectuated by the IP. Such an approach enables materialisation of the substantial feature set in a specialised device, overcome the complexities in the devices’ development and narrow down time-frames. A part of an overview of the efficient IP cores protection, being an important and complex task, is exemplified in the paper. Different approaches and methods are outlined for such protection organisation. Examples are given of the examples of the additional structures’ usage, complementary to ciphering and authentication, that prohibit unauthorised access.

Identification of FSM State Registers by Analytics of Scan-Dump Data

Big data analytics have gained tremendous successes in mining valuable information in various fields. However, its potential to solve complex problems in hardware security has not been adequately tapped. This paper presents a non-invasive approach to identify the state registers of a finite state machine (FSM) in an integrated chip. The state registers of the FSM are mined from the scan-dump data by exploiting the strongly connected property and chronologically correlated state codes of the FSM. The sequence of data scanned out of each scan register is partitioned into non-overlapping strings of high weighted frequencies by a string-matching algorithm. A coherency between a pair of registers is defined and computed based on the partitioned strings. The dimension of the coherency matrix is first reduced by pruning some registers of low influence by a regression analysis. The registers are then clustered to minimize the within-cluster variances based on their coherency values. The proposed scheme is applied to some IP cores from OpenCores. The experimental results show that our scheme can correctly identify the FSM state registers in most designs with high hit rate.

Application of FPGA technologies for modeling hydrophysical processes in reservoirs with complex bottom topography

The article is devoted to the development and research of methods for accelerating calculations and processing input data for mathematical modeling of hydrodynamic processes in reservoirs with complex bottom geometry. The mathematical model of hydrodynamics considers: microturbulent diffusion; the influence of salinity and temperature. To increase the speed of calculations, it is proposed to transfer part of the computational load to reconfigurable computing systems (RVS). The paper also proposes an algorithm for adding input data by analyzing the existing database of environmental data, which was successfully verified analytically. The practical significance of the work is that a hardware implementation of the IP core was proposed, which allows solving systems of linear algebraic equations that arise when sampling the model of hydrodynamics of the Caspian Sea. It is experimentally established that the resulting implementation is characterized by low power consumption and is capable of processing large-dimensional matrices. The prospects of using the proposed algorithm are determined.

Real-Time High Definition License Plate Localization and Recognition Accelerator for IoT Endpoint System on Chip

ABSTRACT Automatic License Plate Recognition (ALPR) systems have become popular application areas of the Internet of Things (IoT). A typical ALPR system always needs powerful processors such as Cortex-A7. However, most known system for Standard Definition (SD) are not suitable for real-time High Definition (HD) image processing and low power consuming requirement in IoT. A HD ALPR accelerator for the IoT endpoint System on Chip (SoC) is proposed in this paper to meet the needs of computations. Based on the programming flexibility of IoT endpoint SoC, it can switch between HD and SD resolutions, which can avoid the specific resolution switching algorithm. A Field Programmable Gate Array (FPGA) chip is transplanted the Cortex-M0 as the IoT endpoint SoC, through the design of ALPR accelerator and Cortex-M0, data communication is achieved by First-In, First-Out (FIFO) with AMBA High-performance Bus (AHB) interface. Heterogeneous implementation of ALPR system has shown that this HD ALPR algorithm can recognize a license plate in 12.5ms, with a success rate of 95.5%. The system utilizes 41,763 Look-Up-Tables (LUTs) without special FPGA IP core. The comparison shows that the system proposed in this paper makes performance of the SoC based on the Cortex-M0 kernel was two times higher than the Cortex-A72 SoC and 39% of the power consumption of Zynq-7000 that is typicalheterogeneous ALPR platform.

Design of domestic serial and parallel interface module

Domestic serial and parallel interface module is based on domestic high performance FPGA CPCIE module. This type of FPGA has rich logical resources and internal integration of a variety of high-speed interfaces, such as PCIE, high-speed Serdes interface, which can achieve serial port, time system, network and other interfaces design, greatly simplifying the hardware design of the module. The main communication interfaces, PCIE and UART, are realized by the IP core of FPGA, realizing the integration of the main functions on the chip, which greatly improves the flexibility and expansibility of the design.

Design of SOPC digital frequency meter based on MicroBlaze

A method of SOPC implementation of digital frequency meter is presented in this paper. In the method, Encapsulated AXI IP core for frequency measurement and duty cycle measurement are configured with the embedded soft core MicroBlaze processor. The parameter measurement of the digital frequency meter is implemented by FPGA logic resources, and the measured data are transmitted to the soft core processor via AXI bus. The computation, control and display is completed by Microblaze soft core. The system is verified and tested on the Basys3 board card launched by digilent company. The results show that the system has the advantages of accurate measurement, good stability, simple scheme and low cost.

Reconfigurable FPGA Realization of Fractional-Order Chaotic Systems

This paper proposes FPGA realization of an IP core for generic fractional-order derivative based on Grünwald-Letnikov approximation. This generic design is applied to achieve reconfigurable realization of fractional-order chaotic systems. The fractional-order real-time configuration boosts the suitability of this particular realization for different applications, including dynamic switching, synchronization, and encryption. The proposed design targets optimized utilization of the FPGA internal resources and efficient employment of the external peripherals: switches and I/O ports in the FPGA board. The digital design of the fractional-order dependent terms: binomial coefficients and power function is proposed. Three approximations of the power function using curve fitting are compared, settling on the quadratic approximation that balances accuracy and efficiency. Three fractional-order chaotic systems: Liu, Li and Chen four-wing, are verified for both commensurate and incommensurate orders cases, using one approach for the commensurate order case and two approaches for the incommensurate order case. The reconfigurable design is realized on the Artix-7 FPGA board, yielding throughputs of 1.1266, 1.1266, and 1.434 Gbit/s for both commensurate and incommensurate orders cases of the three systems, respectively. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.

Heterogeneous verification framework of IP core for image processing algorithm

Heterogeneous verification framework of IP core for image processing algorithm

Hierarchical Group-key Management for NoC-Based MPSoCs Protection

Group keys can be used in order to communicate secretly sensitive data among IP cores. However, the flexibility and dynamic nature of MPSoCs force reshaping the security zones at runtime. Members of a zone must be able to efficiently compute the new group key while former members must be prevented for data disclosure. Efficiently creating security zones for achieving sensitive traffic isolation in MPSoC environments is a challenging problem. In this work we present the implementation of hierarchical group-key management for NoC-based systems in order to efficiently perform the rekeying process. We implement three hierarchical protocols and we show that by decentralizing the security management of the rekeying process, it is possible to achieve an improvement of the performance when compared to the previous flat approaches.

Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores

The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents four energy-efficient FDCT/IDCT configurable IP cores. These architectures are based on Massimino’s algorithm, which was chosen due to its high accuracy and parallelism. The four architectures were built by combining fully-combinational or pipelined datapaths, using either a single or two 1-D DCT blocks with a transpose buffer that assures the optimal minimum latency of eight cycles. Synthesis results for 90nm showed that our most efficient architecture, which uses two pipelined 1-D blocks, achieved 250 MHz as maximum frequency at a total power of 14.03 mW. Such frequency was enough to process 16x 1080p@30fps videos in real time (nearly 2 GigaPixels/s). Comparisons with related work, in terms of energy efficiency (μJ/MPixels), revealed that our most energy-efficient architecture is at least 2 times as efficient as other DCT architectures. Moreover, the four designed architectures were also synthesized by using common low-power techniques. These results showed that pipelined versions at high throughput tend to take more benefit from using Low-Vdd and High-Vt combined than the combinational ones, thus becoming the most energy efficient.

Wearable on-device deep learning system for hand gesture recognition based on FPGA accelerator.

Gesture recognition is critical in the field of Human-Computer Interaction, especially in healthcare, rehabilitation, sign language translation, etc. Conventionally, the gesture recognition data collected by the inertial measurement unit (IMU) sensors is relayed to the cloud or a remote device with higher computing power to train models. However, it is not convenient for remote follow-up treatment of movement rehabilitation training. In this paper, based on a field-programmable gate array (FPGA) accelerator and the Cortex-M0 IP core, we propose a wearable deep learning system that is capable of locally processing data on the end device. With a pre-stage processing module and serial-parallel hybrid method, the device is of low-power and low-latency at the micro control unit (MCU) level, however, it meets or exceeds the performance of single board computers (SBC). For example, its performance is more than twice as much of Cortex-A53 (which is usually used in Raspberry Pi). Moreover, a convolutional neural network (CNN) and a multilayer perceptron neural network (NN) is used in the recognition model to extract features and classify gestures, which helps achieve a high recognition accuracy at 97%. Finally, this paper offers a software-hardware co-design method that is worth referencing for the design of edge devices in other scenarios.

Energy-efficient, EDFA lifetime-aware network planning along with virtualized elastic regenerator placement for IP-over-EON

In this paper, we focus on energy-efficient network planning (including traffic provisioning) along with optimal placement of virtualized elastic regenerators (VERs) for IP-over-elastic optical networks based on a static traffic profile, using a mixed integer linear programming-based optimization model. The proposed model judiciously exploits flexibility of IP core routers, sliceable bandwidth variable transponders (SBVTs) and VERs to accommodate the traffic demands with the minimum power consumption (PC). Optical layer traffic grooming allows to simultaneously originate/terminate multiple lightpaths of different capacities, data slots and maximum transparent reach by a single SBVT. The proposed model also allows to use all functionalities of VER, such as simultaneous regeneration, distance-adaptive transmission option selection, frequency slot merging to be used concurrently for the given static traffic profile. In addition, the proposed model includes lifetime awareness of Erbium-doped fiber amplifier (EDFA) to reduce EDFA failure and associated repairing cost in long run. Using the proposed model, we enhance the average EDFA lifetime by restricting average EDFA occupancy, represented by the ratio of the (average) number of lightpaths being amplified in an EDFA and the maximum possible number of lightpaths that can be amplified in it, even though in the process, the overall PC in network may increase, with reference to the scenario with no EDFA occupancy restriction. The variation in PC and average EDFA lifetime for different permissible (user-defined) average EDFA occupancy are studied. We exhaustively study performance of the model under different network conditions.