AbstractThe high‐capacity high‐performance dynamic MOS RAM is an outgrowth of progress in fine‐pattern fabrication techniques. However, as the short‐channel effect of MOS transistors becomes more pronounced it becomes increasingly difficult to reduce the effective channel length because it results in performance degradation of the refresh time or breakdown voltage in the dynamic RAM. In this paper we propose a method of fabricating a SAGOS (Self‐Aligned Small Gate Overlap Structure) MOS transistor with small gate‐to‐source/drain overlap capacitance using ion implantation and lithography technique. Its characteristics are clarified and it is shown that an MOS transistor with no short‐channel effect can be obtained even with a final poly gate length of 2.3 μm (effective channel length 2.3 μm). Additionally, in order to prove that the small gate input capacitance of the SAGOS MOS transistor is effective for high‐speed LSI, it is applied to a 64‐K dynamic RAM. No degradation of electrical characteristics is exhibited with CAS access time of 54 ns at Ta = 75 C and Vcc = 4.5 V. This is a speed improvement of 11% compared to a conventional MOS transistor with identical conductance.