Ion-implanted Resistors Research Articles

Reliability of High-Temperature Operation for GaN-Based OPAMP

AbstractWe demonstrated electrical characteristics of operational amplifier (OPAMP) circuits fabricated by GaN/AlGaN/GaN HEMTs operating over 100 oC. GaN/AlGaN/GaN HEMTs, with the extremely low source resistance were fabricated by multiple ion implantation, precisely controlled ion-implanted (I/I) resistors and Schottky barrier diodes were integrated on the silicon substrate. The GaN cap layer on the AlGaN was grown to decrease the gate leakage current and current collapse for AlGaN/GaN HEMTs.

Integrated GaN/AlGaN/GaN HEMTs with Preciously Controlled Resistance on Silicon Substrate Fabricated by Ion Implantation

ABSTRACTMultiple ion-implanted GaN/AlGaN/GaN high electron-mobility transistors (HEMTs) and preciously controlled ion-implanted resistors integrated on silicon substrate are reported. Using ion implantation into source/drain (S/D) regions, the performances were significantly improved. On-resistance reduced from 10.3 to 3.5 Ω•mm. Saturation drain current and maximum transconductance increased from 390 to 650 mA/mm and from 130 to 230 mS/mm. Measured transfer curve shows that I/O gain of 4.5 can be obtained at Vdd = 10 V.

Stress-mapping sensors for high-power adaptive micro-optics

Continuous deformable membrane mirrors are becoming more attractive for use in adaptive optics because they cause no diffraction in the reflected beam and ensure smooth and continuous phase variations across the mirrors. However, when such mirrors are used to correct a high-power incident wave front, the absorption in the coatings causes the temperature of the membrane to increase, thereby creating in-plane thermal stress due to the rigidly clamped boundaries. We present a technique to measure thermal stress in such nondeforming membrane structures. The directional stress and temperature effects are simultaneously measured and decoupled in micromachined membrane mirrors by using a group of three ion-implanted silicon resistors with different orientations. In stress measurements made with incident power, the sensors measure changes in compressive thermal stress to within 80-90 kPa.

A precision physical model for three terminal diffused or ion-implanted resistors

In modern CMOS and BiCMOS technologies, the diffused or ion-implanted resistors are widely used devices. One important source of errors in the accurate analog circuit simulation is the variation of resistance respect to applied voltage for diffused or ion-implanted resistors. This paper analyzes the electrical properties of the diffused resistors, and derives a closed form precision physical model for three terminal diffused resistors or ion-implanted. The voltage dependency of the resistance can be described by the depletion layer spreading into the resistor body. The back bias effect is also included in the model. The temperature model is derived from the mobility and built-in potential temperature models. The extreme cases have been studied, which sets up the minimum resistor width and maximum applied voltage of diffused or ion-implanted resistors. Good match between the modeled and experimental results is observed in the diffused resistors with n- and p-type doping.

Calibration and temperature compensation of silicon pressure sensors using ion-implanted trimming resistors

A piezoresistive silicon pressure sensor with bipolar on-chip signal conditioning circuits permits offset voltage, full scale span and temperature coefficient of offset voltage and full scale span to be calibrated from a trimming ion-implanted resistors. The ion-implanted resistors with temperature coefficient of 1700 ppm/°C or 4700 ppm/°C were fabricated by the same process as that used for the base and piezoresistors. The fabricated sensor exhibits a sensitivity of 40.5 mV/kPa and temperature coefficient of 46 ppm/°C at the temperature range of −10 to 70°C.

A 3-terminal model for diffused and ion-implanted resistors

In this paper, we present a new, physically based 3-terminal model for diffused and ion-implanted resistors. The model accounts for the effects of geometry, temperature, and bias, and includes parasitic p-n junction diodes. The junction depletion capacitances are distributed to model high-frequency behavior accurately.

Megalithic microwave signal processing for phased-array beamforming and steering

A microwave signal processing (MSP) architecture is presented for active phased array beam forming and steering. A large scale network, comprising 63 power dividers and 32 pairs of vector-synthetic phase/amplitude controllers, has been successfully developed in an 11 mm/spl times/13 mm GaAs monolithic microwave integrated circuit (MMIC). It has a huge integration level of 128 metal-semiconductor field effect transmitters (MESFETs), 448 spiral inductors, 527 metal-insulator-metal (MIM) capacitors, and 357 ion-implanted resistors. The expected 360/spl deg/ phase is successfully obtained at all the output ports. Vector error standard deviations exhibited are within 0.38-dB root-mean square (rms) and 2.8/spl deg/ r.m.s. over the bandwidth of 20 MHz at 2.5 GHz. This megalithic chip could mark an epoch in phased array systems.

A fully integrated high-performance FM stereo decoder

A custom FM stereo decoder IC which uses switched-capacitor and linear filters, linear MOS and bipolar circuitry, and digital MOS circuitry to eliminate the requirements for accurate external components and external adjustments is described. The IC includes a combined analog/digital VCO and PLL, a switched-capacitor sine-wave multiplier, and a switched-capacitor pilot detector and cancellation stage. An output S/N ratio greater than 80 dB and output distortion less than 0.1% have been achieved. The part is 26000 mils/sup 2/ and is implemented in a 3 mu m n-well CMOS process containing poly-to-poly capacitors, n-p-n's, and ion-implanted poly resistors. >

1/f noise in ion-implanted resistors between 77 and 300 K

The conductivity, the Hall effect, and the noise of ion-implanted resistors is measured between 77 and 300 K. The temperature dependence of the carrier concentration in these boron-doped layers cannot be explained by the freeze-out of the boron acceptor level. Possible explanations are a temperature-dependent Hall factor r and a distribution of trap levels 0.1–0.2 eV above the valence-band edge. The mobility μ can be determined from the conductivity and the Hall-effect data. The mobility shows the highest value after annealing at 750 °C. The value of the 1/f noise parameter α shows a weak temperature dependence after annealing at 450, 550, 650, and 900 °C. After annealing at 750 °C the α value decreases from 10−5 at 300 K to lower than 2×10−7 at 77 K. The highest mobility μ gives the lowest 1/f noise parameter α. This indicates that more defects and lattice damage give more 1/f noise. Additional scattering mechanisms have much more influence on the 1/f noise parameter α than on the mobility μ.

Ion-implanted thin polycrystalline-silicon high-value resistors for high-density poly-load static RAM applications

An application of ion-implanted polycrystalline-silicon resistors for a 4- and 16-Mbit MOS static RAM cell is discussed. 4M and 16M static RAM's are designed with assumed minimum feature sizes of 0.5 and 0.25 µm of double-level polycrystalline-silicon process and power supply voltages of 3.0 and 1.5 V, respectively. The load current of the memory cell is kept at about 30 pA per cell, which is as low as that of state-of-the-art 64K static RAM's. LPCVD polycrystalline-silicon film of about 25-nm thickness is used to etch fine resistor patterns of 0.25 ∼ 0.5 µm feature sizes. Sheet resistances of 24 and 12 GΩ/ for 4M and 16M static RAM cells are controlled by arsenic implantation of about 4 × 1013and 3 × 1013cm-2at 10 keV, respectively. The ion-implanted polycrystalline-silicon resistors show nearly ideal linear current-voltage characteristics. Grain sizes of the polycrystalline-silicon films calculated from the current-voltage characteristics are in good agreement with those measured by transmission electromicrographs. It was shown that 4M and 16M static RAM's would be realized by combining the scaling-down of state-of-the-art 64K RAM cell of the double-level polycrystalline-silicon process and the thin ion-implanted polycrystalline-silicon resistors.

Model of 1/ f noise in ion-implanted resistors as a function of the resistance, determined by a reverse bias voltage : H. G. E. Beck Solid-St. Electron. 22, 475 (1979)

Model of 1/ f noise in ion-implanted resistors as a function of the resistance, determined by a reverse bias voltage : H. G. E. Beck Solid-St. Electron. 22, 475 (1979)

Ion-Implanted p-Resistor Reliability

One of the key aspects of large-scale integration in bipolar technology depends on the use of high valued resistors. Ion implantation can lead to higher valued resistors not possible with diffused technology. Two different process technologies, pre-emitter and post-emitter, for making ion-implanted resistors are described. Also described are measured profiles, reliability studies carried out on p-resistors made by the two technologies, and a model describing the resistor drift with voltage and temperature.

Model of [formula omitted] noise in ion-implanted resistors as a function of the resistance, determined by a reverse bias voltage : H. G. E. Beck. Solid-St. Electron.22, 475 (1979)

Model of [formula omitted] noise in ion-implanted resistors as a function of the resistance, determined by a reverse bias voltage : H. G. E. Beck. Solid-St. Electron.22, 475 (1979)

Pulsed Electron Beam Processing of Silicon Devices

ABSTRACTPulsed electron beams [1] were used to anneal ion-implanted diodes, transistors, and resistors. Devices were fabricated by patterning a thermal oxide on a silicon wafer, ion-implanting and pulse processing with the oxide in place, and then applying contacts. Oxide films over 0.3 micron thick were not damaged, and the silicon below these films was not melted by the pulsed electron beam. Low-dose (101311B+/cm2), implanted, pulse-annealed resistors showed no change in sheet resistance for oxide windows 2.5 to 50.0 microns wide. Diodes were fashioned with good forward and reverse I-V characteristics, with m=1.09 and IO=2.7×10−10 A/cm2 for I=IO exp(qV.mkT)−1 , when a low-temperature (550˚C, 1 hr), postpulse anneal was included in the process sequence. Both bipolar and FET types of transistors were fabricated. Results compare favorably with thermal annealing cycles.

Model of 1/ f noise in ion-implanted resistors as a function of the resistance, determined by a reverse bias voltage

A model is presented for the 1/ f noise in ion-implanted resistors. The resistance was changed by a reverse bias voltage. The model explains the experimentally found square dependence between the relative 1/ f noise intensity C/ C o and the relative change in resistance R/ R o .

Formula omitted] noise measurements in ion-implanted silicon resistors as a function of the substrate reverse bias voltage

The 1 ƒ noise of ion-implanted resistors has been measured as a function of a reverse bias voltage. Using a substrate bias, the sheet-resistance was changed. It has been empirically found that the relative 1 ƒ noise is proportional to the square of the resistance.

A monolithic analog compandor

Describes a bipolar IC analog dynamic range compandor. The approach taken to implement the compressor and expandor functions is discussed, and the active full wave rectifier and variable gain cell are described in detail. Performance easily exceeds telecommunications requirements and is suitable for use in high quality audio systems. The full wave rectifier has excellent accuracy over a 60-dB dynamic range. The variable gain element offers low distortion (<0.1 percent) attenuation with high signal to noise ratio (90 dB). Ion-implanted resistors have been used for lower temperature sensitivity.

Comparison of boron and neon damage effects in boron ion-implanted resistors

Boron and neon damage implants were used in fabricating integrated-circuit resistors in silicon. Resistor properties were studied as functions of damaging ion species and dose. Sheet resistances in the 10000 Ω/□ range were obtained with low temperature and voltage sensitivities and good d.c. isolation.

Popcorn noise and generation-recombination noise observed in ion-implanted silicon resistors

Experimental results show that, for low currents, the generation-recombination noise component increases with current, and, at higher currents, it decreases inversely with current. For currents greater than a certain value, a generation-recombination noise component is scarcely observed.

Ion Implanted N-Type Resistors on High-Resistivity Substrates

The method of fabrication and measured characteristics of phosphorous ion-implanted resistors made on high-resistivity 15–20 Ω cm p-type silicon substrates are presented. The process included a shallow boron-implanted layer at the surface to prevent surface inversion due to Qss. It is demonstrated that enhancement N-channel MOSFET devices can be processed together with the implanted resistors. The range of phosphorous doses studied was 1×1012–5×1014/cm2 and the range of anneal temperatures considered was 500–950 °C. Results are given for measurements of sheet resistivity vs dose and anneal temperature, and for temperature coefficient of resistance. The advantages of using high-resistivity substrates for the implanted resistors are discussed.