Inverter Stage Research Articles

An In-Depth Investigation of a Z-Source Ultrasparse Matrix Converter in Buck and Boost Modes of Operation

Z-source networks are recently being employed to enhance the boosting capability of matrix converters. This paper concentrates on cascaded Z-source ultrasparse matrix converter (ZSUSMC), where the Z-source network is placed between the three-switch input rectifier stage and the six-switch output inverter stage. Two space vector modulation schemes, with and without a zero state in the rectifier stage modulation, are presented and their advantages and disadvantages are discussed. In addition, restrictions imposed on the converter operation in buck mode, which arise from unidirectional nature of the ultrasparse matrix converter, are discussed and a solution is proposed for offsetting those limitations. Furthermore, an optimal switching pattern, which results in minimum possible number of changes in the switching states as well as even distribution of the shoot-through state over the entire control period, is proposed. Also, common-mode voltages of the converter in all possible switching configurations are calculated. Hardware-in-the-loop studies of a ZSUSMC-based permanent magnet synchronous motor drive are carried out to evaluate the performance of the drive under the proposed modulation techniques. The obtained results are compared with a recent study and the superiority of the proposed method in terms of converter input/output current quality is demonstrated.

Open-Circuit Fault Analysis and Diagnosis for Indirect Matrix Converter

Due to the absence of bulky dc-link capacitors, the matrix converter (MC) is a prospective candidate to replace the conventional two-stage ac–ac converter, especially in some applications which require high reliability. In order to enhance the reliability during system operation, this paper investigates an open-circuit fault detection technology for indirect MC. First, combining with the characteristics of the space vector modulation technique, this paper presents analysis work during the appearance of an open-circuit fault. Then, a novel fault diagnosis approach is proposed based on the circuit analysis. The proposed method establishes a unique corresponding relationship between switches and modulation sectors, and the faulty switch can be discriminated exactly by measuring the three-phase output voltages and the dc-link voltage. This method, which can locate the failure that occurs in rectifier stage or inverter stage correctly, offers favorable antidisturbance ability. The experiments are carried out to verify the feasibility and validity of the proposed fault detection method.

A Z-Source-Derived Coupled-Inductor-Based High Voltage Gain Microinverter

Microinverters require high voltage gain capability for interfacing the low dc voltage output of photovoltaic (PV) module to single-phase ac grid. A two-stage nonisolated inverter is proposed in this paper, with a first boost stage and a second traditional pulse width modulated grid-tied inverter stage. The proposed boost stage consists of a coupled inductor added with a voltage multiplier to achieve the required high voltage gain at high efficiency and to operate over a wide input voltage range. Among the coupled inductor topologies, adding a clamp circuit is a common solution to limit the voltage spike caused by leakage inductance. In the proposed converter, the resonance between the coupled inductor and voltage multiplier is used to address the issue of voltage spike, thereby reducing both component count and device voltage stress. Detailed analysis and design procedure of the proposed converter is presented in this paper. Experimental results of a 250-W microinverter are presented to validate the proposed converter.

Design of modified low power CMOS differential ring oscillator using sleepy transistor concept

As the technology feature size shrinks, leakage power is dominating in the total chip power consumption of VLSI circuits. In this work to reduce the leakage power, sleepy transistor technique is used for differential ring oscillator (RO). First design is proposed using CMOS inverter stage in a differential manner to form ring oscillator with sleepy NMOS and sleepy PMOS transistors. Second design of differential ring oscillator is proposed with CMOS cross-coupled cell with sleepy NMOS and PMOS transistors. Further, substrate-biasing concept has been applied to proposed design for improvement in the power consumption. The power consumption for sleepy NMOS inverter stage differential ring oscillator (RO) is 0.696–0.953 mW and the frequency of operation is 3.09–4.56 GHz. Sleepy NMOS cross-coupled based ring oscillator design shows the power consumption of 0.78–1.21 mW at an operating frequency of 2.23–4.25 GHz. The power consumption for sleepy PMOS inverter stage differential RO design is 1.95–2.04 mW and the frequency of operation is 4.41–4.63 GHz. Further, sleepy PMOS cross-coupled RO design shows power consumption of 0.97–1.06 mW at an operating frequency of 2.26–2.41 GHz. The substrate biasing of sleepy NMOS inverter stage ring oscillator design gives power consumption of 0.862–0.924 mW and the frequency of operation is 4.16–4.45 GHz. Substrate biasing of sleepy NMOS cross-coupled ring oscillator design shows power consumption of 1.06–1.16 mW and output frequency varies from 1.86–2.05 GHz. The simulations have been performed using SPICE in 0.18 µm CMOS technology. Results of power consumption, tuning range, phase noise, FoM and output frequency have been compared with earlier circuits and proposed circuits show improvement in results.

Simultaneous DC and three phase output using hybrid converter

This Paper introduces new hybrid converter topologies which can supply simultaneously three phase AC as well as DC from a single DC source. The new Hybrid Converter is derived from the single switch controlled Boost converter by replacing the controlled switch with voltage source inverter (VSI). This new hybrid converter has the advantages like reduced number of switches as compared with conventional design having separate converter for supplying three phase AC and DC loads, provide DC and three AC outputs with an increased reliability, resulting from the inherent shoot through protection in the inverter stage. The proposed converter, studied in this paper, is called Boost-Derived Hybrid Converter (BDHC) as it is obtained from the conventional boost topology. A DSPIC based feedback controller is designed to regulate the DC as well as AC outputs. The proposed Converter can supply DC and AC loads at 95 V and 35 V (line to ground) respectively from a 48 V DC source.

Fault tolerant three‐level boost inverter with reduced source and LC count

Presently single stage boost multilevel inverters are becoming more popular for power conversion in renewable energy systems, AC-DC hybrid microgrids etc. Usually in these boost inverter the voltage stress across the inverter leg switches as well as current through these switches are quite higher as compared to load ratings which increases the chances of inverter leg switch failure. In this paper a three level voltage source boost inverter is proposed to achieve rated three level AC output voltage in a single power conversion stage. It retains all the advantages of three level quasi Z- Source inverter by using less number of passive components in the intermediate network between DC source and inverter leg. Beside the inherent shoot through fault tolerant feature the proposed inverter is capable to operate in open circuit failure to give rated balanced AC voltage at load. The above advantages of the proposed single stage inverter make it suitable for low and medium power renewable energy applications where size, weight are main constraint and some of the critical loads are connected to the system. The proposed inverter is verified by simulation (in MATLAB Simulink) and experiment with the help of a laboratory prototype.

164 nW Inverter-based capacitive readout IC for microaccelerometer

This paper proposes a 164 nW inverter-based capacitive readout integrated circuit (IC) for a microaccelerometer. The designed circuit is implemented using a two-stage inverter-based fully differential current-reuse amplifier to achieve ultra-low power consumption. In order to obtain low magnitudes of current consumption, supply voltage and noise characteristic, the amplifier in the capacitive sensing chain is designed using two cascaded current-reuse inverter stages for both high DC gain and output swing. The low-voltage current-reuse two-stage amplifier configuration with resistive common mode feedback can effectively reduce the power consumption. Two passive resistive common mode detectors and an error amplifier constitute the common mode feedback to enhance the operating range. The correlated double sampling technique is also employed to reduce the flicker (1/f) noise. The IC chip is fabricated using a 0.18-µm 1P6M CMOS process, with an active area of 1.74 mm2, and it consumes an extremely low amount of power, 164 nW at a supply voltage of 0.7 V. The input-referred noise floor of the readout IC is measured to be 4.75 aF/√Hz.

Design and optimization of the ring oscillator based injection locked frequency dividers

In this paper, the large signal operation of the ring oscillator based injection locked frequency divider is analyzed considering the trade-offs among the operating frequency, locking range and power consumption. A large signal model is used to reveal several key findings such as voltage-limited locking ranges and asymmetry between the upper and lower locking bands. They are applied to the optimize the dividers maintaining a good balance among design considerations. Several prototypes, including the divide-by-2 with 3 and 5 stages of inverters, divide-by-3 and divide-by-5, are implemented in a standard 0.18 µm CMOS technology to verify the operation under a large injected signal. As an extension, dual-modulus prescalers are further designed by the integration of switches for different ways of signal mixing. Measurements results show the proposed divide-by-2/3 unit and a divide-by-8/9 with this unit are able to work up to 8 GHz and 4.0 GHz with maximum power consumption of 0.7 mW and 1.5 mW respectively.

Common mode voltage reduction technique in a three‐to‐three phase indirect matrix converter

In this study, common mode voltage (CMV) reduction using space vector pulse-width modulation (SVPWM) technique is proposed for a three-phase induction motor drive fed by a three-to-three phase indirect matrix converter (MC). The proposed SVPWM effectively reduces the peak of the CMV without affecting the output voltage gain. By adopting the proposed SVPWM there is no change in the dv/dt of CMV at the terminal of the machine when compared to the existing method. The proposed control is possible by proper placement of zero vectors in the rectifier stage and discarding zero voltage vectors in the inverter stage of the indirect MC. The control technique is implemented in MATLAB/Simulink environment. Hardware setup is developed and control algorithm is implemented using dSPACE working in conjunction with the FPGA interface board. The results of the proposed SVPWM are compared with the existing method of CMV elimination and the improvement is established. The simulation results obtained are verified with the experimental results. The obtained results confirm a reduction of CMV by 48% (peak) and validate the viability of the proposed scheme in a three-phase induction motor drive system.

Soft-Switched High Voltage Gain Boost-Integrated Flyback Converter Interfaced Single-Phase Grid-Tied Inverter for SPV Integration

A two-stage grid-tied efficient solar photovoltaic (SPV) system with zero voltage switching (ZVS) and zero current switching (ZCS) at the dc–dc converter stage and adaptive synchronization at the inverter stage is proposed. In the first stage, an improved high step-up boost-integrated flyback converter with quasi resonant voltage multiplier cell is proposed. ZVS turn-on of all mosfet s and ZCS turn-off of all diodes of resonant voltage multiplier cell results in high efficient power conversion compared with the conventional boost-integrated flyback converters. Small-sized coupled inductor enhances magnetic utilization in this converter. Second stage consists of a single-phase H-bridge grid interfaced inverter with variable band hysteresis current control technique. Amplitude adaptive notch filter is used to extract fundamental unit voltage vector of grid voltage required for estimation of synchronized reference current for hysteresis controller. A 250 W laboratory prototype is developed and experimentally evaluated. Experimental results demonstrate efficient renewable energy conversion at dc–dc converter stage and quality power injection at dc–ac inverter stage of the proposed grid-tied SPV system under changing solar insulation levels.

Ultra low-power DC voltage limiter for RFID application in 0.18-$\mu $m CMOS technology

In this paper, a low-power DC voltage limiter is designed for radio frequency identification tags. In this design, the low-power bandgap reference (BGR) circuit, which is insensitive to temperature, and also the comparator are used for the voltage limiter circuit. To make the I-V curve approach the ideal one, four inverter stages are employed to the output of the comparator. The structure of the BGR and comparator use only MOSFET transistors that work in subthreshold region when the limiter is inactive. These two blocks have power consumption of 220 pW and 1300 pW, respectively. The limited output voltage is 1.5 V and the current consumption when the tag and the reader are far from each other is 31.56 nA, which is very insignificant compared with the total current consumption of the tag. The chip area of the voltage limiter circuit is 1936 μm2 . The simulation is done in 0.18 μm CMOS technology and the operational frequency is 960 MHz.

A novel simulated multilevel inverter topolo-gy with minimal switches

In this project, an advanced design of simulated multilevel inverters is proposed, which helps to boost the number of output voltage levels and decrease the number of power switches, driver circuits, and the maximum charge of the inverter. It is significant to note down advanced design, the unidirectional power switches are used. Results in decreased complexity and economical. The comparison is done with the conventional topologies and confirmed by simulation outcome. The planned design by using the new technique in produce all voltage levels for a stage inverter which its performance and functional accuracy is confirmed by simulation and experimental results.

Carrier‐based pulse‐width modulation control strategy of five‐phase six‐bridge indirect matrix converter under unbalanced load

To solve the problem that three-to-five-phase matrix converter (MC) cannot supply symmetrical voltages to unbalanced loads, a topology of five-phase six-bridge indirect MC and a carrier-based pulse-width modulation (PWM) method are proposed. A midline bridge is added to the neutral point of five-phase loads in inverter stage. The neutral point voltage is analysed and derived by space vector PWM (SVPWM) method for calculating the duty ratio of midline bridge. Calculations of other five-phase bridge duty ratios of SVPWM method remain unchanged. All of the duty ratios are used to calculate modulation waves of rectifier stage and inverter stage. Driving signals of two-stage power switches are generated by comparing the modulation waves with a carrier, which are used to control the neutral voltage as corresponding zero-sequence voltage. Therefore, five symmetrical output voltage sinusoids are obtained under both balanced and unbalanced loads. Finally, simulation and experimental results are provided to verify the feasibility and validity of the proposed method.

A 60-kW 3-kW/kg Five-Level T-Type SiC PV Inverter With 99.2% Peak Efficiency

A silicon carbide (SiC) T-type LCL inverter can achieve smaller device loss than two-level topology, however, its improvement on power density is limited by current ripple loss on magnetic components as switching frequency increases. This paper presents a five-level T-type (5LT2) photovoltaic (PV) inverter that achieves better utilization of SiC devices than the traditional three-level T-type LCL topology at higher switching frequency. The operation principle of the SiC 5LT2 PV inverter has been presented. The key design aspects including magnetic balancing, short-circuit protection, and digital controller computation time have been discussed and methods are developed. A 60-kW PV converter including boost stage and inverter stage has been built in the laboratory, which achieves a power density of 27 W/in3 and 3 kW/kg, and measured peak efficiency of 99.2%.

Improved PV Inverter Operating Range Using a Miniboost

In the past two decades, the operating voltage of photovoltaic (PV) installation has increased in order to reduce current ratings and system installation costs. Such a large number of PV panels in series (e.g., 1000–1500 V systems) lead to wide variations of PV voltage due undesirable effects such as shading, soiling/dust, aging, and hot surface temperature. A partial shade would normally shut down solar inverters, unless a boost stage is added to the system input to ensure a proper dc-link operating voltage for the inverter. A boost input stage can double the input voltage operating range to extract maximum power under any possible shading and temperature condition. In this paper, a new PV string boost topology arrangement is proposed in the form of a miniboost used for three-phase grid-connected converters. The string miniboost increases the dc voltage range to extend power extraction under shading and low irradiance conditions and only requires to process a fraction of the rated power. The proposed cost-effective solution is further improved by using the inverter peak power envelope at boundary operation, resulting in expanded energy extraction beyond existing techniques. A design procedure to optimally size the miniboost and the peak-power envelope is presented along with a comparative analysis, under different irradiance levels, to illustrate the advantages in energy extraction obtained with the proposed PV string miniboost solution under low voltage and boundary operation. Furthermore, improved efficiency operation schemes and issues of common-mode current are discussed, and three mitigation design techniques intended for three-phase, three-level inverter transformerless topology are presented. Simulations and experimental results using a dual miniboost dc–dc stage and three-phase three-level neutral point clamped inverter are presented to validate the proposed dc-bus extension range and system design.

On Approach to Optimize Manufacturing of a Power Stage Inverter to Increase Integration Rate of Their Elements

On Approach to Optimize Manufacturing of a Power Stage Inverter to Increase Integration Rate of Their Elements

Modulated Predictive Control for Indirect Matrix Converter

Finite State Model Predictive Control (MPC) has been recently applied to several converter topologies as it can provide many advantages over other MPC techniques. The advantages of MPC include fast dynamics, multi-target control capability and relatively easy implementation on digital control platforms. However, its inherent variable switching frequency and lower steady state waveform quality, with respect to standard control which includes an appropriate modulation technique, represent a limitation to its applicability. Modulated Model Predictive Control (M2PC) combines all the advantages of MPC with the fixed switching frequency characteristic of PWM algorithms. The work presented in this paper focuses on the Indirect Matrix Converter (IMC), where the tight coupling between rectifier stage and inverter stage has to be taken into account in the M2PC design. This paper proposes an M2PC solution, suitable for IMC, with a switching pattern which emulates the desired waveform quality features of Space Vector Modulation (SVM) for matrix converters. The switching sequences of the rectifier stage and inverter stage are rearranged in order to always achieve zero-current switching on the rectifier stage, thus simplifying the current commutation strategy.

D‐Q frame predictive current control methods for inverter stage of solid state transformer

Solid state transformer (SST) is regarded as the most emerging technologies of energy internet. The inverter stage of SST supplies sinusoidal voltage to the home users. This study proposes model predictive current control (MPCC) of the inverter stage of SST. It is much easier to perform analysis and design controllers in DQ frame for the inverter stage of SST because all time-varying state variables of the inverter stage become DC time-invariant. Without integral action, the conventional MPCC contains steady-state errors in both d-axis and q-axis currents, hence degrading the closed-loop performance. The integral MPCC (IMPPC) is therefore proposed to eliminate the steady-state errors of the current control system and improve its closed-loop performance. Furthermore, the improved IMPCC is less sensitive to system parameter variations when compared with the conventional MPCC. Simulation and experimental results are utilised to show the successful design and implementation of the conventional MPCC and improved IMPCC. The experimental results reveal that the improved IMPCC has the benefit of fast dynamic performance, zero steady-state errors and insensitive to system parameter variations.

PV Single-Phase Grid-Connected Converter: DC-Link Voltage Sensorless Prospective

In this paper, a dc-link voltage sensorless control technique is proposed for single-phase two-stage grid-coupled photovoltaic (PV) converters. Matching conventional control techniques, the proposed scheme assigns the function of PV maximum power point tracking to the chopper stage. However, in the inverter stage, conventional techniques employ two control loops: outer dc-link voltage and inner grid current control loops. Diversely, the proposed technique employs only current control loop and mitigates the voltage control loop, thus eliminating the dc-link high-voltage sensor. Hence, system cost and footprint are reduced, and control complexity is minimized. Furthermore, the removal of the dc-link voltage loop proportional-integral controller enhances system stability and improves its dynamic response during sudden environmental changes. The system simulation is carried out, and an experimental rig is implemented to validate the proposed technique effectiveness. In addition, the proposed technique is compared with the conventional one under varying irradiance conditions at different dc-link voltage levels, illustrating the enhanced capabilities of the proposed technique.

Predictive Current Control With Instantaneous Reactive Power Minimization for a Four-Leg Indirect Matrix Converter

This paper presents the experimental validation of a predictive current control strategy with minimization of the instantaneous reactive input power for a Four-Leg Indirect Matrix Converter (4Leg-IMC). The topology includes an input matrix converter stage, which provides the dc voltage for a four-leg voltage source converter (VSC) output stage. The VSC's fourth leg provides a path for the zero sequence load current. The control technique is based on a finite control set model predictive control (FCS-MPC) strategy, whereby the switching states for the input and output converters are selected by evaluating a predictive cost function. This results in a simpler approach than that seen in other well-known modulation methods, such as three-dimensional space vector modulation (3D-SVM). Positive dc voltage, (a requirement for the safe operation of the IMC) and minimization of the instantaneous input reactive power are obtained, while maintaining good tracking of the load reference currents. Furthermore, soft switching is achieved by synchronizing the state changes in the input stage with the application of zero voltage space vectors in the inverter stage. The control strategy is experimentally verified using a laboratory prototype.