Inversion-mode Devices Research Articles

Three-dimensional simulation of threshold voltage variations due to an oblique single grain boundary in sub-40 nm polysilicon nanowire FETs

We perform a comparative study of the threshold voltage (Vth) variation between inversion-mode and junctionless nanowire devices with oblique single grain boundary (o-SGB) in a sub-40 nm poly-silicon (Poly-Si) channel using 3D simulation. The Vth variation due to the o-SGB becomes significant as the devices scale down to 20 nm where the o-SGB can fully affect the whole channel potential. In addition, due to relatively less flat energy band in the channel, the junctionless Poly-Si nanowire devices show larger Vth variation compared with the inversion-mode devices.

3-D compact model for nanoscale junctionless triple-gate nanowire MOSFETs, including simple treatment of quantization effects

In this work we briefly review our 2-D compact model for nanoscale junctionless (JL) double-gate (DG) MOSFETs and present and extension for 3-D triple-gate nanowire (TG-NW) devices. The model itself is physics-based and derived in closed-form. Important short-channel effects (SCEs) are covered by the model, as well as carrier quantization effects (QEs). The modeling of QEs in JL devices differs from their common treatment in inversion mode devices and therefore, requires some special attention. The model is verified versus TCAD simulations and measurement data, which were provide through the “SQWIRE” project, by the LETI in Grenoble, France. Additionally, important device characteristics such as symmetry around Vds=0V and continuity of the drain current Ids at derivatives of higher order (up to third order) are in focus of this work.

Effects of HfO2/SiON/SiN stacked trapping layer on operation characteristics of poly-Si flash memory devices

A HfO2/SiON/SiN (HON) bandgap-engineered trapping layer (BETL) on inversion-mode (IM) and junctionless (JL) polycrystalline-Si flash memory devices is investigated in this work. The HON layer is formed by performing a rapid thermal oxidation process between the depositions of SiN and HfO2. For IM device, the programming speed, retention and endurance characteristics are improved by the HON BETL while without degrading its erasing speed when compared to that with HfO2/SiN (HN) BETL. As to the JL device, improved erasing speed and retention characteristics are obtained with HON BETL; high programming speed and good endurance performances of the JL device are also observed. HON BETL is promising to improve retention characteristics of poly-Si flash memory devices since the conduction band level of SiON is higher and the trap density of SiON is lower as compared to those of SiN.

Radiation sensitivity of junctionless double-gate 6T SRAM cells investigated by 3-D numerical simulation

The Junctionless Double-Gate (JL-DGFET) technology is potentially interesting for future ultra-scaled devices, due to the simplified manufacturing process and reduced leakage currents. In this work, we investigate, for the first time, the sensitivity to radiation of 6T SRAM cells built up of JL-DGFETs. A detailed comparison with SRAMs based on inversion-mode devices (FDSOI and IM-DGFET) is performed. Our simulations indicate that JL-DGFET SRAMs are naturally more immune to radiation than FDSOI SRAMs, but more sensitive to radiation than IM-DGFET SRAMs.

Analysis of the leakage current in junctionless nanowire transistors

This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the temperature, device dimensions, and doping concentration have been studied. The results of inversion-mode devices of similar dimensions are also presented for comparison purpose.

Improved Erasing Speed in Junctionless Flash Memory Device by ${\rm HfO}_{2}/{\rm Si}_{3}{\rm N}_{4}$ Stacked Trapping Layer

A junctionless (JL) polycrystalline-based flash memory device with HfO2/Si3N4(HN) stacked trapping layer is studied for the first time. Effects of the HN stacked trapping layer on JL and inversion-mode (IM) flash devices are compared. JL device shows faster programming speed than the IM one because of its heavily doped n-channel. Specially, comparable erasing speed of JL device can be achieved by HN stacked trapping layer due to more effective electron detrapping. JL device with HN stacked trapping layer also shows better retention characteristics and keeps a larger window after 105 programming/erasing cycles, which makes it promising for 3-D memory integration in the future.

Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications

In this paper, we report the potential of junctionless (JL) MOS transistors for ultra low power (ULP) subthreshold logic applications. It is demonstrated that double gate (DG) JL devices, which do not require source or drain extension region engineering, can perform significantly better than conventional inversion mode devices, and comparable with underlap DG MOSFETs for ULP applications. Sensitivity analysis shows that among all device parameters, JL devices exhibit least sensitivity to gate length in comparison with inversion mode and underlap MOSFETs. Results highlight the advantages and challenges of JL transistors for next-generation ULP CMOS logic devices.

Trap density characterization through low-frequency noise in junctionless transistors

Display Omitted HighlightsCurrent noise spectral density of JNTs with different gate dielectrics is evaluated.Devices with SiO2 gate dielectric present lower trap density than the HfSiON ones.Lorentzian noise is more clearly observed in SiO2 gate dielectric devices.HfSiON dielectric devices present time constant higher than SiO2 ones. This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. Along the work, the LFN resultant from both devices was compared in linear and saturation regimes for different gate biases, showing that these devices can exhibit either 1/f or Lorentzian as the dominant noise source depending on the technology and gate bias. Such analysis showed that devices with SiO2 gate dielectric have presented only one corner frequency over the whole frequency range whereas two corner frequencies with different time constants could be observed in devices with HfSiON gate dielectric. The trap density of both devices showed to be similar to the values reported for inversion mode devices in different recent papers, in the order of 1016cm-3eV-1 and 1019cm-3eV-1, for SiO2 and HfSiON gate dielectrics, respectively.

Impact ionization induced dynamic floating body effect in junctionless transistors

Subthreshold Swings, SSs, smaller than theoretical ‘ln(10)kT/q’ are observed in nanowire junctionless (JL) and inversion mode (IM) MuGFETs. The low SS is attributed to the floating body effect in the channel, which is initiated by impact ionization. Comparing with IM devices, decreased drain voltage (Vd) is required for the generation of steep subthreshold slopes in JL devices and the floating body is relatively dynamic. In both JL and IM MuGFETs the floating body effect is suppressed for narrow devices, which indicates this effect is geometry dependent. Moreover, it shows that the short channel JL devices with enhanced electric field can exhibit steep subthreshold slopes at lower Vd. It gives another option to decrease the supply voltage (Vdd) for low power applications of JL devices.

PBTI에 의한 무접합 및 반전모드 다중게이트 MOSFET의 소자 특성 저하 비교 분석

In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> , 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> , and 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate oxide thickness ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0 V; <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">acc</sup> /(CW <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ), in strong accumulation regime.

3-D Numerical Simulation of Bipolar Amplification in Junctionless Double-Gate MOSFETs Under Heavy-Ion Irradiation

The bipolar amplification and charge collection in Junctionless Double-Gate MOSFETs (JL-DGFET) submitted to heavy-ion irradiation are investigated. The transient response of JL-DGFET is compared to that of conventional devices operating in inversion-mode (IM-DGFET). We show that the bipolar amplification is higher in junctionless devices than in conventional inversion-mode devices mainly due to the higher doping levels in the channel which induce larger floating body effects.

기판전압에 따른 나노와이어 Junctionless MuGFET의 전류-전압 특성

In this paper, a current-voltage characteristics of n-channel junctionless and inversion mode(IM) MuGFET, and p-channel junctionless and accumulation mode(AM) MuGFET has been measured and analyzed for the application in high speed and low power switching devices. From the variation of the threshold voltage and the saturation drain current with the substrate bias voltages, their variations in IM devices are larger than junctionless devices for n-channel devices, but their variations in junctioness devices are larger than AM devices for p-channel devices. The variations of transconductance with substrate biases are more significant in p-channel devices than n-channel devices. From the characteristics of subthreshold swing, it was observed that the S value is almost independent on the substrate biases in n-channel devices and p-channel junctionless devices but it is increased with the increase of the substrate biases in p-channel AM devices. For the application in high speed and low power switching devices using the substrate biases, IM device is better than junctionless devices for n-channel devices and junctionless device is better than AM devices for p-channel devices.

Errors Limiting Split-$CV$ Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs

The accuracy of the split- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric and an InP barrier, through a “simulated experiment” procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> method can appreciably underestimate the actual channel mobility in these devices, with an error of >;20% and >;50% on peak mobility and high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> . It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.

Electro-optic metal–insulator–semiconductor–insulator–metal Mach-Zehnder plasmonic modulator

The performance of a CMOS-compatible electro-optic Mach-Zehnder plasmonic modulator is investigated using electromagnetic and carrier transport simulations. Each arm of the Mach-Zehnder device comprises a metal–insulator–semiconductor–insulator–metal (MISIM) structure on a buried oxide substrate. Quantum mechanical effects at the oxide/semiconductor interfaces were considered in the calculation of electron density profiles across the structure, in order to determine the refractive index distribution and its dependence on applied bias. This information was used in finite element simulations of the electromagnetic modes within the MISIM structure in order to determine the Mach-Zehnder arm lengths required to achieve destructive interference and the corresponding propagation loss incurred by the device. Both inversion and accumulation mode devices were investigated, and the layer thicknesses and height were adjusted to optimise the device performance. A device loss of <8dB is predicted for a MISIM structure with a 25nm thick silicon layer, for which the device length is <3μm, and <5dB loss is predicted for the limiting case of a 5nm thick silicon layer in a 1.2μm long device: in both cases, the maximum operating voltage is 7.5V.

Variability of Inversion-Mode and Junctionless FinFETs due to Line Edge Roughness

We investigated the variability impact of line edge roughness (LER) on standard inversion-mode (IM) and junctionless FinFETs (JL-FinFET) designed for the 2009 ITRS high-performance logic 32-, 21-, and 15-nm nodes using technology computer-aided design simulations. Fluctuations in threshold voltage, drive current, leakage current, subthreshold swing, and drain-induced barrier lowering were found to be significantly worse in junctionless devices compared to IM devices at root-mean-square LER amplitudes up to 1 nm. We invoke a simple physical argument to explain these findings based on the operating principles of IM and junctionless devices and the specific means by which LER affects both device architectures. Our findings show that JL-FinFETs are inherently more sensitive to variability than standard IM devices and will pose significant challenges as a feasible post-CMOS technology.

Impact of the Series Resistance in the I-V Characteristics of nMOS Junctionless Nanowire Transistors

The series resistance (RS) of Junctionless Nanowire Transistors (JNTs) with different doping concentrations was extracted from 473 K down to 100 K. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices and the impact of the series resistance on the drain current of the devices was evaluated. The RS analysis was carried out through experimental results and devices tridimensional numerical simulations. According to the study, RS presents opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on RS is noted with the temperature increase, whereas a resistance decrease is obtained with the temperature lowering in IM devices. The parasitic resistance in JNTs affects the drain current in such a way that there may not be a Zero Temperature Coefficient (ZTC) operation point.

Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm

Junctionless accumulation-mode (JAM) devices with channel lengths Lg down to 26 nm were fabricated on a trigate process and compared to conventional inversion-mode (IM) devices. This letter represents the first experimental comparison of short-channel JAM-to-IM devices at matched off-state leakage (Ioff) . The JAM devices show better channel mobility (when moderately doped) and lower gate capacitance than the IM control counterparts at matched Ioff. However, the JAM devices also show reduced gate control and degraded short-channel characteristics. The observed degraded behavior of JAM relative to IM is explained with the aid of device simulations and a simple analytic model of the channel charge.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.