Inversion Layer Charge Research Articles

Pyrolytic fragmentation-induced defect formation in formamidinium lead halide perovskite thin films and photovoltaic performance limits

Defect formation through the fragmented formamidinium cation in lead iodide perovskite leads to the widening charge inversion layer and limited solar cell performance.

Unveiling the Role of H2Plasma for Efficient InP Solar Cells

III–V semiconductors are among the highest performing materials for solar energy conversion devices. Exposing III–V semiconductors to a hydrogen plasma can improve optoelectronic properties and is a critical step in fabricating efficient InP solar cells. However, there is a limited understanding of the changes induced by hydrogen plasma exposure to the surface and in the bulk of III–V semiconductors. Herein, it is demonstrated that a 19.3% efficient p‐InP solar cell with a TiO2electron selective contact layer can be achieved by exposing the InP substrate to hydrogen plasma. Detailed investigations employing ultraviolet photoelectron spectroscopy and capacitance–voltage measurement unveil that the hydrogen plasma exposure on p‐InP leads to charge carrier polarity inversion in the near‐surface region (charge inversion layer) while simultaneously reducing the carrier concentration (charge‐depleted layer) in the bulk. The study provides important insights into the impact of hydrogen plasma exposures on InP which may lead to more efficient optoelectronic devices such as solar cells, photodetectors, light‐emitting diodes, and photoelectrochemical cells.

SIMULATION OF POTENTIAL DISTRIBUTIONS IN THE SPACE CHARGE REGION OF SEMICONDUCTOR STRUCTURES

The methods of description of semiconduc tor-insulator interface characteristics based on process change of MIS type structure was considered. By using Maple Software, the calculations of quantities of inversion layer charge , total charge of semiconductor, inversion layer width and SCR semiconductor total width were m ade. Also, dependence theses quantities from doping level, temperature and surface potential were obtained

Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic

Multi-state room temperature operation of SiOx-cladded Si quantum dots (QD) and GeOx-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density nQM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

Notice of Violation of IEEE Publication Principles: A Compact Model for Digital Circuits Operating Near Threshold in Deep-Submicrometer MOSFET

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy.

High-Mobility Ge pMOSFETs With Crystalline ZrO2 Dielectric

High-mobility Ge pMOSFETs with crystalline ZrO2 gate dielectric are realized and compared against devices with O3/ZrO2, amorphous ZrO2, and Al2O3/ZrO2 gate dielectrics. The crystallization of ZrO2provides for significantly improved effective hole mobility ( $\boldsymbol {\mu }_{\textsf {eff}}$ ) and reduced capacitance equivalent thickness (CET), boosting the transistor drive current. An interfacial Al2O3 passivation layer enhances $\boldsymbol {\mu }_{\textsf {eff}}$ but increases the CET. Passivation-free Ge pMOSFETs with 2.5-nm crystalline ZrO2gate dielectric achieve a higher $\boldsymbol {\mu }_{\textsf {eff}}$ than previously reported unstrained Ge pMOSFETs with the CET below 1 nm, at a high inversion-layer charge density.

Highly Sensitive Bulk Silicon Chemical Sensors with Sub-5 nm Thin Charge Inversion Layers.

There is an increasing demand for mass-producible, low-power gas sensors in a wide variety of industrial and consumer applications. Here, we report chemical-sensitive field-effect-transistors (CS-FETs) based on bulk silicon wafers, wherein an electrostatically confined sub-5 nm thin charge inversion layer is modulated by chemical exposure to achieve a high-sensitivity gas-sensing platform. Using hydrogen sensing as a "litmus" test, we demonstrate large sensor responses (>1000%) to 0.5% H2 gas, with fast response (<60 s) and recovery times (<120 s) at room temperature and low power (<50 μW). On the basis of these performance metrics as well as standardized benchmarking, we show that bulk silicon CS-FETs offer similar or better sensing performance compared to emerging nanostructures semiconductors while providing a highly scalable and manufacturable platform.

Influence of the Frontside Charge Inversion Layer on the Minority Carrier Collection in Backside Contacted Liquid Phase Crystallized Silicon on Glass Solar Cells

External quantum efficiency and light beam induced current measurements were used to investigate backside contacted solar cells made on p-type, liquid phase crystallized silicon on glass (LPC-Si). Among other differences, these cells had either a SiOxNy or an Al2O3/SiO2 based frontside surface passivation (interlayer). From the measurements it was observed that the cell with the SiOxNy interlayer showed a charge carrier collection from below the absorber contact and from outside the cell area that is much larger than expected from the typical diffusion length in LPC-Si. This was in contrast to the cell with the Al2O3/SiO2 interlayer, which showed the expected behavior. It was also observed that for the cell with the SiOxNy interlayer, both the collection outside and the collection inside the cell area were strongly bias light dependent. It is argued that these charge carriers collected from outside the cell area are collected through a frontside charge inversion layer. This was supported by an analysis of the measured wavelength and bias light dependence of the collection outside the cell area for the cell with the SiOxNy interlayer. The measured fixed charge density of the interlayer stack with the SiOxNy layer was used to estimate the sheet resistance of the frontside charge inversion layer and this sheet resistance could explain the bias light dependence of the collection outside the cell area. The fixed charge density was also used to simulate the excess carrier density dependence of effective surface recombination at the SiOxNy/c-Si interface and these simulation results could explain the bias light dependence of the collection inside the cell area.

Charge Transport in MoS2/WSe2 van der Waals Heterostructure with Tunable Inversion Layer.

Despite numerous studies on two-dimensional van der Waals heterostructures, a full understanding of the charge transport and photoinduced current mechanisms in these structures, in particular, associated with charge depletion/inversion layers at the interface remains elusive. Here, we investigate transport properties of a prototype multilayer MoS2/WSe2 heterojunction via a tunable charge inversion/depletion layer. A charge inversion layer was constructed at the surface of WSe2 due to its relatively low doping concentration compared to that of MoS2, which can be tuned by the back-gate bias. The depletion region was limited within a few nanometers in the MoS2 side, while charges are fully depleted on the whole WSe2 side, which are determined by Raman spectroscopy and transport measurements. Charge transport through the heterojunction was influenced by the presence of the inversion layer and involves two regimes of tunneling and recombination. Furthermore, photocurrent measurements clearly revealed recombination and space-charge-limited behaviors, similar to those of the heterostructures built from organic semiconductors. This contributes to research of various other types of heterostructures and can be further applied for electronic and optoelectronic devices.

Electrical characteristics of metal–insulator–semiconductor and metal–insulator–semiconductor–insulator–metal capacitors under different high-k gate dielectrics investigated in the semi-classical and quantum mechanical models

In this paper the electrical characteristics of metal–insulator–semiconductor (MIS) and metal–insulator–semiconductor–insulator–metal (MISIM) capacitors with (100)-oriented p-type silicon as a substrate under different high- k gate dielectrics (SiO2, HfO2, La2O3 and TiO2) are investigated in the semi-classical and quantum mechanical models. We review the quantum correction in the inversion layer charge density for p-doped structures. The purpose of this paper is to point out the differences between the semi-classical and quantum mechanical charge descriptions at the insulator–semiconductor interface and the effect of the type of oxide and their position (gate oxide or buried oxide) in our structures. In particular, capacitance–voltage (C– V), relative position of the sub-band energies and their wavefunctions are studied to examine qualitatively and quantitatively the electron states and charging mechanisms in our devices. We find that parameters such as threshold voltage and device trans-conductance are enormously sensitive to the proper treatment of quantization effects.

A TCAD Low-Field Electron Mobility Model for Thin-Body InGaAs on InP MOSFETs Calibrated on Experimental Characteristics

A simple analytical low-field electron mobility model to be employed for technology computer-aided design of thin-body MOSFETs based on III-V compound semiconductors is presented. The scattering sources accounted for in the model are Coulomb centers, lattice vibrations (i.e., phonons), and surface roughness. The dependence of the thin-body effective thickness on the transverse electric field is calculated through 1-D Schrodinger–Poisson numerical simulations and is introduced in the model by means of an appropriate analytical function. Then, the free-electron density distribution is determined by considering both quantization effects and oxide–semiconductor interface traps. The model is calibrated on the experimental data collected on In0.53Ga0.47As-on-InP thin-body MOSFETs featuring body thicknesses as low as 5 nm. In particular, the model accurately reproduces $C_{G}$ – $V_{\mathrm{ GS}}$ characteristics, effective mobility against inversion layer charge plots, and $I_{\mathrm{ DS}}$ – $V_{\mathrm{ GS}}$ curves at low $V_{\mathrm{ DS}}$ .

Understanding short channel mobility degradation by accurate external resistance decomposition and intrinsic mobility extraction

An intrinsic short channel mobility extraction method is proposed by measuring two short-channel devices with different channel lengths and the same source/drain and contact geometry. The constant and dynamic components of external resistance are separated. Short-channel mobility degradation is observed and its origin is studied. The possible causes of the halo doping and the non-uniformity of the inversion layer charge are accounted for. The weaker temperature dependence of short channel devices indicates that the short channel mobility degradation may result from some combination of defect-induced and Coulomb-induced scattering near the S/D regions, differing in severity between NFETs and PFETs which employ, respectively, ion implant and embedded epitaxy as the primary component of S/D design.

A Novel Method to Extract Carrier Mobility and Threshold Voltage in High-Voltage DDD MOSFETs

In this work, we apply the Hauser technique and combine a newer inversion layer charge model to extract the effective channel carrier mobility (μeff) and threshold voltage (Vth) of several high-voltage DDD MOSFETs with different dimensions in channel length and width. This paper proposes and demonstrates that our new method is a novel and efficient to extract the carrier mobility and threshold voltage in the DDD MOSFET, meanwhile, the extracted data is well consistent with UT model. And, only the extracted values by our new method and BCV method can clearly reflect the narrow-width effect which results from the so called LOCOS isolation technique. Therefore, it is clearly to see that our extraction technique can exactly reflect the device characteristics in high-voltage DDD MOSFETs.

Quantum mechanical compact modeling of symmetric double-gate MOSFETs using variational approach

A physics-based analytical model for symmetrically biased double-gate (DG) MOSFETs considering quantum mechanical effects is proposed. Schrödinger's and Poisson's equations are solved simultaneously using a variational approach. Solving the Poisson and Schrödinger equations simultaneously reveals quantum mechanical effects (QME) that influence the performance of DG MOSFETs. The inversion charge and electrical potential distributions perpendicular to the channel are expressed in closed forms. We systematically evaluated and analyzed the potentials and inversion charges, taking QME into consideration, in Si based double gate devices. The effect of silicon thickness variation in inversion-layer charge and potentials are quantitatively defined. The analytical solutions provide good physical insight into the quantization caused by quantum confinement under various gate biases.

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

In this paper, the quantum mechanical (QM) effects in bulk MOSFETs and their modeling approaches in the compact modeling framework are reviewed. As the device dimensions are scaled to the sub-100 nm range, QM effects affect the device properties, such as effective oxide thickness, inversion layer charge density and profile, threshold voltage, effective bandgap, gate capacitance, mobility, surface potential, subthreshold characteristics, drain current, and gate leakage current. The classical theory is no longer sufficient for accurate modeling of these device characteristics. In this paper, models which have incorporated QM effects to obtain the device characteristics are discussed and compared. The roles of QM effects in affecting some of the device properties are also presented.

Deterministic solution of the 1D Boltzmann transport equation: Application to the study of current transport in nanowire FETs

In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FETs operating under quasi-ballistic conditions. Starting from general expressions of the current–voltage characteristics worked out in a previous paper, we extract the above parameters and their functional dependence on inversion-layer charge and device length. The computation is based on a rigorous analytic solution of the BTE and on a numerical solution of the coupled Schrödinger–Poisson equations, by which multiple subbands are taken into account. We propose three different definitions of the ballistic ratio, clarify their meaning and compute their values against the gate voltage and the device length. As opposed to most phenomenological treatments addressing this subject for 2D nanoscale MOSFETs, the strength of our approach is that the aforementioned parameters can be computed from the knowledge of the scattering probabilities, without introducing any major simplifying assumptions.

Magneto-modulation of gate leakage current in 65 nm nMOS transistors: Experimental, modeling, and simulation results

We introduce experimental results that reveal a small static and a slowly varying-dynamic magnetic field B induces a magneto-modulation of the gate leakage current of a 65 nm nMOSFET. For the case of a 100 mT (mili-Tesla) static B field a variation of the 6% (1.5 nA/27 nA) of the gate current is observed. For a 5 Hz slowly varying (±100 mT) square pulsed magnetic field, the gate current dynamic variation raises up to 18% (4.8 nA/27 nA). These experimental observations are explained in terms of space and time modulation of the two-dimensional surface inversion layer charge. The static B field dependent model is validated through Minimos-NT numerical simulations, while the dynamic B field experimental observations are reproduced with a SPICE macro-model, which uses the static device model as initial condition for the dynamic model. With this model we are able to predict the impact of small static and dynamic B fields on the gate leakage current and channel current interference of low-dimensional MOS transistors. We also propose this electro-magnetic experimental technique as an alternative for detailed exploration of the Si–SiO 2 interface properties for 2 nm or thinner gate oxides, as well as for low-dimensional semiconductor devices.

Tunneling-lifetime model for metal-oxide-semiconductor structures

In this paper we investigate the basic physics of charge carriers (electrons) leaking out of the inversion layer of a metal-oxide-semiconductor capacitor with a biased gate. In particular, we treat the gate leakage current as resulting from two combined processes: (1) the time-dependent decay of electron wave packets representing the inversion-layer charge and (2) the local generation of ``new'' electrons replacing those that have leaked away. As a result, the gate current simply emerges as the ratio of the total charge in the inversion layer to the tunneling lifetime. The latter is extracted from the quantum dynamics of the decaying wave packets, while the generation rate is incorporated as a phenomenological source term in the continuity equation. Not only do the gate currents calculated with this model agree very well with experiment, the model also provides an onset to solve the paradox of the current-free bound states representing the resonances of the Schr\odinger equation that governs the fully coupled metal-oxide-semiconductor system.

Compact model of short-channel MOSFETs considering quantum mechanical effects

A unified analytical model for the I–V characteristics of short channel bulk nMOSFETs with 〈100〉 Si surface orientation valid for the subthreshold, linear and saturation regions is presented. In this model, the inversion layer charge is obtained considering quantum mechanical (QM) effects. The field dependent mobility variations, velocity saturation of carriers and secondary effects such as DIBL and channel length modulation have been incorporated in this model. There is a smooth transition in the current from subthreshold to above threshold and also from linear to saturation regions of operation. This results in highly continuous channel conductance (gds) and transconductance (gm), which are important circuit parameters in small signal analysis. In addition, the result of a few benchmark tests shows that the model holds good promise for analog circuit design. The model has been implemented in SABER, a circuit simulator. The result from the model shows an excellent agreement with two-dimensional device simulator and experimental data.

Simulation of Capacitance-Voltage characteristics of Ultra-thin Metal-Oxide-Semiconductor Structures with Embedded Nanocrystals

AbstractThis paper presents an approach to model quantum mechanical effects in solid-state devices such as Metal Oxide Semiconductor (MOS) capacitor with and without nanocrystal in the oxide at the device simulation level. This quantum-mechanical model is developed to understand finite inversion layer width and threshold voltage shift. It allows a consistent determination of the physical oxide thickness based on an agreement between the measured and modeled C-V curves. However, as for thinner oxides finite inversion layer width effects become more severe, quantum-mechanical model predicts higher threshold voltage than the classical model. The inversion-layer charge density and MOS capacitance in multidimensional MOS structures are simulated with various substrate doping profiles and gate bias voltages. The effectiveness of the QM correct method for modeling quantum effects in ultrathin oxide MOS structures is also investigated. The CV characteristic is used as a tool to compare results of the QM correction with that of the Schrödinger–Poisson (SP) solution and Classical solution The variation of (different parameters) for various doping profiles at different gate voltages is investigated.