Inverse Narrow Width Effect Research Articles

Mobility Enhancement and Abnormal Humps in Top-Gate Self-Aligned Double-Layer Amorphous InGaZnO TFTs

The mobility enhancement and the positive bias stress of top-gate self-aligned TFTs using the a-IGZO channel with a front barrier are investigated. The a-IGZO front barrier can keep electrons in the a-IGZO channel away from the top-gate oxide to significantly enhance the electron mobility at the top gate operation. The parasitic channel induces a hump in the transfer characteristics. The positive bias stress shifts the hump to the negative voltage abnormally. The H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O in the polymer film on array layer is responsible for the abnormal shift. The H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O diffuses into the top-gate insulator and is electrolyzed to create H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> , which forms a parasitic channel with a negative shift of threshold voltage, leading to the abnormal hump. The abnormal humps are increasingly significant with the increasing channel width and the decreasing channel length. The channel width dependence on positive bias stress is due to the inverse narrow width effect caused by the fringe electric field. The channel length dependence on positive bias stress is due to the H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion toward the center of the parasitic channel from both the source and drain sides.

A 16 ns, 28 fJ Wide-Range Subthreshold Level Converter Using Low-Voltage Current Mirror

This paper proposes a high-speed and energy-efficient low-voltage current mirror-based level converter (LCM LC) which can perform a wide-range conversion of a subthreshold input signal (180 mV) to an above-threshold output signal (1.2 V). The proposed level converter utilizes low-voltage current mirror (LCM) circuit with high-threshold-voltage (hvt) PMOS devices in the pull-up network, which drives a switching current from high supply rail to output node during the high-to-low transition of an input signal to ensure wide-range conversion. The driving capability of the pull-down network in LCM LC is increased by employing inverse-narrow-width-effect (INWE)-aware low-threshold-voltage (lvt) NMOS devices in order to perform a high-speed operation. This level converter employs multi-threshold CMOS devices and is implemented in 45 nm technology using Cadence Virtuoso. The LCM LC exhibits a delay of 16.4 ns, energy per transition of 28.1 fJ and static power of 412 pW which are observed using Spectre circuit simulator for the target conversion from 0.2 to 1.2 V at a signal frequency of 1 MHz.

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

In this study, the authors propose a sub-threshold standard cell library in which the quintessence is a quasi-Schmitt-trigger logic design scheme and the inverse narrow width effect aware sizing method. The techniques can improve the I on-to-I off ratio of the logic cells effectively and provide a significant suppression in leakage current, enhancing the robustness of the circuits. Simulation results show that the NAND3 and NOR3 logics with the new techniques achieve 40–60% and 30–50% reductions in leakage power compared with conventional logic circuits, respectively, when the voltage is scaled down to sub-threshold region. Again, they also exhibit considerable improvements in process variation immunity and power-delay product.

An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications

Ultra-low power design techniques specifically subthreshold designs, play a vital role in Internet of things systems that survive on limited power budget or harvested energy sources. In this paper, the width and length of a transistor operating at subthreshold region are optimized considering the nano-scale effects such as reverse short channel effect and inverse narrow width effect, which improves performance, reduces area, minimizes sensitivity to process variation and reduces energy consumption. A subthreshold standard cell library consisting of 45 standard cells is designed. The physical synthesis of ISCAS′85 benchmark circuits and a floating point unit shows that energy savings in area-mapped design are up to 23% whereas area savings in performance-mapped design are up to 30%. The measurement results from a test chip fabricated in industrial 130 nm technology demonstrate a performance improvement of up to 27%, reduction in delay variability of up to 24% and energy savings of 18%.

Six‐track multi‐finger standard cell library design for near‐threshold voltage operation in 130 nm complementary metal oxide semiconductor technology

In this study, a six-track standard cell library with a multi-finger layout structure is proposed to improve the delay, energy, and area of the digital circuit design for near-threshold operation. The proposed library is optimised by using the parasitic effects of the technology and optimising the layout. To enhance the performance and energy efficiency, inverse narrow width effect has been considered in the design, whereby the minimum width of the process was used as the based width unit. To minimise the design area, the standard cell was designed in the lowest possible height with a multi-finger layout structure. The proposed library with a few basic cells was developed and characterised in 130 nm technology, which is available for synthesis and automatic place-and-route (P&R). The proposed library was analysed and compared with two eight-track multiplier layout libraries in the cell and block design level. Based on the place-and-route results of ISCAS'85 benchmark circuits, the proposed six-track library could achieve up to 27% of delay improvement, 29% energy reduction and 44% area reduction as compared to the multiplier structure library at the minimum critical path delay.

An energy-efficient variation aware self-correcting latch

Power dissipation is a prime concern in sub-nanometer VLSI regime and, therefore, operation at near/sub-threshold regime has gained importance. However, though energy efficient, a system performance/functionality is at stake, because of the increase in the variability in near/sub-threshold regime. Therefore, resilient circuit approaches are important in alleviating the performance degradation resulting from Process, Voltage, and Temperature (PVT) variations. This paper presents an energy efficient and resilient circuit design approach using novel self correcting latches. The proposed technique corrects the faults due to timing violation caused by variations in datapaths and sequential elements automatically, thereby lowering PVT variation induced performance degradation. Our technique employs Inverse Narrow Width Effect (INWE) in designing the self-correcting latches to reduce performance variability. In this technique INWE is used to realize devices which have equal gate capacitances and different current drives. We validate the proposed methodology on several ISCAS′89 benchmark circuits and 74X series circuits. Simulation results show that by employing the proposed methodology, an average improvement of ∼20%, 10%, and 4.85% in delay, power delay product, and layout area, respectively, over previous resilient methodologies can be achieved.

Effective Drive Current for Near-Threshold CMOS Circuits’ Performance Evaluation: Modeling to Circuit Design Techniques

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts.

A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 10~20% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 10~20% with a simply controlled body-biasing scheme compared with the conventional one.

Adjustable Silicon Corner Rounding Radius by Wet Technique

Shallow trench isolation (STI) and active area (AA) top corner rounding is important to devices performance. AA top corner rounding techniques include STI etch, linear oxidation , H2 annealing and wet oxide pull back (PB). However, conventional STI etch will caused AA facet and need to additional thermal in linear oxidation or H2 annealing processes. Wet oxide PB is easily to control the pad oxide etching amount and reach desired AA top corner top rounding radius.In this study, different pad oxide PB amount by Hydrogen Fluoride (HF) with corner rounding correlation were shown. At high pad oxide PB amount, additional hydrogen peroxide (H2O2) with dilute HF can optimize the AA top corner profile and enlarge the corner radius. Sharp AA corners profile caused gate oxide formation thickness thinning let strong electrical filed at AA corner. In wafer acceptable test had brought about double hump effect in I-V characteristics and inverse narrow width effect. Pad oxide PB following STI Etch is used by HF to let the silicon top corner be exposed and beneficial for increasing AA top corner rounding radius of liner oxidation process. This study gives some course to improve the silicon corner profile and AA top corner radius. After STI etch process, different wet etch amount were used for pad oxide PB from pad nitride by 0.49% HF process time adjustment. Different wet oxide PB amount were split for corner radius comparison. As oxide PB amount increased from 0nm to 5nm the corner radius can be improved, and the best radius showed at PB 5nm. When oxide PB amount add to 7.5nm, the corner radius became worse slightly. The radius of PB 10nm is even worse and close to without oxide PB process. This result suspected that AA corner profile might be changed in wet oxide PB process. When oxide PB amount increase, oxide etch rate might decrease and exposed silicon corner be continually damaged by HF erosion. The silicon damage of PB 5nm is slight and can be recovered after linear oxidation thermal process. At PB 7.5nm the AA corner “stepped” profile was observed. It can explain while the PB amount >5nm the corner rounding radius decrease. Because the “stepped” profile caused the corner split two curvatures then the radius decrease. The “stepped” profile of PB amount >7.5nm still be find after linear oxidation. To reduce the AA top corner “stepped” profile, the post-HF treatment’s AA silicon exposed in following APM process. The AA top corner and silicon sidewall which with APM treatment is clipping suspect H2O2 oxidize silicon and NH4OH consume the oxide caused. This profile made the region of exposed silicon to be deficient and pointed in AA geometry of silicon corner. The pointed AA top corner profile is unhelpful for corner rounding radius improvement, so the key factor of AA top rounding profile is corner silicon loss controller. In order to reduce the corner silicon loss amount, using H2O2 to replace the APM and dilute HF concentration to do oxide PB. This optimistic experience will be expected lower the exposed corner silicon consumption and corner rounding radius improvement. According oxide PB amount 5nm and 7.5nm comparison in 0.49%HF, the corner radius reduced 0.1nm when the PB increased. Nonetheless, HF concentration changed from 0.49% to 0.1% and H2O2 addition, the corner radius can be improved 0.3nm and 0.7nm. This result proved that the corner silicon profile of PB >5nm will be damaged in concentrated HF wet etch. Change to dilute HF concentration will reduce corner silicon loss and enable to recover corner silicon which with “stepped” profile by additional H2O2 treatment. As the higher oxide PB amount the pad oxide PB rate will become lower cause that without oxide protected corner silicon will be damaged and result in “stepped” profile. Nevertheless, using dilute HF can lower corner silicon loss and reduce the silicon erosion which without oxide protected. Additional H2O2 treatment introduced the rounding and smooth profile. The relationship between pad oxide PB and AA top corner rounding is established in STI process. The AA top corner radius of oxide PB amount 5nm can be improved 2.6nm compare to without PB process. When oxide PB amount >5nm the corner radius is decreased. The decreasing corner radius come from higher oxide PB amount that without oxide protected corner silicon will be damaged. This phenomenon result in “stepped” profile with difference curvature and corner radius decreasing. Dilute HF with H2O2 treatment is demonstrated that it is beneficial to reduce and recover the corner damaged. Figure 1

Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits

Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifinger gate structure (MFGS) empirically using 3-D technology computer aided design simulations. Thereafter, we use these stress models along with a model for INWE to establish a physics-based relationship between effective drive current and number of fingers in MFGS. We also design single-stage combinational standard cells and predict the values of their logical effort using our approach. The performance of the standard cells using our approach improves significantly compared with the conventional approach. Inverter chains (buffers) are representative and extensively used multistage circuits. Using our model of effective drive current, we propose a methodology to optimize the buffer designed and layout to maximize performance in stress-enabled technologies. We observe that the proposed methodology results in a significant reduction in power dissipation up to 35% and reduction in silicon area up to 43% as compared with the existing methodologies.

A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range

Level shifters (LS) are crucial interface circuits for multisupply voltage designs, and it is challenging to achieve both robust and efficient level conversion from subthreshold to aforementioned threshold. In this brief, we propose two circuit techniques for a novel subthreshold LS with wide conversion range. First, we introduce a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion. Second, we explore the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction. When implemented in a commercial 65-nm MTCMOS process, the proposed LS achieves robust conversion from deep subthreshold (sub-100 mV) to nominal supply voltage (1.2 V). For the target conversion from 0.3 to 1.2 V, the proposed LS shows on average 25.1-ns propagation delay, 30.7-fJ energy efficiency, and 2.5-nW leakage power across 25 test chips.

An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.

Subthreshold DC‐gain enhancement by exploiting small size effects of MOSFETs

A pseudo-cascode split-transistor technique is proposed for DC-gain enhancement of amplifiers in the subthreshold by exploiting the small size effects of metal–oxide semiconductor field effect transistors (MOSFETs) including the reverse short-channel effect and the inverse narrow-width effect. It requires no body-biasing and occupies a small area. A compact 114 μm2 two-stage amplifier with pseudo-cascode compensation for in-pixel amplification in vision sensors has been designed using the proposed technique. A total of 10 samples of split-transistors and amplifiers fabricated in an UMC 0.18 μm standard CMOS process were measured. More than half of the tested split-transistors show considerable DC-gain enhancement over a wide range of bias currents and nine amplifiers have increased DC gains larger than 85 dB at about 4 nA power consumption.

Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxidesemiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, 0.18 μm 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

A 40 nm Dual-Width Standard Cell Library for Near/Sub-Threshold Operation

Near/sub-threshold operation is promising to achieve energy minimization when high performance is not required. The device sizing in sub-threshold region is different from super-threshold region due to significantly different IV characteristics and impact of parasitic effects in these two regions. We have investigated the impact of the inverse narrow width effect (INWE) on transistor drain current in the near/sub-threshold region at three different technology nodes (90 nm, 65 nm, and 40 nm) and proposed an INWE-aware sub-threshold device sizing method to mitigate the impact of INWE to reduce delay, power consumption and area. We applied the proposed device sizing method to designing an INWE-aware standard cell library and achieved up to 20% less delay, 34% less power consumption and 47% less area, compared with the sub-threshold library designed using conventional sizing method. For further optimization, we proposed a dual-width library by combining the INWE-aware library and the minimum sized library. A near-threshold baseband processor designed with the dual width library achieved a total power consumption of ~ 4 μW with 6 MHz at 0.5 V, which is 30% better than the counterpart design.

Analytical modelling of inverse narrow width effect for narrow channel STI MOSFETs

This paper presents an analytical physics-based model for the width dependence of threshold voltage of nano-scale MOSFETs considering the combined effect of gate-fringing and dopant redistribution. Shallow trench isolated MOSFETs have been considered in the 90 nm and 65 nm technology node. An analytical expression for the trench oxide parasitic capacitance is derived by taking into account the enhanced depletion depth caused due to the gate-fringing field at the trench oxide sidewalls and dopant redistribution in the channel. The short channel effects on the depletion charges have been taken care of while deriving this expression. This is then used to develop the model for a width-dependent threshold voltage shift. The developed model has been validated by comparing the results predicted from the derived model with experimental data as well as simulation data. In addition, the developed model has been compared with a similar model available in the literature. It has been demonstrated that our model predicts more correctly the inverse narrow width effect of nano-scale devices compared to the existing model.

Enhancement of Data Retention Time in DRAM through Optimization of Sidewall Oxidation Precleaning

This paper proposes a DRAM data retention time enhancement method that minimizes silicon loss and undercut at STI sidewall by reducing the SC1 (Standard Cleaning) time. SC1 time optimization debilitates the parasitic electric field in STI's top corner, which reduces an inverse narrow width effect to result in reduction of channel doping density without increasing the subthreshold leakage of cell Tr. Moreover, it minimizes the electric field in depletion area from cell junction to P-well, increasing yield or data retention time.

Preference of designing CMOS subthreshold logic circuits using uniform-size transistors

We demonstrate that designing subthreshold digital circuits using only similarly-sized PMOS and similarly-sized NMOS transistors usually results in faster circuits than those scaled according to conventional design methods such as Logical Effort. This statement is valid if both transistor types exhibit the inverse narrow-width effect. For proving the claim, a number of circuits are designed in both ways, compared, and the results are reported.

STI Liner Evolution as the CMOS Scaling Down

As the planar CMOS transistor devices scaling down, a lot of original process have to be optimized, developed or changed to meet the evolutional requirement, and the new process elements were continuously implemented into the manufacture. The STI-liner is one of the processes from the STI module, which comes after the trench etch and before the trench gap-fill, to provide an excellent interface and good adhesion between the silicon and the oxide. While the device scaling down, some device issues, such as, the incident of dislocations which impacted on the device leakage current, the dopant segregation which result in the threshold voltage variation and impact the inverse narrow width effect (INWE) and the gate oxide integrity (GOI), etc, are associated with the STI module and can be improved by the STI-liner process. The STI liner process is evolved from the furnace oxidation, the dry RTO, the nitrided oxide liner to the ISSG.

Electrical assessment of lithographic gate line-end patterning

Line-end pullback is a major source of patterning problems in low-k1 lithography. Lithographers have been well-served by geometric metrics such as critical dimension (CD) at a gate edge; however, the ever-rising contribution of line-end extension to layout area necessitates reduced pessimism in qualification of line-end patterning. Electrically aware metrics for line-end extension can be helpful in this regard. The device threshold voltage is, with nominal patterning, a weak function of line-end shapes. However, the electrical impact of line-end shapes can increase with overlay errors, since displaced line-end extensions can be enclosed in the transistor channel, and nonideal line-end shape will manifest as an additional gate CD variation. We propose a super-ellipse parameterization that enables exploration of a large variety of line-end shapes. Based on a gate capacitance model that includes the fringe capacitance due to the line-end extension, we model line-end-dependent incremental current Ion and Ioff to reflect inverse narrow width effect. Last, we calculate the Ion and Ioff considering line-end shapes as well as line-end extension length, and we define a new electrical metric for line-end extension-namely, the expected change in Ion or Ioff under a given overlay error distribution. Our model accuracy is within 0.47% and 1.28% for Ion and Ioff, respectively, compared to 3-D TCAD simulation in a typical 45-nm process. Using our proposed electrical metric, we are able to quantify the electrical impact of optical proximity correction, lithography, and design rule parameters, and we can quantify trade-offs between cost and electrical characteristics.