Electrical assessment of lithographic gate line-end patterning

Abstract

Line-end pullback is a major source of patterning problems in low-k1 lithography. Lithographers have been well-served by geometric metrics such as critical dimension (CD) at a gate edge; however, the ever-rising contribution of line-end extension to layout area necessitates reduced pessimism in qualification of line-end patterning. Electrically aware metrics for line-end extension can be helpful in this regard. The device threshold voltage is, with nominal patterning, a weak function of line-end shapes. However, the electrical impact of line-end shapes can increase with overlay errors, since displaced line-end extensions can be enclosed in the transistor channel, and nonideal line-end shape will manifest as an additional gate CD variation. We propose a super-ellipse parameterization that enables exploration of a large variety of line-end shapes. Based on a gate capacitance model that includes the fringe capacitance due to the line-end extension, we model line-end-dependent incremental current Ion and Ioff to reflect inverse narrow width effect. Last, we calculate the Ion and Ioff considering line-end shapes as well as line-end extension length, and we define a new electrical metric for line-end extension-namely, the expected change in Ion or Ioff under a given overlay error distribution. Our model accuracy is within 0.47% and 1.28% for Ion and Ioff, respectively, compared to 3-D TCAD simulation in a typical 45-nm process. Using our proposed electrical metric, we are able to quantify the electrical impact of optical proximity correction, lithography, and design rule parameters, and we can quantify trade-offs between cost and electrical characteristics.