Inverse Lithography Technology Research Articles

Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization

Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization

Inverse lithography physics-informed deep neural level set for mask optimization.

As the feature size of integrated circuits continues to decrease, optical proximity correction (OPC) has emerged as a crucial resolution enhancement technology for ensuring high printability in the lithography process. Recently, level set-based inverse lithography technology (ILT) has drawn considerable attention as a promising OPC solution, showcasing its powerful pattern fidelity, especially in advanced processing. However, the massive computational time consumption of ILT limits its applicability to mainly correcting partial layers and hotspot regions. Deep learning (DL) methods have shown great potential in accelerating ILT. However, the lack of domain knowledge of inverse lithography limits the ability of DL-based algorithms in process window (PW) enhancement, etc. In this paper, we propose an inverse lithography physics-informed deep neural level set (ILDLS) approach for mask optimization. This approach utilizes level set-based ILT as a layer within the DL framework and iteratively conducts mask prediction and correction to significantly enhance printability and PW in comparison with results from pure DL and ILT. With this approach, the computational efficiency is significantly improved compared with ILT. By gearing up DL with the knowledge of inverse lithography physics, ILDLS provides a new and efficient mask optimization solution.

Effective multi-objective inverse lithography technology at full-field and full-chip levels with a hybrid dynamic priority algorithm.

Inverse lithography technology (ILT), such as source mask optimization (SMO), is used to improve lithography performance. Usually, a single objective cost function is selected in ILT, and an optimal structure for one field point is achieved. The optimal structure is not the case for other images at full field points where the aberrations of the lithography system are different, even in high-quality lithography tools. The optimal structure that must match the high-performance images at the full field is urgently required for extreme ultraviolet lithography (EUVL). In contrast, multi-objective optimization algorithms (MOAs) limit the application of multi-objective ILT. Assigning target priority is incomplete in current MOAs, which results in the over-optimization of some targets and under-optimization of others. In this study, multi-objective ILT and a hybrid dynamic priority (HDP) algorithm were investigated and developed. High-performance images with high fidelity and high uniformity were obtained at multi-field and multi-clip areas across the die. A hybrid criterion was developed for the completion and reasonable prioritization of each target to ensure sufficient improvement. Compared to the current MOAs, the uniformity of images at full-field points was improved by up to 31.1% by the HDP algorithm in the case of multi-field wavefront error-aware SMO. The multi-clip source optimization (SO) problem showed the universality of the HDP algorithm to deal with different ILT problems. It acquired higher imaging uniformity than existing MOAs, which indicated that the HDP is more qualified for multi-objective ILT optimization than existing MOAs.

Curvilinear mask optimization with refined generative adversarial nets

Inverse lithography technology (ILT) can optimize the mask to gain the best process window and image quality when the design dimension shrinks. However, as a pixel level correction method, ILT is very time-consuming. In order to make the ILT method useful in real mask fabrication, the runtime of ILT-based optical proximity correction mask must evidently decrease while keeping the good lithographic metric performance. Our study proposes a framework to obtain the curvilinear ILT mask with generative adversarial network (GAN). It is subsequently refined with the traditional ILT to exclude unexpected outliers generated by the GAN method. We design conditional GAN, reverse GAN (RGAN), and high discretion GAN (HDGAN) to generate curvilinear ILT mask. Their runtime and the performance are compared. Compared with the CILT method, the speed of GAN type methods with the afterward refinement is increased by an order of magnitude. The RGAN has a better performance in edge placement error and process variation band evaluation, and HDGAN has a better performance in the mask error enhancement factor evaluation. The designed RGAN and HDGAN are promising in actual application to generate the curvilinear mask. They can evidently decrease the runtime and have better lithographic metric performance.

Label-free neural networks-based inverse lithography technology.

Neural network-based inverse lithography technology (NNILT) has been used to improve the computational efficiency of large-scale mask optimization for advanced photolithography. NNILT is now mostly based on labels, and its performance is affected by the quality of labels. It is difficult for NNILT to achieve high performance and extrapolation ability for mask optimization without using labels. Here, we propose a label-free NNILT (LF-NNILT), which is implemented completely without labels and greatly improves the printability of the target layouts and the manufacturability of the synthesized masks compared to the traditional ILT. More importantly, the optimization speed of LF-NNILT is two orders of magnitude faster than the traditional ILT. Furthermore, LF-NNILT is simpler to implement and can achieve better solvers to support the development of advanced lithography.

Source and mask optimizing with a defocus antagonism for process window enhancement.

With the continuous reduction of critical dimension (CD) of integrated circuits, inverse lithography technology (ILT) is widely adopted for the resolution enhancement to ensure the fidelity of photolithography, and for the process window (PW) improvement to enlarge the depth of focus (DOF) and exposure latitude (EL). In the photolithography, DOF is a critical specification which plays a vital role for the robustness of a lithographical process. DOF has been investigated to evaluate the optimization quality of ILT, but there is not a clear scenario to optimize the DOF directly. In this paper, the source and mask optimization (SMO) based on defocus generative and adversarial method (DGASMO) is proposed, which takes the source, mask and defocus as variables, and the inverse imaging framework employs the Adam algorithm to accelerate the optimization. In the optimization process, the penalty term constantly pushes the defocus outward, while the pattern fidelity pushes the defocus term inward, and the optimal source and mask are constantly searched in the confrontation process to realize the control of DOF. Compared to SMO with the Adam method (SMO-Adam), the PW and DOF (EL = 15%) in DGASMO maximally increased 29.12% and 44.09% at 85 nm technology node, and the PW and DOF (EL = 2%) at 55 nm technology node maximally increased 190.2% and 118.42%. Simulation results confirm the superiority of the proposed DGASMO approach in DOF improvement, process robustness, and process window.

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network

Optical proximity correction (OPC) in modern design closures has become extremely expensive and challenging. Conventional model-based OPC encounters performance degradation and large process variation, while aggressive approach, such as inverse lithography technology (ILT), suffers from large computational overhead for both mask optimization and mask writing processes. In this article, we developed Neural-ILT, an end-to-end learning-based OPC framework, which literally conducts mask prediction and ILT correction for a given layout in a single neural network, with the objectives of: 1) mask printability enhancement; 2) mask complexity optimization; and 3) flow acceleration. A domain-specific model pretraining recipe, which introduces the domain knowledge of lithography system, is proposed to help Neural-ILT achieving faster and better convergence. Quantitative results show that compared to the state-of-the-art (SOTA) learning-based OPC solutions and conventional OPC flows, Neural-ILT can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$30\times $ </tex-math></inline-formula> turnaround time (TAT) speedup and the best mask printability with relatively lower mask complexity. Based on the developed infrastructure, we further investigated the feasibility of handling multiple mask optimization tasks for different datasets within a common Neural-ILT platform. We believe this work could bridge well-developed deep learning toolkits to GPU-based high-performance lithographic computations to achieve groundbreaking performance boosting on various computational lithography-related tasks.

Breakthrough curvilinear ILT enabled by multi-beam mask writing

Background: Multi-beam mask writers have been one of the most significant additions to the semiconductor manufacturing equipment arsenal in over a decade. The ability of multi-beam mask writers to write masks with a constant write time regardless of mask shapes or complexity has made them an eagerly anticipated advancement to help write curvilinear mask shapes for both today’s advanced 193i nodes and for extreme ultra-violet (EUV) lithography in the future. Perhaps the most obvious application for these new pixel-based mask writers is the production of curvilinear inverse lithography technology (ILT) masks. ILT has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes and mask writing times associated with this computational technique have limited its practical application. Until recently, it had been used for critical “hotspots” on chips, but had not been used for entire chips. Aim: The introduction of multi-beam mask writing, along with the advent of graphics processing unit (GPU)-accelerated computing for mask and wafer, have enabled the introduction of a new approach to full-chip ILT using these new technologies. The goal was to produce full-chip, curvilinear ILT within the traditional turnaround times of mask shops. Approach: The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement—partitioning and stitching—has failed to produce satisfactory results, either in terms of runtime or in terms of quality. In 2019, D2S introduced an entirely new, stitchless approach, systematically designed for ILT, multi-beam mask writers, and GPU acceleration, that makes full-chip ILT a practical reality in production for the first time. Results: We present this new ILT approach, first introduced using a multi-beam mask writer to create the complex curvilinear mask shapes. We also review findings that targeting curvilinear mask shapes creates masks that are more resilient to manufacturing variation. Finally, we review the results of this new, stitchless full-chip curvilinear ILT as applied to memory chip making. We show mask making and wafer print results, including pattern fidelity and process window, to demonstrate the actual benefit of such technologies—a doubling in the wafer process window—for semiconductor manufacturing.

Sub-resolution assist feature placement with generative adversarial network

Background: As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have since been widely adopted. Aim: The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better PW as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion. Approach: Generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix, and CycleGAN, were first trained and then utilized to synthesize realistic ILT images. Results: These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon source-mask optimizer (SMO). Conclusions: Methodologies of SRAF placement based on GANs were demonstrated in this paper. While traditional MO approach showed the best lithography performance, CycleGAN in particular was close behind and had much better performance than conventional RB-SRAF approach, whilst achieving good stability for different layout environments. Most importantly, the efficiency of SRAF insertion can be enhanced significantly through GANs.

Study on various curvilinear data representations and their impact on mask and wafer manufacturing

Inverse lithography technology (ILT) optical proximity correction is going to play a critical role in addressing challenges of optical and EUV lithography as the industry pushes toward advanced nodes. One major barrier in adoption of ILT has been the mask writer’s inability to efficiently write curvilinear patterns. With the introduction of multibeam mask writers, this barrier has been removed and widespread adoption of ILT is imminent. Traditionally, mask writers have accepted only trapezoidal inputs to the tool, though recent trends show that mask writers are adopting newer formats that already reduce file size. However, as the ILT shape complexity and data volume increases further for 5 nm nodes and beyond, the explosion of mask pattern data file size becomes a major concern. Therefore, there is a need for the industry to look toward other compact formats of data representation that will be capable of serving well for multiple generations of mask making. We compare various curvilinear data representation schemes and their value in the curvilinear ILT-based mask manufacturing flow. We demonstrate that given the nature of curvilinear data, representing it using native curve formats has significant value to reduce file size for future mask making flows. The same format may not be applicable for all types of features in the input mask. These options will be discussed. We will compare the value of such exotic representations with regular simplification approaches that reduce data volume using standard methods and discuss the extents and limits of all these techniques. To evaluate practical use of curvilinear representation in place of conventional piecewise linear representation, we manufacture and measure a photomask to evaluate the accuracy of curvilinear representations. Finally, we use EUV AIMS to assess the impact of curvilinear representation on wafer process window.

Inverse lithography technology: 30 years from concept to practical, full-chip reality

In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

Fast inverse lithography based on dual-channel model-driven deep learning.

Inverse lithography technology (ILT) is extensively used to compensate image distortion in optical lithography systems by pre-warping the photomask at the pixel scale. However, computational complexity is always a central challenge of ILT due to the big throughput of data volume. This paper proposes a dual-channel model-driven deep learning (DMDL) method to overcome the computational burden, while break through the limit of image fidelity over traditional ILT algorithms. The architecture of DMDL network is not inherited from conventional deep learning, but derived from the inverse optimization model under a gradient-based ILT framework. A dual-channel structure is introduced to extend the capacity of the DMDL network, which allows to simultaneously modify the mask contour and insert sub-resolution assist features to further improve the lithography image fidelity. An unsupervised training strategy based on auto-decoder is developed to avoid the time-consuming labelling process. The superiority of DMDL over the state-of-the-art ILT method is verified in both of the computational efficiency and image fidelity obtained on the semiconductor wafer.

Sub-Resolution Assist Feature Cleanup Based on Grayscale Map

As an approach of resolution enhancement technique (RET), sub-resolution assist feature (SRAF) is used to meet the pitch requirements for sparse patterns in off-axis illumination (OAI) and supplements the spatial frequencies of main patterns to improve the resolution. Rules-based SRAF (RB-SRAF) is a technique that foundry extracts SRAF placement rules from wafer data or simulation data and then apply these rules to full chip. RB-SRAF often produces a lot of conflicts. Usually, the geometric constrains are the only factors taken into account in cleaning up of these conflicts, which may lead to mistaken cleanup and be counter-productive. Therefore, it is necessary to introduce some physical factors in the course of cleanup. The transmissivity distribution of mask in hotspot region can be obtained by inverse lithography technology (ILT). And the statistical information of the grayscale map from ILT can be used for leading cleanup and keeping the SRAFs which contribute more to process window (PW). The feasibility of this method has been verified by a series of simulations.

Subresolution assist features impact and implementation in extreme ultraviolet lithography for next-generation beyond 7-nm node

The next-generation beyond 7-nm node potentially requires the implementation of subresolution assist features (SRAF) with extreme ultraviolet (EUV) lithography. This paper aims at providing a clear SRAF strategy for the next-generation beyond 7-nm node designs through a series of experiments. Various factors are considered, including stochastic effects, three-dimensional (3-D) mask effects, through-slit effects, aberrations, and pixelated source mask optimization (SMO) sources. We consider process variability bands with a variety of process conditions, including focus/dose/mask bias changes and also the normalized image log-slope/image log-slope as our objective functions, to determine what the best SRAF solution is for a set of test patterns. Inverse lithography technology is implemented to optimize both the main feature (MF) mask and SRAF placement, in particular, asymmetric SRAF placement to balance the 3-D mask effects. SRAF can potentially mitigate image shift through-focus, i.e., nontelecentricity, caused by EUV 3-D shadowing effect. This shadowing effect is pattern-dependent and contributes to the overlay variation. As we approach the next-generation beyond 7-nm node, this image shift can be more significant relative to the overlay budget, hence, we further investigate the impact of SRAF placement to the image shift. Moreover, the center of focus shift due to the large 3-D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus and is evaluated using both metal and contact layer test cases. We study the source impact to SRAF insertion by experimenting with both a symmetric source (standard source) and an asymmetric source (SMO source). Finally, we understand the importance of using full flare map and full through-slit model (including aberration variation through-slit) in the MF correction. Furthermore, we evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next-generation beyond 7-nm node.

Directed self-assembly graphoepitaxy template generation with immersion lithography

We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Fast Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement and Its Application

Inverse lithography technology (ILT) is one of the promising resolution enhancement techniques (RETs), as the advanced integrated circuits (IC) technology nodes still use the 193 nm light source. Among all the algorithms for ILT, the level-set-based ILT (LSB-ILT) is a feasible choice with good production result in practice. However, existing ILT algorithms optimize masks at nominal process condition without giving sufficient attention to the process variations, and thus the optimized masks show poor performance with focus and dose variations. In this paper, we put forward a new LSB-ILT algorithm for process robustness improvement with fast convergence. In order to account for the process variations in the optimization, we adopt a new form of the cost function by adding the objective function of process variation band (PV band) to the nominal cost. We also adopt the hybrid conjugate gradient (CG) method to reduce the runtime of the algorithm. We perform experiments on ICCAD 2013 benchmarks and the results show that our algorithm outperforms the top two winners of the ICCAD 2013 contest by 6.5%. We also adopt the attenuated phase shift mask (att-PSM) in the experiment with test cases from industry. The results show that our new algorithm has a fast convergence speed and reduces the process manufacturability index (PMI) by 38.77% compared with the LSB-ILT algorithm without the consideration of PV band.

Single spherical mirror optic for extreme ultraviolet lithography enabled by inverse lithography technology.

Traditionally, aberration correction in extreme ultraviolet (EUV) projection optics requires the use of multiple lossy mirrors, which results in prohibitively high source power requirements. We analyze a single spherical mirror projection optical system where aberration correction is built into the mask itself, through Inverse Lithography Technology (ILT). By having fewer mirrors, this would reduce the power requirements for EUV lithography. We model a single spherical mirror system with orders of magnitude more spherical aberration than would ever be tolerated in a traditional multiple mirror system. By using ILT, (implemented by an adjoint-based gradient descent optimization algorithm), we design photomasks that successfully print test patterns, in spite of these enormous aberrations. This mathematical method was tested with a 6 plane wave illumination source. Nonetheless, it would have poor power throughput from a totally incoherent source.

SVM based layout retargeting for fast and regularized inverse lithography

Inverse lithography technology (ILT), also known as pixel-based optical proximity correction (PB-OPC), has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the traditional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine (SVM) based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the ‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manufacturability is another critical issue in ILT; however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT (LSB-ILT) algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8% and 69.0%, respectively.

Regularized level-set-based inverse lithography algorithm for IC mask synthesis

Inverse lithography technology (ILT) is one of the promising resolution enhancement techniques, as the advanced IC technology nodes still use the 193 nm light source. In ILT, optical proximity correction (OPC) is treated as an inverse imaging problem to find the optimal solution using a set of mathematical approaches. Among all the algorithms for ILT, the level-set-based ILT (LSB-ILT) is a feasible choice with good production in practice. However, the manufacturability of the optimized mask is one of the critical issues in ILT; that is, the topology of its result is usually too complicated to manufacture. We put forward a new algorithm with high pattern fidelity called regularized LSB-ILT implemented in partially coherent illumination (PCI), which has the advantage of reducing mask complexity by suppressing the isolated irregular holes and protrusions in the edges generated in the optimization process. A new regularization term named the Laplacian term is also proposed in the regularized LSB-ILT optimization process to further reduce mask complexity in contrast with the total variation (TV) term. Experimental results show that the new algorithm with the Laplacian term can reduce the complexity of mask by over 40% compared with the ordinary LSB-ILT.

Convolution-variation separation method for efficient modeling of optical lithography

We propose a general method called convolution-variation separation (CVS) to enable efficient optical imaging calculations without sacrificing accuracy when simulating images for a wide range of process variations. The CVS method is derived from first principles using a series expansion, which consists of a set of predetermined basis functions weighted by a set of predetermined expansion coefficients. The basis functions are independent of the process variations and thus may be computed and stored in advance, while the expansion coefficients depend only on the process variations. Optical image simulations for defocus and aberration variations with applications in robust inverse lithography technology and lens aberration metrology have demonstrated the main concept of the CVS method.