Breakthrough curvilinear ILT enabled by multi-beam mask writing

Linyong (Leo) Pang,Kechang Wang,Ryan Pearman,Bo Su,Ezequiel Vidal Russell,Jennefir Digaum,Bill Baggenstoss,Michael Lee,Ali Bouaricha,Ming-Chuan Yang,P Jeffrey Ungar,Aki Fujimura

doi:10.1117/1.jmm.20.4.041405

Abstract

Background: Multi-beam mask writers have been one of the most significant additions to the semiconductor manufacturing equipment arsenal in over a decade. The ability of multi-beam mask writers to write masks with a constant write time regardless of mask shapes or complexity has made them an eagerly anticipated advancement to help write curvilinear mask shapes for both today’s advanced 193i nodes and for extreme ultra-violet (EUV) lithography in the future. Perhaps the most obvious application for these new pixel-based mask writers is the production of curvilinear inverse lithography technology (ILT) masks. ILT has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes and mask writing times associated with this computational technique have limited its practical application. Until recently, it had been used for critical “hotspots” on chips, but had not been used for entire chips. Aim: The introduction of multi-beam mask writing, along with the advent of graphics processing unit (GPU)-accelerated computing for mask and wafer, have enabled the introduction of a new approach to full-chip ILT using these new technologies. The goal was to produce full-chip, curvilinear ILT within the traditional turnaround times of mask shops. Approach: The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement—partitioning and stitching—has failed to produce satisfactory results, either in terms of runtime or in terms of quality. In 2019, D2S introduced an entirely new, stitchless approach, systematically designed for ILT, multi-beam mask writers, and GPU acceleration, that makes full-chip ILT a practical reality in production for the first time. Results: We present this new ILT approach, first introduced using a multi-beam mask writer to create the complex curvilinear mask shapes. We also review findings that targeting curvilinear mask shapes creates masks that are more resilient to manufacturing variation. Finally, we review the results of this new, stitchless full-chip curvilinear ILT as applied to memory chip making. We show mask making and wafer print results, including pattern fidelity and process window, to demonstrate the actual benefit of such technologies—a doubling in the wafer process window—for semiconductor manufacturing.

Highlights

1.1 Curvilinear inverse lithography technology (ILT) Started over a Decade Ago Over the last two decades, for semiconductor manufacturers targeting advanced nodes—from 90 nm all the way to 5 nm —the greatest challenge has always been lithography
We review findings that targeting curvilinear mask shapes creates masks that are more resilient to manufacturing variation
The semiconductor industry has recognized the value of ILT in addressing the challenges of advanced-node lithography

Summary

Introduction

1.1 Curvilinear ILT Started over a Decade Ago Over the last two decades, for semiconductor manufacturers targeting advanced nodes—from 90 nm all the way to 5 nm —the greatest challenge has always been lithography. This is because lithography is fundamentally constrained by basic principles of optical physics. It has long been known that the best lithography that is theoretically possible can be achieved by considering the design of photomasks as an inverse problem—and solving the inverse problem to find the optimal photomask for a given process, using a mathematical approach This approach has been explored for many years, starting with the pioneering work of Saleh et al in the 1980s.1–8. It had been used for critical “hotspots” on chips, but had not been used for entire chips

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