Intrinsic Device Performance Research Articles

Hot-carrier thermophotovoltaic systems

A thermophotovoltaic (TPV) energy converter harnesses thermal photons emitted by a hot body and converts them to electricity. When the radiative heat exchange between the emitter and photovoltaic cell is spectrally monochromatic, the TPV system can approach the Carnot thermodynamic efficiency limit. Nonetheless, this occurs at the expense of vanishing extracted electrical power density. Conversely, a spectrally broadband radiative heat exchange between the emitter and the cell yields maximal TPV power density at the expense of low efficiency. By leveraging hot-carriers as a means to mitigate thermalization losses within the cell, we demonstrate that one can alleviate this trade-off between power density and efficiency. Via detailed balance analysis, we show analytically that one can reach near-Carnot conversion efficiencies close to the maximum power point, which is unattainable with conventional TPV systems. We derive analytical relations between intrinsic device parameters and performance metrics, which serve as design rules for hot-carrier-based TPV systems.

Accurate Adjusting the Lattice Strain of Triple-Cation and Mixed-Halide Perovskites for High-Performance Photodetector

The instability of perovskite optoelectronic devices remains a big barrier to their commercialization. The instability caused by external stimuli has been addressed by encapsulation, such as humidity, oxygen, heat, and ultraviolet light. However, the intrinsic instability of perovskite materials due to the lattice strain has not been fully addressed, which affects the physical properties and device performance to a great extent. Tuning the lattice strain by controlling the perovskite composition and ratio is an effective way to further develop efficient and stable devices. Herein, we prepare a series of triple-cation and mixed-halide (FAPbI3)x(MAPbBr3)y(CsPbI3)1-x-y perovskite single-crystal thin films and study the effect of lattice strain on the perovskite optoelectronic properties. Especially, the perovskite photodetector with a horizontal structure based on (FAPbI3)0.79(MAPbBr3)0.13(CsPbI3)0.08 single-crystal thin films exhibits excellent performance with an enhanced responsivity of 40 A/W, high detectivity of 1.9 × 1013 Jones, external quantum efficiency of 9100%, and superior stability. This can be explained by the fact that the optimal coordination between each element leads to the release of lattice strain and further produces low defect density and long carrier lifetime in (FAPbI3)0.79(MAPbBr3)0.13(CsPbI3)0.08 single-crystal thin films. This research shows the significance of ion ratios in tuning lattice strain and determining the intrinsic device performance and makes the perovskite (FAPbI3)0.79(MAPbBr3)0.13(CsPbI3)0.08 a promising candidate for the next generation of optoelectronic devices.

Approaching the intrinsic exciton physics limit in two-dimensional semiconductor diodes.

Two-dimensional (2D) semiconductors have attracted intense interest for their unique photophysical properties, including large exciton binding energies and strong gate tunability, which arise from their reduced dimensionality1-5. Despite considerable efforts, a disconnect persists between the fundamental photophysics in pristine 2D semiconductors and the practical device performances, which are often plagued by many extrinsic factors, including chemical disorder at the semiconductor-contact interface. Here, by using van der Waals contacts with minimal interfacial disorder, we suppress contact-induced Shockley-Read-Hall recombination and realize nearly intrinsic photophysics-dictated device performance in 2D semiconductor diodes. Using an electrostatic field in a split-gate geometry to independently modulate electron and hole doping in tungsten diselenide diodes, we discover an unusual peak in the short-circuit photocurrent at low charge densities. Time-resolved photoluminescence reveals a substantial decrease of the exciton lifetime from around 800 picoseconds in the charge-neutral regime to around 50 picoseconds at high doping densities owing to increased exciton-charge Auger recombination. Taken together, we show that an exciton-diffusion-limited model well explains the charge-density-dependent short-circuit photocurrent, a result further confirmed by scanning photocurrent microscopy. We thus demonstrate the fundamental role of exciton diffusion and two-body exciton-charge Auger recombination in 2D devices and highlight that the intrinsic photophysics of 2D semiconductors can be used to create more efficient optoelectronic devices.

Low-Frequency Noise in Supported and Suspended MoS2 Transistors

Sensitivity of sensors, the phase noise of oscillators, and intrinsic device performance at the nanoscale are primarily limited by fluctuations in resistance at low frequencies, also called flicker noise. These intrinsic fluctuations in resistance become more prominent in two-dimensional materials due to their ultrathin nature. Here, we report the low-frequency noise (LFN) behavior of supported and suspended MoS2 FETs. Carrier-number fluctuation mechanism was found to be responsible for LFN in both configurations. The extracted frequency index ( $\gamma $ in 1/ ${f}^\gamma $ ) indicates the different trap time constants and mechanisms responsible for LFN in MoS2 transistors. A $\gamma $ value of 2 in suspended transistors indicates a tight trap time-constant distribution likely due to recombination–generation through trap states arising only from intrinsic defects and/or extrinsic adsorbates. A wide time-constant distribution ( $\gamma \!\sim \textsf {1}$ to 1.4) in supported transistors indicates the presence of various kinds of traps, such as adsorbates, intrinsic defects, as well as interface and oxide traps. Furthermore, variation in S0 (characterizes the magnitude of noise) with gate voltage in both supported and suspended device configurations was validated analytically using the carrier-number fluctuation model.

Molecular understanding of diphenylether-, 9,9-biphenylfluorene- and tetraphenylsilane-centered wide bandgap host materials for highly efficient blue phosphorescent OLEDs

Organic wide bandgap semiconductor is a hot research topic in optoelectronic fields. In this work, a series of diphenylether-, 9,9-biphenylfluorene- and tetraphenylsilane-centered wide bandgap materials are designed and synthesized. Comprehensive experiments and theoretical calculations are conducted to investigate their intrinsic thermal stability, photophysical property, electrochemical behavior and device performance, aiming at exploring the potentials of oxygen, sp3-hybridized carbon and silicon atoms for wide bandgap materials. They all can interrupt molecular conjugation to generate wide bandgaps. By modification of appropriate donor and acceptor, relatively high triplet energy level (ET) can be obtained in the resulting materials. Quantum chemical calculations indicate the sort of triplet energy levels of N-carbazole > fluorene > benzonitrile, which fully supports the experimental results. Tetraphenylsilane-based materials display lower LUMO levels than corresponding diphenylether- and 9,9-biphenylfluorene-centered materials owing to the dπ-pπ conjugation. Among them, DCzSiPy/FIrpic doped device gives the best device performance with maximum current efficiency of 35.6 cd/A and maximum external quantum efficiency of 16.8%, demonstrating the superiority of tetraphenylsilane skeleton. 9,9-Biphenylfluorene-based doped devices have comparable efficiencies with tetraphenylsilane-hosted ones, meaning 9,9-biphenylfluorene unit also can be a good constructing skeleton for wide bandgap host materials.

Wafer Level Variability Improvement by Spatial Source/Drain Activation and Ion Implantation Super Scan for FinFET Technology

In this paper, CMOS wafer level ring oscillator frequency variability improvement >40% is demonstrated by either spatial source/drain activation or ion implantation super scan in FinFET technology. Yield improvement (up to 17%) is verified with better within wafer uniformity and with no intrinsic device performance degradation. Furthermore, the combination of super scan and spatial source/drain activation is suggested for optimized variability improvement benefits from individual device type uniformity tuning (super scan) and all device type uniformity tuning (from spatial S/D activation).

Improving Performances of In-Plane Transition-Metal Dichalcogenide Schottky Barrier Field-Effect Transistors.

Monolayer Schottky barrier (SB) field-effect transistors based on the in-plane heterojunction of 1T/1T'-phase (metallic) and 2H-phase (semiconducting) transition-metal dichalcogenides (TMDs) have been proposed following the recent experimental synthesis of such devices. By using density functional theory and ab initio simulations, intrinsic device performance, sub-10 nm scaling, and performance boosting of MoSe2, MoTe2, WSe2, and WTe2, SB field-effect transistors are systematically investigated. We find that the Schottky barrier heights (SBHs) of these in-plane 1T(1T')/2H contacts are proportional to their band gaps: the bigger band gap corresponds to bigger SBH. For four TMDs, the SBH of 1T/2H contact is always smaller than that of 1T'/2H contact. The WTe2 SB field-effect transistor can provide the best performance and satisfy the requirement of the high-performance transistor outlined by the International Technology Roadmap for Semiconductors down to a 6 nm gate length. In addition, the replacement of suitable 1T-TMD on the source/drain regions can modulate conduction band SB, leading to the 8.8 nm WSe2 SB field-effect transistor also satisfying the requirement. Moreover, the introduction of the underlap can increase the effective channel length and reduce the coupling between the source/drain and the channel, leading to the 5.1 nm WTe2 SB field-effect transistor also satisfying the International Technology Roadmap for Semiconductors high-performance requirement. The underlying physical mechanisms are discussed, and it is concluded that the in-plane SB engineering is the key point to optimize such two-dimensional devices.

Impact of Embedment of Cu/TaOx/Ru on Its Device Performance

In our previous work, electric performance of Cu/TaOx/Ru has been found to be inferior to that of Cu/TaOx/Pt device. The poor switching properties of the Ru device have been attributed to the degraded inertness properties of the Ru electrode as a stopping barrier for Cu as compared to the Pt electrode. To study this degradation effect further, we have manufactured two nominally identical Cu/TaOx/Ru devices however differently embedded on the Si wafer. While device A is characterized by the layer sequence SiO2-730nm/Ti-20nm/Ru-50nm/TaOx-25nm/Cu-150nm device B has an additional TaOx-30nm layer inserted between SiO2 and Ti layers. We find the electric behavior of the two devices markedly different. Thus the embedment of the device has a major impact on the intrinsic device performance. We explain the difference to be due to high local temperatures >600oC in the device during the switching that cause species interlayer diffusion and trigger undesired chemical reactions.

Impact of Embedment of Cu/TaOx/Ru on Its Device Performance

In our previous work (ECS Trans.75 (32), 13-23, 2017), we have compared the electric performance of Cu/TaOx/Ru and Cu/TaOx/Pt devices finding that the performance of the Ru device is far inferior to that of the Pt device. The poor resistive switching (RS) properties of the Ru device were imputed to the greatly degraded inertness properties of the Ru electrode as a stopping barrier for Cu drift-diffusion. The degraded inertness of the Ru electrode, in turn, has been attributed to larger Cu surface and/or Cu bulk diffusion in Ru than in Pt. The result is surprising as both Pt and Ru are known to be excellent diffusion barriers for Cu in CMOS backend applications. Here, we have manufactured two nominally identical Cu/TaOx/Ru devices, though, differently embedded on the Si wafer. While Ru device A has been manufactured on oxidized Si wafers with 730 nm SiO2 followed by 20 nm of Ti, 55 nm of Ru, 25 nm of TaOx, and 150 nm of Cu, Ru device B has been manufactured in the same way except that a 30 nm TaOx layer has been inserted between SiO2 and Ti layers. Electrical analysis shows that the RS behavior of the two devices is markedly different. Thus the way, nominally identical RS devices are embedded into a technology module has a major impact on the intrinsic device performance. We have identified three major reasons for this disparity. First, the layers of Ti and Ru involved are very thin (20nm and 55 nm). Second, during resistive switching local temperatures at the filament during the form/set and reset operations can exceed 600oC i.e. far higher than the maximum temperature which CMOS backend may experience when the underlying processor is in operation. This temperature is estimated to be ~120oC. Indeed, up to 120oC and above, amorphous Ru remains an excellent diffusion barrier for Cu. The third reason is the crystallinity phase of Ru thin layers that depends on the deposition method and the subsequent ‘unintended’, i.e. related to the RS, local anneals. We find that Ru device A can be switched a limited number of times at high compliance currents Icc (~0.5mA) while the device B at such Icc levels shows either volatile filament formation or when a filament forms, it is permanent. Conversely, at Icc of ~5uA Ru device B shows fairly good RS behavior, while Ru device A shows mostly volatile behavior. Besides Icc, the other critical parameter is the ramp rate rr during the voltage sweep. Both parameters determine effectively the thermal budget during the set and reset operations and are thus responsible for: 1) chemical reactions taking place between the thin metal and dielectric layers and formation of chemical compounds. 2) Cu surface diffusion on the Ru electrode and Cu penetration through the Ru electrode which appears to include compound formation of Ru2Si3 and Cu3Si in case of Ru device A. Therefore, the declared purpose of inserting the TaOx layer between SiO2 and Ti was to prevent those silicidation reactions. In this work, we show that reports in the literature on a number of Ru metallization issues such as: a) thin Ru amorphous films crystallize into a polycrystalline phase at ~550oC; b) observation of a strong diffusive penetration of Cu through the increased number of grain boundaries within Ru layer at 475oC; c) Ru transforms into a less dense Ru2Si3 at ~500oC; d) Ru2Si3 triggers Cu3Si formation at low temperature (~200oC) and degrades the barrier functionality of Ru electrode, are indeed correlated with the differences between the device I-V characteristics of the two Ru devices. Because of the chemical reactions triggered by high local temperatures during cell switching, the Ru devices show new properties over the stable Pt devices. In contrast to Pt devices, the voltage ramp rate has a major impact on the resistance of the on-state, Ron, in the Ru devices: lower ramp rate leads to a higher Ron values because the forming filament is exposed for a longer time to elevated temperatures and suffers from Cu out-diffusion. The observation that Ron in Ru device A is significantly higher than in the Ru device B at the same Icc and rr values, demonstrates that Ru electrode in Ru device B has better inertness properties than in the Ru device A. In summary, this work shows that nominally same device with excellent characteristics in a specific experimental environment, may show vastly degraded characteristics when embedded into a module such as CMOS metallization backend – an issue that has largely been disregarded so far.

Can a Black Phosphorus Schottky Barrier Transistor Be Good Enough?

Experimental two-dimensional (2D) black phosphorus (BP) transistors typically appear in the form of Schottky barrier field effect transistors (SBFETs), but their performance limit remains open. We investigate the performance limit of monolayer BP SBFETs in the sub-10 nm scale by using ab initio quantum transport simulations. The devices with 2D graphene electrodes are apparently superior to those with bulk Ti electrodes due to their smaller and tunable Schottky barrier heights and the absence of metal induced gap states in the channels. With graphene electrodes, the performance limit of the sub-10 nm monolayer BP SBFETs outperforms the monolayer MoS2, carbon nanotube, and advanced silicon transistors and even can meet the requirements of both high performance and low power logic applications of the next decade in the latest International Technology Roadmap for Semiconductors. It appears that the ML BP SBFETs have the best intrinsic device performance among the reported sub-10 nm 2D material SBFETs.

Integration and fabrication of high-performance Sb-based heterostructure backward diodes with submicron-scale airbridges for terahertz detection

In this work, the authors report integration and fabrication of high-performance Sb-based heterostructure backward diodes (HBDs) with planar folded dipole antennas (FDAs) using submicron-scale airbridges for terahertz (THz) detection. By integrating HBDs into FDAs, high detector responsivity of 20 000 V/W at 200 GHz and 9500 V/W at 585 GHz could be potentially achieved due to the optimized impedance matching between the antenna and HBD detector. In order to minimize interconnect parasitics, the HBD integration is accomplished using submicron-scale airbridges. Electromagnetic simulations coupled to device models show that by introducing submicron-scale airbridges and optimizing the device layout, parasitic capacitance and spreading resistance can be significantly reduced. This allows performance nearly equal to the intrinsic device performance to be obtained. To achieve this level of performance, a novel fabrication and integration process has been developed. The process includes mix-and-match electron beam and optical lithography to span the size scales required for both the FDA and small-area HBDs, and offers high accuracy and reproducibility while requiring fewer critical fabrication steps compared to conventional hybrid integration techniques. Devices fabricated using this process have obtained a record-high device curvature coefficient of −58 V−1, indicating the quality of the devices that can be achieved. The process is scalable—in terms of device size, frequency range, and array size—enabling the development of THz focal plane arrays in a wide frequency range (100 GHz to beyond 1 THz).

Pulse I–V characterization of a nano-crystalline oxide device with sub-gap density of states

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I–V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I–V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I–V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.

Comparative advantages of mechanical biosensors.

Mechanical interactions are fundamental to biology. Mechanical forces of chemical origin determine motility and adhesion on the cellular scale, and govern transport and affinity on the molecular scale. Biological sensing in the mechanical domain provides unique opportunities to measure forces, displacements and mass changes from cellular and subcellular processes. Nanomechanical systems are particularly well matched in size with molecular interactions, and provide a basis for biological probes with single-molecule sensitivity. Here we review micro- and nanoscale biosensors, with a particular focus on fast mechanical biosensing in fluid by mass- and force-based methods, and the challenges presented by non-specific interactions. We explain the general issues that will be critical to the success of any type of next-generation mechanical biosensor, such as the need to improve intrinsic device performance, fabrication reproducibility and system integration. We also discuss the need for a greater understanding of analyte-sensor interactions on the nanoscale and of stochastic processes in the sensing environment.

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its improved electrostatics and short-channel effect control. FinFETs represent one of the architectures of interest within that family together with Ω-gates, Π-gates, gate-all-around… They can readily be manufactured starting from SOI or bulk substrates even though more efforts have been dedicated to the SOI option so far. We report in this work an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations. Both alternatives show better scalability (threshold voltage – V t vs. L) than PLANAR CMOS and exhibit similar intrinsic device performance ( I off vs. I on). Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced threshold voltage mismatch. Using an optimized integration to minimize parasitic capacitances and resistances we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both SOI and bulk FinFETs. SRAM cells are also reported to work, scaling similarly with the supply voltage (VDD) for the two FinFET integration schemes.

Single halo SDODEL n-MOSFET: an alternative low-cost pseudo-SOI with better analog performance

In this paper, with the help of extensive TCAD simulations, we investigate the analog performance of source/drain on depletion layer (SDODEL) MOSFETs with a single-halo (SH) implant near the source side of the channel. We use the SH implant in such a structure for the first time. The analog performance parameters in SH SDODEL MOSFETs are compared to those in SH MOSFETs as well as in SH SOI MOSFETs. In addition to reduced junction capacitance for the SH SDODEL structure as compared to that in bulk SH devices, it has been shown that such devices lead to improved performance and lower power dissipation for sub-100 nm CMOS technologies. Our results show that, in SH SDODEL MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/ID, etc) for the sub-100 nm technologies.

1-$\mu\hbox{m}$ Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm

In this letter, 1-mum GaAs-based enhancement-mode n-channel devices with channel mobility of 5500 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> exceeding 250 mS/mm have been fabricated. The measured device parameters including threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> , maximum extrinsic transconductance g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> , saturation current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dss </sub> , on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> , and gate current are 0.11 V, 254 mS/mm, 380 mA/mm, 4.5 Omegamiddotmm, and < 56 pA for a first wafer and 0.08 V, 229 mS/mm, 443 mA/mm, 4.5 Omegamiddotmm, and < 90 pA for a second wafer, respectively. With an intrinsic transconductance g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mi</sub> of 434 mS/mm, GaAs enhancement-mode MOSFETs have reached expected intrinsic device performance

Performance comparison of channel engineered deep sub-micrometer pseudo SOI n-MOSFETs

In this paper, with the help of extensive TCAD simulations, a novel channel and source/drain (S/D) impurity profile engineering has been proposed for pseudo SOI MOSFET structures in order to reduce their junction capacitances. It has been shown that this approach leads to improved performance and lower power dissipation for sub 100 nm CMOS technologies. These pseudo SOI structures studied in this work are referred to as the Source Drain On Depletion Layer (SDODEL) MOSFETs in the earlier studies. We have investigated DC characteristics and analog performance parameters in Single Halo SDODEL MOSFET, Double Halo SDODEL MOSFET and compared their performance with Double Halo MOSFETs (which will henceforth be referred to as Control MOSFETs) with extensive process and device simulations. Our results shows that, in Single Halo SDODEL MOSFET there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g m/ I D etc.) for the sub 100 nm technologies.

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/I/sub D/ etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs.

Analysis of carrier transport phenomena in high band gap II–VI-based MIS photovoltaic devices

High efficiency devices with band gaps in the 1.6–2.0 eV range are needed to develop high efficiency compound semiconductor tandem devices. CdSe with a band gap of 1.7 eV and Cd x Zn 1− x Te with a band gap that is tunable over this range show promise. Some success has been achieved with CdSe metal–insulator–semiconductor device structures. Using AMPS simulations we demonstrate that tunneling is not needed to achieve effective transport of light generated carriers across the intrinsic layer and good device performance. Fabrication of Cu/ZnSe/CdSe/transparent conductor devices has been guided by the simulation results, and measured performance data for these devices are found to be consistent with predictions. Guided by these insights short circuit current densities of 14.7 mA/cm 2 have been achieved without correction for Cu absorption. Open circuit voltages in excess of 400 mV have been achieved for Cu contacts; higher open circuit voltages are attained using Au, but losses in short circuit current occur. The key to further improvements in performance is development of p contacts with larger work function.