Intrinsic Capacitance Research Articles

(Invited) Compact Model for Short-Channel Organic Thin-Film Transistors with Extension for Non-Quasistatic Circuit Simulation and Variability Analysis

We present a compact model for organic thin-film transistors (TFTs) that covers both below-threshold and above-threshold operation with a single charge-based current expression [1]. The effect of hopping transport is included by a power-law mobility model. Contact resistances for staggered and coplanar device structures (Fig. 1) are considered, which can be nonlinear in the case of work-function mismatch between contacts and organic semiconductor [2]. Short-channel effects in submicron transistors, such as threshold-voltage roll-off and drain-induced barrier lowering (DIBL), are included [3].From the expression for the accumulated channel charge, a closed-form model for the drain-current variability due to carrier-number and correlated mobility fluctuations has been derived, relating these statistical variations to the trap density in the channel [4].Furthermore, by applying a partitioning scheme, charges are explicitly attributed to the source and drain contacts, allowing the derivation of a charge-based capacitance model valid for quasi-static operation [5]. Charges in the gate-to-contact overlap regions have been included.Utilizing this device model in a transmission-line approach, a circuit simulation including non-quasistatic effects is possible [6]. In the circuit-simulation netlist, the TFT is replaced by a macro model consisting of a finite number of n single transistors, whereby each single transistor represents a section of the intrinsic channel capacitance and a segment of the intrinsic channel resistance. This model is able to capture the charging and discharging of the channel capacitance of each segment through the channel resistance of the adjacent transistors. In this way, the frequency dependence of the node-to-node capacitances of the full device is obtained.The compact model has been implemented in the hardware description language Verilog-A and verified using results of measurements performed on organic p-channel TFTs fabricated on flexible polyethylene naphthalate (PEN) substrates by stencil lithography (Figs. 2, 3). The TFTs consist of 25-nm-thick aluminum gate electrodes, a 5.3-nm-thick hybrid AlOx/SAM gate dielectric, 30-nm-thick gold (Au) source and drain contacts coated with a pentafluorobenzenethiol (PFBT) monolayer, and a 25-nm-thick vacuum-deposited layer of the small-molecule organic semiconductor DPh-DNTT [7,8]. The transmission-line approach has been verified with good accuracy by comparison with frequency-dependent admittance measurements and numerical simulations of the transient switching behavior of organic TFTs. For a transient analysis, the optimum number of segments required to achieve good agreement between the results from the model and those from TCAD simulations is approximately n=6.In conclusion, the model presented here is fully capable of providing accurate results in dc, small-signal ac, and transient circuit simulations, including short-channel effects. Furthermore, the same set of equations allows an estimation of the drain-current variability due to charge trapping. Acknowledgements: This project was funded by the German Federal Ministry of Education and Research ("SOMOFLEX", No. 13FH015IX6), German Research Foundation (DFG) under Grant KL 1042/9-2 (SPP FFlexCom), and EU H2020 RISE ("DOMINO", No. 645760). We acknowledge AdMOS GmbH, Germany for support.

An Accurate Neural Network-Based Consistent Gate Charge Model for GaN HEMTs by Refining Intrinsic Capacitances

Neural network-based capacitance models are accurate, but some of them are not charge-conservative. In this work, a novel consistent gate charge model for GaN high electron mobility transistors is presented based on neural networks. The equivalent circuit parameters are extracted using the multiobjective gray wolf optimizer-based hybrid method, which improves the accuracy of parameter extraction. To obtain more reliable data sets for accurate neural network-based modeling, the outliers in the extracted intrinsic capacitances are automatically detected and removed using the isolation forest technique. The gate charge is obtained by integrating the capacitances with the voltages at different temperatures. A neural network is used to model the bias- and temperature-dependent gate charges, and the intrinsic capacitance formulation is obtained by taking the partial derivative of the gate charge function with respect to the voltages. The proposed model is charge-conservative and requires no transcapacitances. The large-signal model is implemented in the Advanced Design System and verified by small- and large-signal measurements. Good agreement is obtained between the measurements and simulations.

Computational screening toward quantum capacitance of transition-metals and vacancy doped/co-doped graphene as electrode of supercapacitors

It is of importance to explore electrode materials with high specific capacitance, improving energy density of supercapacitors. Generally, the composition and structure of electrode materials determines its function. Despite many advantages of graphene, low intrinsic capacitance limits its application in the electrode of supercapacitors. Herein, quantum capacitance of 56 kinds of 3d, 4d and 5d transition-metal and vacancy doped/co-doped graphene, named as TM@G and TM@VG, are screened by density functional theory. We concluded that quantum capacitance (Cq) and density of surface charge (Qsc) of graphene-based electrodes can be effectively enhanced with transition-metal and vacancy co-doping, which can be related to shift and/or enhancement of DOS near the Fermi level. Calculated stability (ΔEb) and Qsc imply that Y@G, Ta@VG, Au@VG and Ni@VG are suitable for anode in aqueous systems, while Sc@VG, Y@VG, Fe@VG and Zn@VG for cathode. Cu@VG and Re@VG are more potential for symmetric supercapacitors. Besides, the capacitive performance of graphene can also be enhanced by transition-metal and vacancy co-doping in ionic/organic systems. Noteworthily, in aqueous/ionic/organic systems, Sc@VG and Y@VG are good cathode materials, when Y@G, Ta@VG and Au@VG are superior candidates for anode materials. Therefore, the selection of electrode materials will hold an instructional significance in the development of suporcapacitors.

Plant’s electrophysiological information manifests the composition and nutrient transport characteristics of membrane proteins

ABSTRACT Almost all life activities of plants are accompanied by electrophysiological information. Plant’s electrical parameters are considered to be the fastest response to environment. In this study, the theoretically intrinsic relationships between the clamping force and leaf resistance (R) and inductive reactance (XL) were revealed as 3-parameter exponential decay based on bioenergetics for the first time. The intrinsic resistance (IR), capacitive reactance (IXc), inductive reactance (IXL), impedance (IZ), and capacitance (IC) in plant leaves were successfully monitored. The nutrient flux per unit area (UNF), nutrient transfer rate (NTR) and nutrient transport capacity (NTC) in plants based on IR, IXc, IXL, IZ and IC were defined to reflect nutrient transport characteristics. The results indicate that IXc and IXL could be used to manifest the relative composition characteristics of cell membrane proteins, and are inversely proportional to the amount of surface and binding proteins that induce membrane Xc and XL in plant leaves, respectively. UNF, NTR or NTC exhibited good correlations with crude protein or crude ash, and accurately revealed the nutrient transport strategies of tested plants and their diversity. This study highlights that plant’s electrophysiological information could effectively manifest the composition and nutrient transport characteristics of membrane proteins in plant cells.

Apparent capacitance reduction at high frequencies by self-heating in organic thin-film devices and correction methods

The effects of self-heating in electrical devices on measurement capacitance have not been considered seriously. In a previous study, we showed that self-heating is a source of negative capacitance (NC), observed widely in devices in low frequency ranges. The NC is caused by the nonlinear coupling of the real and imaginary parts of admittance through temperature modulation, owing to self-heating in devices. Because capacitance reduction leading to NC in low frequency ranges can start even at high frequencies (∼100 kHz), the capacitance will likely be underestimated when self-heating is not considered. Thus, here, the self-heating model is extended to explain the capacitance reduction in high frequency ranges; the key to enhancing the reduction is adiabatically heated layers with an extremely small volume. Moreover, a concise method of correcting the reduction is developed. The combination of the self-heating model and the equivalent circuit of a tested device provides a method to eliminate the nonlinear effects and obtain the intrinsic capacitance of the device. The applicability of the model and correction method is examined by fitting impedance spectra for double-layered organic light emitting diodes. The corrected capacitance obtained by the fit clarifies the charge accumulation in each layer under high bias. The model and method are general and applicable to various electronic devices. Our findings prompt the reconsideration of conventional capacitance vs voltage or frequency analyses for electronic devices with ubiquitous self-heating.

Investigation of frequency-up conversion effect on the performance improvement of stack-based piezoelectric generators

This paper originally investigates the influence of frequency-up conversion effect on piezoelectric stack generators for high-performance energy harvesting. A compressive-mode piezoelectric generator is proposed comprised of a piezostack and a spring-mass system for electromechanical transduction and mechanical excitation, respectively. The frequency-up conversion effect is induced by amplitude truncations of the mass under external excitation. A control group, i.e. without truncation, is set for performance comparisons. Experimental results indicate that, with the frequency-up conversion, instantaneous power and average power are enhanced by over 1000 and 177 times, respectively. Each voltage response cycle consists of two stages: high-frequency high-amplitude oscillation and the rest of low-frequency low-amplitude harmonic vibration. The frequency of the former stage determines impedance matching. Due to the frequency converted up by 69 times, and intrinsic high capacitance of the stack, the matched resistance is significantly reduced from over 5 kΩ to 73.10 Ω, resulting much higher power response than that without conversion. Additionally, increase of spring stiffness causes the decrease of voltage responses and less effectiveness of frequency conversion effect. In this work we conclusively report that an instantaneous peak power output of 0.32 W can be generated from a millimeter-size piezoelectric generator, which can foster development of high-viability self-powered applications.

Compact Modeling and Analysis of Charge and Device Capacitance for SELBOX Junctionless Transistor

A charge based compact drain current and capacitance modeling has been developed to describe the transfer and Capacitance-Voltage characteristics of the proposed device. The inversion charge density of the proposed model is defined on the basis of the surface potential model equation at the source and the drain end. These inversion charges are evaluated by the Ward Dutton partition method using the current continuity principle and charge balance equations. Using these inversion charges, a drain current model is discussed for the proposed device, which is based on implicit unified charge control expression. This model defined all the possible intrinsic capacitances analytically derived by the terminal charges associated with the terminal voltages. This compact model is valid in the weak, moderate and strong regime of the device operation. The transfer characteristics of the drain current and C-V characteristic of capacitances have been validated using 2-D numerical simulation.

Analog/RF and Power Performance Analysis of an Underlap DG AlGaN/GaN Based High-K Dielectric MOS-HEMT

This paper exemplifies an exhaustive, figurative and subjective study on the RF performance and DC characteristics analysis of an Underlapped Double-Gate (U-DG) AlGaN/GaN heterojunction-based MOS-HEMT device with Hafnium-based high-k dielectric gate material. This paper depicts the effect of gate length variations on the drain current (ID), the transconductance (gm), the transconductance generation factor (gm/ID) and the RF FOMs intrinsic capacitances (CGD, CGS and CGG), intrinsic resistances (RGD and RGS), cut-off frequency (fT) and maximum oscillation frequency (fMAX). This study reveals shortening of channel length leading to better gate controllability hence an overall superior analog and RF performance is achieved. The U-DG AlGaN/GaN based MOS-HEMT device of 100 nm channel length shows a better Power Output Efficiency (POE) of 33% in contrast to 31% and 23% for the 200 nm and 300 nm devices respectively.

Analysis and Modeling of the Temperature-Dependent Nonlinearity of Intrinsic Capacitances in AlGaN/GaN HEMTs

Modeling the temperature-dependent nonlinearity of intrinsic capacitances in AlGaN/GaN high electron mobility transistors (HEMTs) improves model accuracy. In this letter, extraction results indicate that the current modeling methods cannot accurately reflect the variations of nonlinearity in intrinsic capacitances with temperature. This letter analyzes the causes of unmodeled phenomena and characterizes them based on device physics. Verifications show that the improved intrinsic capacitance model in this letter effectively enhances the accuracy of the HEMT model at non-nominal temperatures.

Gate capacitance model of AlGaN/GaN high electron mobility transistor

<sec>The research on capacitance model of AlGaN/GaN high electron mobility transistor (HEMT) is of great significance in modern communication technology and circuit simulation. At present, many modeling methods of AlGaN/GaN HEMT capacitance models have been proposed. The gate capacitance is composed of intrinsic capacitance and fringe capacitance. However, most researches focus on the intrinsic capacitance but ignore the fringe capacitance, which leads to a large error in the final results. A total gate capacitance model including fringe capacitance needs to be established.</sec><sec>In this paper, the conformal mapping method and transition functions are used to establish the inner fringe capacitance model, and the intrinsic capacitance model is derived based on the Ward-Dutton charge distribution principle. The intrinsic capacitance model and the outer fringe capacitance model are combined to obtain the source/drain total gate capacitance model. Based on this model, the relationship between the bias condition and the fringe capacitance is analyzed. We compare the difference between the effects of external bias on gate capacitance with and without the fringe capacitance considered, and the error rate of the gate capacitance in the on state is calculated without considering the fringe capacitance.</sec><sec>The results show that the fringe capacitance is mainly affected by the gate bias. When the fringe capacitance is taken into account in the intrinsic capacitance model, the total capacitance model is larger than that without considering the fringe capacitance. For the gate capacitance, if the influence of fringing capacitance is not considered, the gate capacitance error rate of the device in the OFF state can reach 80%; for fringing capacitance, the error rate is over 65% when the device is working in the saturation region.</sec>

Monte Carlo simulations of the switching processes in the superconducting quantron-based neuron

We study the response function of a superconducting single-contact interferometer (quantron or rf-SQUID), which is the building block for adiabatic neuron with a nonlinear transfer characteristic. It is shown that the intrinsic shunt capacitance of the junction leads to distortions in the response function. At the same time the contact resistance leads to the suppression of these vibrations. The response function of the rf-SQUID at finite temperature is calculated by Monte Carlo method.

10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors

Computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of the multiply-and-accumulate (MAC) operation under a memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an approach focusing on scalable CIM designs using a new ten-transistor (10T) static random access memory (SRAM) bit-cell. Using the proposed 10T SRAM bit-cell, we present two SRAM-based CIM (SRAM-CIM) macros supporting multibit and binary MAC operations. The first design achieves fully parallel computing and high throughput using 32 parallel binary MAC operations. Advanced circuit techniques such as an input-dependent dynamic reference generator and an input-boosted sense amplifier are presented. Fabricated in 28 nm CMOS process, this design achieves 409.6 GOPS throughput, 1001.7 TOPS/W energy efficiency, and a 169.9 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> throughput area efficiency. The proposed approach effectively solves previous problems such as writing disturb, throughput, and the power consumption of an analog to digital converter (ADC). The second design supports multibit MAC operation (4-b weight, 4-b input, and 8-b output) to increase the inference accuracy. We propose an architecture that divides 4-b weight and 4-b input multiplication to four 2-b multiplication in parallel, which increases the signal margin by 16× compared to conventional 4-b multiplication. Besides, the capacitive digital-to-analog converter (CDAC) area issue is effectively addressed using the intrinsic bit-line capacitance existing in the SRAM-CIM architecture. The proposed approach of realizing four 2-b parallel multiplication using the CDAC is successfully demonstrated with a modified LeNet-5 neural network. These results demonstrate that the proposed 10T bit-cell is promising for realizing robust and scalable SRAM-CIM designs, which is essential for realizing fully parallel edge computing.

Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design

Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies ( f T, f max), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/μm. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/μm. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.

ANALYSIS OF EMITTER COUPLED MULTIVIBRATORS

The purpose of this investigation is to develop a systematic nonlinear analysis of the circuit in Figure 1, as yet not available in the literature, obtaining an exact formula for the oscillation frequency. Then, we find the condition for the circuit to behave as a relaxation oscillator, or as a nearly sinusoidal oscillator, analyzing the circuit behavior around the equilibrium point through a circuit model accounting for the transistor intrinsic capacitances. A nonlinear analysis of the popular emitter-coupled multivibrator is performed, which is based on the classical discontinuity theory. Exact relationships for calculating its waveform are obtained. Then, we investigate the circuit dynamic behavior showing that at very high frequencies the circuit exhibits a completely different behavior, similar to an LC second-order nearly sinusoidal oscillator. Conditions allowing us to predict one or the other behavior are found.

Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors

Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level performances to CMOS at comparable nodes. Analytical models of the parasitic capacitances of a TIGFET transistor were derived using techniques such as the equivalent Schwarz-Christoffel transformation and standard cylindrical capacitors and show close agreement with numerical simulations. The maximum capacitance of a TIGFET transistor is $2\times $ larger than for a 15 nm CMOS High Performance (HP) device due to the TIGFET’s two additional gated contacts, but this is countered by its ability for multiple modes of operation which reduces the effective switching capacitance per device. A TIGFET transistor sees, on average, only a 30% increase in total capacitance compared to a CMOS HP device. Additionally, the TIGFET’s increased device functionality can be used to modify the circuit-level architecture of a TIGFET-based design to mitigate the performance impact of its larger device-level capacitance. This combination of a TIGFET’s (1) multiple modes of operation, and (2) circuit-level architecture lead to enhanced system performance. In particular, we show that at the 15 nm technology node TIGFET technology has 18% lower energy-delay product for a fan-out of 4 and higher when using 1-bit full-adder logic circuit than for the equivalent node CMOS HP.

Multi-scale analysis of radio-frequency performance of 2D-material based field-effect transistors.

Two-dimensional materials (2DMs) are a promising alternative to complement and upgrade high-frequency electronics. However, in order to boost their adoption, the availability of numerical tools and physically-based models able to support the experimental activities and to provide them with useful guidelines becomes essential. In this context, we propose a theoretical approach that combines numerical simulations and small-signal modeling to analyze 2DM-based FETs for radio-frequency applications. This multi-scale scheme takes into account non-idealities, such as interface traps, carrier velocity saturation, or short channel effects, by means of self-consistent physics-based numerical calculations that later feed the circuit level via a small-signal model based on the dynamic intrinsic capacitances of the device. At the circuit stage, the possibilities range from the evaluation of the performance of a single device to the design of complex circuits combining multiple transistors. In this work, we validate our scheme against experimental results and exemplify its use and capability assessing the impact of the channel scaling on the performance of MoS2-based FETs targeting RF applications.

RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric

The incorporation of dual-metal, double-gate, germanium pocket and hetero gate dielectric tunnel field effect transistor (DMG-DG-Ge pocket TFET) allows the conceptualization and realization of suppressed ambipolarity. These deployed technology boosters for the TFET tailor the electric field as per the need at source-channel and drain-channel interfaces. The novelty of this work lies in its dual-metal and hetero dielectric structure that are introduced in Ge- pocket TFET structure. The major goal achieved here is enhanced ION/IOFF ratio. Further using the exhaustive and calibrated TCAD analysis, this work examines the analog/RF and linearity distortion performance of DMG-DG-Ge pocket TFET. Here, intrinsic device capacitances, transconductance, cutoff frequency, transgeneration factor (TGF), higher order derivatives of drain current (gm2 and gm3), VIP2, VIP3, IIP3 and IMD3 are being extracted. Effect of different device parameters: channel length, body thickness, oxide thickness and pocket width on the dc, analog/RF and linearity distortion parameters has also been studied. The present analysis reveals an in-depth guideline for the design of DMG-DG-Ge pocket TFET with optimized analog/RF performance with least linearity distortions.

Continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation of the terminal charges, verified against TCAD simulation data. The AC symmetry tests of the trans-capacitance compact model are thoroughly investigated.

Merged-Element Transmon

Transmon qubits are ubiquitous in the pursuit of quantum computing using superconducting circuits. However, they have some drawbacks that still need to be addressed. Most importantly, the scalability of transmons is limited by the large device footprint needed to reduce the participation of the lossy capacitive parts of the circuit. In this work, we investigate and evaluate losses in an alternative device geometry, namely, the merged-element transmon (mergemon). To this end, we replace the large external shunt capacitor of a traditional transmon with the intrinsic capacitance of a Josephson junction (JJ) and achieve an approximately 100 times reduction in qubit dimensions. We report the implementation of the mergemon using a sputtered Nb--amorphous-Si--Nb trilayer film. In an experiment below 10 mK, the frequency of the readout resonator, capacitively coupled to the mergemon, exhibits a qubit-state dependent shift in the low power regime. The device also demonstrates the single- and multi-photon transitions that represent a weakly anharmonic system in the two-tone spectroscopy. The transition spectra are explained well with master-equation simulations. A participation ratio analysis identifies the dielectric loss of the a-Si tunnel barrier and its interfaces as the dominant source for qubit relaxation. We expect the mergemon to achieve high coherence in relatively small device dimensions when implemented using a low-loss, epitaxially-grown, and lattice-matched trilayer.

On the Mechanisms of Linearity Peak Modeling in Common-Emitter SiGe HBTs Using Mextram 505

An important aspect of compact modeling for RF application is to accurately model the biasing current at which transistor linearity is maximized, i.e. where the third order intercept point, IP3, peaks. We have shown recently that for common-emitter SiGe HBTs, Mextram 504.12 has problem modeling the IP3 peak behavior at high injection [1]. We have further developed a couple of new modeling options in Mextram 505 [2] for CB junction depletion capacitance intended to improve IP3 peak modeling [1]. However, the detailed mechanisms of how these improved CB junction depletion capacitance models translate into IP3 peak modeling improvement remains unclear and require further investigation.For instance, the collector current, which is the output current, consists of the transistor main current In that flows from the collector to the emitter, and the CB junction capacitance discharging current that flows from the collector to the base. With the change of CB junction depletion capacitance model, which distortion current is dominant, In or the CB discharging current, in determining IP3 peak? Through detailed analysis of the harmonic components of the individual branch currents at the collector node of the Mextram large signal equivalent circuit, we find that the In distortion current dominates in determining IP3 peak behavior.The next logic question is if the In distortion current improvement with the Mextram 505 CB depletion capacitance models is directly due to the normalized base hole charge term, q1I in Mextram terminology, that goes directly into the In expression, or indirectly due to propagation of the CB discharging current induced distortion to IN, through circuit interactions. We will show that it is the later rather than the former with carefully designed custom Verilog-A codes of Mextram, by using separate CB depletion capacitance models in the main current equation formulation and the CB depletion charge equations. Changing the CB depletion capacitance model used in the main current equation leads to no visible changes in IP3, while changing the CB depletion capacitance model used in the CB depletion charge equation leads to obvious changes in third order output current and hence IP3. This proves that the observed third order distortion current improvement in In responsible for the improved IP3 peak modeling in Mextram 505 fundamentally results from the CB depletion charge term, despite the small values of third order distortion in the CB depletion charge current itself.We will then further examine how reducing the CB junction depletion capacitance might affect IP3 and how the partition between extrinsic and intrinsic CB junction capacitance affects IP3 peak behavior. Interestingly, simply making all CB depletion capacitance extrinsic gets rid of the IP3 peak modeling problem in Mextram 504, implying that the high injection related increase of the intrinsic CB junction depletion charge control voltage Vjunc and its related smooth limiting parameter Vch are the root problems. A reduction of CB depletion capacitance, intrinsic or extrinsic, is found to be beneficial for IP3 peak improvement.[1] G. Niu, H. Zhang, Y. Li, X. Ding, M. Willemsen, and A. Scholten, “Physics and Compact Modeling of SiGe HBT Linearity Using Mextram,” ECS Transactions, 86 (7), pp. 145-154, 2018.[2] G. Niu, R. van der Toorn, J. C. J. Paasschens, W. J. Kloosterman, The Mextram Bipolar Transistor Model, 505.10, Model Definition Document, Auburn University, 2019.