Intrinsic Capacitance Research Articles

An empirical nonlinear RF model for CMOS fet suitable for modeling the breakdown region

ABSTRACTThis paper deals with modeling of drain current IDS(VGS,VDS) and intrinsic nonlinear capacitances Cgs(VGS,VDS) and Cgd(VGS,VDS) of the CMOS FET by means of empirical analytical expressions. The proposed models are based on exponential series allowing modeling of the CMOS FET from the linear to the breakdown region. Several High Voltage CMOS (HVMOS) FETs were used to validate the proposed models under pulsed DC, small and large signals. The high correlation between simulated and measured data supports the capability of the proposed empirical model to predict the electrical behavior of the CMOS FET. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:563–567, 2017

Foldable All-Solid-State Supercapacitors Integrated with Photodetectors

Recent development in flexible electronics has promoted the increasing demand for their energy storage systems that will be lightweight, thin, flexible, and even foldable. Although various flexible supercapacitors recently have been successfully developed, the design and assembly of highly foldable supercapacitors have received less attention. Furthermore, foldable supercapacitors are in general operated independently with other electronics, resulting in some space and energy consumption from the external connection system. Therefore, the authors fabricate the foldable all-solid-state integrated devices with supercapacitor and photodetector functions in a simplified and compact configuration based on single-walled carbon nanotube films and TiO2 nanoparticles. The integrated devices not only retain the intrinsic capacitance behavior but also show excellent sensitivity of detecting white light. More importantly, the capacitance behavior of integrated devices remains almost unchanged and the photodetector behavior is quite stable even folded by 180° due to their unique integrated configuration. Such rational design of all-solid-state integrated devices will pave the way for assembling energy storage devices and other electronics into highly flexible and foldable integrated devices.

Influence of mesa edge capacitance on frequency behavior of millimeter-wave AlGaN/GaN HEMTs

The influence of mesa edge capacitance on the frequency characteristics of AlGaN/GaN HEMTs with 90nm gate length was studied in this paper. To extract mesa edge capacitances, a small-signal equivalent circuit model considering mesa edge capacitances was provided. Based on the model, the intrinsic gate capacitances of AlGaN/GaN HEMTs with 2×20μm, 2×30μm, 2×40μm, and 2×50μm gate widths were extracted, respectively. Through linear fitting along gate width for the extracted results and simulations, 8.06fF/μm2 of mesa edge capacitances at Vgs=−4.5V and Vds=8V in the devices with 2×20μm gate width was obtained, which can be about 33.2% of the total gate capacitance. Mesa edge capacitances results in a significant drop of current-gain cut-off frequency (fT), and the effect is more serious in the shorter gate length devices.

Effect of spacer dielectric engineering on Asymmetric Source Underlapped Double Gate MOSFET using Gate Stack

In this paper, the use of high-k spacers in a source underlapped nMOSFET is explored. The effects have been reported by varying the dielectric constant of the spacer from 3.9 to 22.5 and the study includes a comparison of analog parameters such as transconductance, transconductance generation factor, intrinsic gain, and RF parameters such as parasitic capacitances, resistances, and cut-off frequency. The RF parameters are calculated using the Non-Quasi Static (NQS) Approach which is required for sub 20 nm technology node. The device with high-k spacers features an improvement of 33% in DIBL, significantly increases the on current and reducing the off current by 60%. However, there is a slight compromise in the RF performance of the device, owing to an increase in intrinsic capacitance by about 0.35 fF. The Voltage Transfer Characteristics (VTC) and AC gain analysis of the circuit is also done in this paper. The circuit performance using single stage amplifier with the proposed device as the driver MOS has been analysed. High-k spacers also account for 19% improvement in small signal gain when used in a single stage amplifier circuit.

Investigation of the Differential Capacitance of Highly Ordered Pyrolytic Graphite as a Model Material of Graphene.

A study of the differences among the capacitances of freshly exfoliated highly ordered pyrolytic graphite (HOPG, sample denoted FEG), HOPG aged in air (denoted AAG), and HOPG aged in an inert atmosphere (hereafter IAG) is presented in this work. The FEG is found to be more hydrophilic than AAG and IAG because the aqueous electrolyte contact angle (CA) increases from 61.7° to 72.5° and 81.8° after aging in Ar and air, respectively. Electrochemical impedance spectroscopy shows the FEG has an intrinsic capacitance (6.0 μF cm-2 at the potential of minimum capacitance) higher than those of AAG (4.3 μF cm-2) and IAG (4.7 μF cm-2). The observed changes in the electrochemical response are correlated with spectroscopic characterization (Raman spectroscopy and X-ray photoelectron spectroscopy), which show that the surface of HOPG was doped or contaminated after exposure to air. Taken together, these changes upon atmospheric exposure are attributed to oxygen molecule, moisture, and airborne organic contaminations: high-vacuum annealing was applied for the removal of the adsorbed contaminants. It was found that annealing the aged sample at 500 °C leads to partial removal of the contaminants, as gauged by the recovery of the measured capacitance. To the best of our knowledge, this is first study of the effect of the airborne contaminants on the capacitance of carbon-based materials.

Monte Carlo Study of 2-D Capacitance Fringing Effects in GaAs Planar Schottky Diodes

Nanometer scale planar Schottky barrier diodes (SBDs) with realistic geometries have been studied by means of a 2-D ensemble Monte Carlo simulator. The topology of the devices studied in this paper is based in real planar GaAs SBDs used in terahertz applications, such as passive frequency mixing and multiplication, in which accurate models for the diode capacitance are required. The intrinsic capacitance of such small devices, which due to edge effects strongly deviates from the ideal value, has been calculated. In good agreement with the classical models, we have found that the edge capacitance is independent of the properties of the semiconductor beneath the contact and, as novel result, that the presence of surface charges at the semiconductor dielectric interface can reduce it almost 15%. We have finally provided a compact model for the total capacitance of diodes with arbitrary shape that could be easily implemented in design automation software such as Advance Design System (ADS).

The Study of Porous Geometry Design for Capacitive Deionization Devices through Vertically-Aligned Carbon Nanotube Electrodes

In the face of an increasing water crisis, we are developing tools to optimize capacitive deionization (CDI) for brackish water desalination. CDI can be a competitive technology for brackish water treatment due to its higher energy efficiencies compared to reverse osmosis and its more inherent resistance to fouling [1]. However, CDI is still a developing technology where adsorption capacity and salt removal rates into porous, tortuous carbon electrodes is still low. We have designed vertically-aligned carbon nanotube (VA-CNT) electrodes, with minimal tortuosity, to investigate the role of porous geometry on the performance of flow-by CDI devices, specifically examining changes in diffusion resistance, salt adsorption rate and capacity. Previously, a breadth of carbon materials have been investigated for CDI including activated carbon, carbon aerogels, ordered mesoporous carbons, carbide-derived carbons, and carbon nanotubes, among many others [2]. High salt adsorption capacities have been attributed to the presence of micropores (< 2 nm), [3] and optimal materials seem to have a presence of macroporous pathways with microporous structures. [4, 5] However, many carbon materials have tortuous pores making it challenging to decouple the role of pore diameter on salt adsorption rate. VA-CNTs are an exciting material for investigating this issue due to the ability to manipulate the inter-CNT spacing, to study changes in the ion transport rate as a function of geometry, while maintaining mininimal tortuosity and intrinsic capacitance. In this work, we synthesize VA-CNT electrodes that are sparse (inter-CNT spacings upto 100 nm), and more dense CNTs (inter-CNT spacings upto 25 nm). These CNTs are grown using a standard chemical vapor deposition of ethylene on silicon wafers with iron catalyst. By varying the partial pressure of ethylene and the oxygen content in the furnace, we synthesize CNTs of varying densities. The VA-CNT forests is delaminated from the substrate with a high-temperature oxygen etch, seperating the carbon from the corrosive catalyst. The free-standing films are mounted against Ti metal plates serving as the current collectors, and constrained by a PEEK porous mesh (200 μm window, 40 μm wire diameter). We use a flow-by CDI experimental set up to study the role of varying voltages, electrode thicknesses, CNT densities, and chemical functionalization on desalination performance. We find that in a 1mM NaCl solution, CNT electrodes can adsorb from 5-15 mg salt/g carbon, at rates of 0.2-1 mg/g-min. Through densification, we maintain gravimetric performance, but increase our volumetric salt adsorption capacity from 0.2 to 0.3 g/cm3. We achieve charge efficiencies upto 80% for these systems. We combine this experimental investigation with an electric double layer model for macroporous electrodes to inform the design of carbon electrode materials for optimal ion adsorption and throughput in a flow-by CDI device. [1] T. Humplik, J. Lee, S. O'Hern, B. Fellman, M. Baig, S. Hassan, et al., Nanotechnology, 22, 292001 (2011). [2] S. Porada, R. Zhao, A. v. d. Wal, V. Presser, and P. M. Biesheuvel, Progress in Materials Science, 58, 8 (2013). [3] S. Porada, L. Weinstein, R. Dash, A. v. d. Wal, M. Bryjak, Y. Gogotsi, et al., ACS applied materials & interfaces, 4, 3 (2012). [4] M. Suss, T. Baumann, W. Bourcier, C. Spadaccini, K. Rose, et al., Energy & Environmental Science, 5, 11 (2012). [5] C. Tsouris, J. Mayes, K. Sharma, S. Yiacoumi, et al., Environmental Science & Technology, 45, 23 (2011).

Highly Flexible, Freestanding Supercapacitor Electrode with Enhanced Performance Obtained by Hybridizing Polypyrrole Chains with MXene

Though polypyrrole (PPy) is widely used in flexible supercapacitors owing to its high electrochemical activity and intrinsic flexibility, limited capacitance and cycling stability of freestanding PPy films greatly reduce their practicality in real‐world applications. Herein, we report a new approach to enhance PPy's capacitance and cycling stability by forming a freestanding and conductive hybrid film through intercalating PPy into layered Ti3C2 (l‐Ti3C2, a MXene material). The capacitance increases from 150 (300) to 203 mF cm−2 (406 F cm−3). Moreover, almost 100% capacitance retention is achieved, even after 20 000 charging/discharging cycles. The analyses reveal that l‐Ti3C2 effectively prevents dense PPy stacking, benefiting the electrolyte infiltration. Furthermore, strong bonds, formed between the PPy backbones and surfaces of l‐Ti3C2, not only ensure good conductivity and provide precise pathways for charge‐carrier transport but also improve the structural stability of PPy backbones. The freestanding PPy/l‐Ti3C2 film is further used to fabricate an ultra‐thin all‐solid‐state supercapacitor, which shows an excellent capacitance (35 mF cm−2), stable performance at any bending state and during 10 000 charging/discharging cycles. This novel strategy provides a new way to design conductive polymer‐based freestanding flexible electrodes with greatly improved electrochemical performances.

Study of process induced variability of germanium-pTFET in analog and RF domain

Germanium (Ge) tunnel field effect transistor (TFET) is considered to be an excellent solution to resolve the low on-currents issue of Silicon-based TFETs. Whereas, process variability in any low technology node devices (sub-100nm) is a crucial subject of matter which affects the device reliability and dependability in advanced SoC applications. In this brief, we have investigated the two main process induced variability a) the thickness of the germanium body b) the thickness of gate oxide in Ge-pTFET using Sentaurus TCAD device simulation. The analysis is performed in complete analog domain along with the study of intrinsic RF performance parameters using small signal equivalent model with non-quasi static effect of the device under consideration. The process induced variability is estimated on the figure of merits (FOMs) such as drain current (Ids), transconductance (gm), output resistance (Ro), intrinsic gain (gmRo), unity-gain cutoff frequency (fT), transit frequency of maximum available power gain (fMAX), transport delay (τm), intrinsic resistance (Rgd) and intrinsic capacitances (Cgs, Cgd).

Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers

This paper presents the design of a matching network (MN) for switched-capacitor PAs (SCPA) optimized for efficiency against required load output power. The presented third-order MN exploits the intrinsic output capacitance of the SCPA, reducing the number of passive components required by the MN. As an example, a MN for a 1.1 V switched capacitor power amplifier has been designed with a bluetooth application in mind. The example MN has been implemented in a 28 nm CMOS RF metal stack and provides 16.7 dBm output power with IL = 1.1 dB at 2.4 GHz in an area of 300 × 300 μm2 when resonated by an SCPA capacitance of 2.3 pF. Further structures have then been implemented and characterized, covering a broader set of applications.

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of high-k spacers. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE’s), however, it significantly reduces the on current due to the increased channel resistance. To overcome these drawbacks, the use of high-k spacers is projected as one of the remedies. In this paper, the analog performance of the devices is studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/Id) and intrinsic gain (gmro). The RF performance is analyzed on the merits of intrinsic capacitance (Cgd, Cgs), resistance (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillation (fmax). The circuit performance of the devices are studied by implementing the device as the driver MOSFET in a Single Stage Common Source Amplifier. The Gain Bandwidth Product (GBW) has been analyzed from the frequency response of the circuit.

Large-Signal Model of Graphene Field-Effect Transistors—Part I: Compact Modeling of GFET Intrinsic Capacitances

We present a circuit-compatible compact model of the intrinsic capacitances of graphene field-effect transistors (GFETs). Together with a compact drain current model, a large-signal model of GFETs is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the DC, transient behavior, and frequency response of the circuit. The drain current model is based in a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward-Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional non-idealities.

Physically Based Predictive Model for Single Event Transients in CMOS Gates

An analytical model is presented to understand the time response of an inverter to ionizing particles based on physical equations. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state nMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state nMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state pMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state pMOS resistance, doping concentration of P-region in the diode, and the photocurrent pulse are scrutinized.

An Accurate Empirical Model Based on Volterra Series for FET Power Detectors

An empirical model for field-effect transistor (FET) based power detectors is presented. The electrical model constitutes a Volterra analysis based on a Taylor series expansion of the drain current together with a linear embedding small-signal circuit. It is fully extracted from S-parameters and IV curves. The final result are closed-form expressions for the frequency dependence of the noise equivalent power (NEP) in terms of the FET intrinsic capacitances and parasitic resistances. Excellent model agreement to measured NEP of coplanar access graphene FETs with varying channel dimensions up to 67 GHz is obtained. The influence of gate length on responsivity and NEP is theoretically and experimentally studied.

Influence of Underlap on Gate Stack DG-MOSFET for analytical study of Analog/RF performance

In this paper, the characteristics of 18 nm Underlap Double Gate (U-DG) NMOSFET with gate stack, (GS) are presented. The high-k dielectric as gate insulator under consideration is Hafnium Dioxide (HfO2). The SiO2 padding reduces the effect of scattering at the silicon and oxide interface. The ratio of on current to off current is used for optimizing the underlap length. The Analog and RF performance comparison are shown in this paper considering the drain current (Id), the transconductance (gm), the intrinsic gain (gmRo), the intrinsic capacitances (Cgs, Cgd), the intrinsic resistances (Rgs, Rgd), the transport delay (τm), the intrinsic inductance (Hsd), the unity current gain cut-off frequency (fT) and the maximum frequency of oscillation (fmax). RF parameters are extracted using the Non Quasi Static (NQS) model of the U-DG MOSFET. The performance of single stage amplifiers using the devices is also analyzed. The sharpest transition is shown in case of U-DG-GS MOSFET with optimized underlap length and enhancement in the intrinsic capacitances and resistances, and unity Gain Bandwidth product in case of devices with GS.

Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes short-channel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results.

Resonance-induced enhancement of the energy harvesting performance of piezoelectric flags

The spontaneous flapping of a flag can be used to produce electrical energy from a fluid flow when coupled to a generator. In this paper, the energy harvesting performance of a flag covered by a single pair of polyvinylidene difluoride piezoelectric electrodes is studied both experimentally and numerically. The electrodes are connected to a resistive-inductive circuit that forms a resonant circuit with the piezoelectric's intrinsic capacitance. Compared with purely resistive circuits, the resonance between the circuit and the flag's flapping motion leads to a significant increase in the harvested energy. Our experimental study also validates our fluid-solid-electric nonlinear numerical model.

Quantum decay of the supercurrent and intrinsic capacitance of Josephson junctions beyond the tunnel limit

A nondissipative supercurrent state of a Josephson junction is metastable with respect to the formation of a finite-resistance state. This transition is driven by fluctuations, thermal at high temperatures and quantum at low temperatures. We evaluate the lifetime of such a state due to quantum fluctuations in the limit when the supercurrent is approaching the critical current. The decay probability is determined by the instanton action for the superconducting phase difference across the junction. At low temperatures, the dynamics of the phase is massive and is determined by the effective capacitance, which is a sum of the geometric and intrinsic capacitance of the junction. We model the central part of the Josephson junction either by an arbitrary short mesoscopic conductor described by the set of its transmission coefficients, or by a diffusive wire of an arbitrary length. The intrinsic capacitance can generally be estimated as ${C}_{*}\ensuremath{\sim}G/{E}_{g}$, where $G$ is the normal-state conductance of the junction and ${E}_{g}$ is the proximity minigap in its normal part. The obtained capacitance is sufficiently large to qualitatively explain the hysteretic behavior of the current-voltage characteristic even in the absence of overheating.

Benchmarking of MoS2FETs With Multigate Si-FET Options for 5 nm and Beyond

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET.