Abstract
ABSTRACTThis paper deals with modeling of drain current IDS(VGS,VDS) and intrinsic nonlinear capacitances Cgs(VGS,VDS) and Cgd(VGS,VDS) of the CMOS FET by means of empirical analytical expressions. The proposed models are based on exponential series allowing modeling of the CMOS FET from the linear to the breakdown region. Several High Voltage CMOS (HVMOS) FETs were used to validate the proposed models under pulsed DC, small and large signals. The high correlation between simulated and measured data supports the capability of the proposed empirical model to predict the electrical behavior of the CMOS FET. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:563–567, 2017
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
