Intra-chip Communication Research Articles

Integrating deep convolutional surrogate solvers and particle swarm optimization for efficient inverse design of plasmonic patch nanoantennas

Abstract Plasmonic nanoantennas with suitable far-field characteristics are of huge interest for utilization in optical wireless links, inter-/intrachip communications, LiDARs, and photonic integrated circuits due to their exceptional modal confinement. Despite its success in shaping robust antenna design theories in radio frequency and millimeter-wave regimes, conventional transmission line theory finds its validity diminished in the optical frequencies, leading to a noticeable void in a generalized theory for antenna design in the optical domain. By utilizing neural networks, and through a one-time training of the network, one can transform the plasmonic nanoantennas design into an automated, data-driven task. In this work, we have developed a multi-head deep convolutional neural network serving as an efficient inverse-design framework for plasmonic patch nanoantennas. Our framework is designed with the main goal of determining the optimal geometries of nanoantennas to achieve the desired (inquired by the designer) S 11 and radiation pattern simultaneously. The proposed approach preserves the one-to-many mappings, enabling us to generate diverse designs. In addition, apart from the primary fabrication limitations that were considered while generating the dataset, further design and fabrication constraints can also be applied after the training process. In addition to possessing an exceptionally rapid surrogate solver capable of predicting S 11 and radiation patterns throughout the entire design frequency spectrum, we are introducing what we believe to be the pioneering inverse design network. This network enables the creation of efficient plasmonic antennas while concurrently accommodating customizable queries for both S 11 and radiation patterns, achieving remarkable accuracy within a single network framework. Our framework is capable of designing a wide range of devices, including single band, dual band, and broadband antennas, with directivities and radiation efficiencies reaching 11.07 dBi and 75 %, respectively, for a single patch. The proposed approach has been developed as a transformative shift in the inverse design of photonics components, with its impact extending beyond antenna design, opening a new paradigm toward real-time design of application-specific nanophotonic devices.

Design and Modeling of a Terahertz Transceiver for Intra- and Inter-Chip Communications in Wireless Network-on-Chip Architectures.

This paper addresses the increasing demand for computing power and the challenges associated with adding more core units to a computer processor. It explores the utilization of System-on-Chip (SoC) technology, which integrates Terahertz (THz) wave communication capabilities for intra- and inter-chip communication, using the concept of Wireless Network-on-Chips (WNoCs). Various types of network topologies are discussed, along with the disadvantages of wired networks. We explore the idea of applying wireless connections among cores and across the chip. Additionally, we describe the WNoC architecture, the flip-chip package, and the THz antenna. Electromagnetic fields are analyzed using a full-wave simulation software, Ansys High Frequency Structure Simulator (HFSS). The simulation is conducted with dipole and zigzag antennas communicating within the chip at resonant frequencies of 446 GHz and 462.5 GHz, with transmission coefficients of around -28 dB and -33 to -41 dB, respectively. Transmission coefficient characterization, path loss analysis, a study of electric field distribution, and a basic link budget for transmission are provided. Furthermore, the feasibility of calculated transmission power is validated in cases of high insertion loss, ensuring that the achieved energy expenditure is less than 1 pJ/bit. Finally, employing a similar setup, we study intra-chip communication using the same antennas. Simulation results indicate that the zigzag antenna exhibits a higher electric field magnitude compared with the dipole antenna across the simulated chip structure. We conclude that transmission occurs through reflection from the ground plane of a printed circuit board (PCB), as evidenced by the electric field distribution.

Characterizing Multi-Chip GPU Data Sharing

Multi-chip Graphics Processing Unit (GPU) systems are critical to scale performance beyond a single GPU chip for a wide variety of important emerging applications. A key challenge for multi-chip GPUs, though, is how to overcome the bandwidth gap between inter-chip and intra-chip communication. Accesses to shared data, i.e., data accessed by multiple chips, pose a major performance challenge as they incur remote memory accesses possibly congesting the inter-chip links and degrading overall system performance. This article characterizes the shared dataset in multi-chip GPUs in terms of (1) truly versus falsely shared data, (2) how the shared dataset scales with input size, (3) along which dimensions the shared dataset scales, and (4) how sensitive the shared dataset is with respect to the input’s characteristics, i.e., node degree and connectivity in graph workloads. We observe significant variety in scaling behavior across workloads: some workloads feature a shared dataset that scales linearly with input size, whereas others feature sublinear scaling (following a \(\sqrt {2}\) or \(\sqrt [3]{2}\) relationship). We further demonstrate how the shared dataset affects the optimum last-level cache organization (memory-side versus SM-side) in multi-chip GPUs, as well as optimum memory page allocation and thread scheduling policy. Sensitivity analyses demonstrate the insights across the broad design space.

Single-mode waveguide-coupled light emitting diodes in unmodified silicon photonics fabrication processes

We realize single-mode, waveguide-coupled, electrically driven silicon light emitting diodes in commercial, unmodified silicon photonics foundry processes and develop a model of both the electrical and optical behavior to understand the performance limitations. We measure a center wavelength of 1130 nm, a 90 nm 3 dB optical bandwidth, and 200 pW of optical power propagating in each direction. We show on-chip modulation and detection of the generated light using native resonant photodetectors integrated in the same chip. Our work unveils a new native light source available in silicon photonics processes, which can find applications ranging from device screening and fabrication quality assessment to imaging, refractive index sensing, or intra-chip communication.

Self-controlling photonic-on-chip networks with deep reinforcement learning

We present a novel photonic chip design for high bandwidth four-degree optical switches that support high-dimensional switching mechanisms with low insertion loss and low crosstalk in a low power consumption level and a short switching time. Such four-degree photonic chips can be used to build an integrated full-grid Photonic-on-Chip Network (PCN). With four distinct input/output directions, the proposed photonic chips are superior compared to the current bidirectional photonic switches, where a conventionally sizable PCN can only be constructed as a linear chain of bidirectional chips. Our four-directional photonic chips are more flexible and scalable for the design of modern optical switches, enabling the construction of multi-dimensional photonic chip networks that are widely applied for intra-chip communication networks and photonic data centers. More noticeably, our photonic networks can be self-controlling with our proposed Multi-Sample Discovery model, a deep reinforcement learning model based on Proximal Policy Optimization. On a PCN, we can optimize many criteria such as transmission loss, power consumption, and routing time, while preserving performance and scaling up the network with dynamic changes. Experiments on simulated data demonstrate the effectiveness and scalability of the proposed architectural design and optimization algorithm. Perceivable insights make the constructed architecture become the self-controlling photonic-on-chip networks.

Advancing in-memory Arithmetic Based on CMOS-integrable Memristive Crossbar Structures

Memristive computing will be advantageous in large-scale, highly parallel mixed-mode processing architectures because processing can be performed directly within memristive memory architectures and intrachip communication can be implemented by a memristive crossbar structure with reconfigurable logic gates. Here we report on the development of a new concept for in-memory adders, using XOR functionality. Exploited memristive crossbar structures are based on memristive complementary resistive switches, e.g. TaOx, and BiFeO3.

An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method

Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.

Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications.

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

An Analysis of RF On-Chip Antennas in Si-Based Integrated Microwave Photonics

We investigate the monolithic integration of RF antennas onto a silicon-based integrated microwave photonics (IMWP) chip for short-range millimeter-wave (mmW) communication. The unification of antenna with photonic integrated circuits (PICs) reduces system loss for high data rate communication by eliminating parasitic interconnects. This integration of electronics (antenna) with photonics will be a key milestone leading to increased bandwidth capability and ubiquitous wireless links for emerging applications such as 5G, Internet of Things (IoT), autonomous vehicles, high data rate point-to-point communication, and wireless sensors. Through simulation above 20 GHz, we compare the transmission of three on-chip antenna structures designed in a commercial silicon photonics (SiPh) process and consider them for both inter and intra-chip communication. Results provide insight on the transmission gain variations relative to the antenna orientation from their distinct radiation pattern. The folded monopole structure provides superior gain, smaller footprint with layout flexibility, and good transmission spectrum. The analysis supports the idea of a monolithic mmW transmitter integrated with on-chip antennas on IMWP chip.

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective

The academia and industry have been pursuing network-on-chip (NoC) related research since two decades ago when there was an urgency to respond to the scaling and technological challenges imposed on intra-chip communication in SoC designs. Like any other research topic, NoC inevitably goes through its life cycle: A. it started up (2000–2007) and quickly gained traction in its own right; B. it then entered the phase of growth and shakeout (2008–2013) with the research outcomes peaked in 2010 and remained high for another four/five years; C. NoC research was considered mature and stable (2014–2020), with signs showing a steady slowdown. Although from time to time, excellent survey articles on different subjects/aspects of NoC appeared in the open literature, yet there is no general consensus on where we are in this NoC roadmap and where we are heading, largely due to lack of an overarching methodology and tool to assess and quantify the research outcomes and evolution. In this paper, we address this issue from the perspective of three specific complex networks, namely the citation network, the subject citation network, and the co-authorship network. The network structure parameters ( e.g. , modularity, diameter, etc. ) and graph dynamics of the three networks are extracted and analyzed, which helps reveal and explain the reasons and the driving forces behind all the changes observed in NoC research over 20 years. Additional analyses are performed in this study to link interesting phenomena surrounding the NoC area. They include: (1) relationships between communities in citation networks and NoC subjects, (2) measure and visualization of a subject’s influence score and its evolution, (3) knowledge flow among the six most popular NoC subjects and their relationships, (4) evolution of various subjects in terms of number of publications, (5) collaboration patterns and cross-community collaboration among the authors in NoC research, (6) interesting observation of career lifetime and productivity among NoC researchers, and finally (7) investigation of whether or not new authors are chasing hot subjects in NoC. All these analyses have led to a prediction of publications, subjects, and co-authorship in NoC research in the near future, which is also presented in the paper.

A New Router Architecture for High-Performance Intrachip Networks

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication

A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO2 with much smaller and hence denser interconnects, are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of ∼19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ∼ $0.18\text{ ps} $ and $0.19\text{ ps},$ energy dissipation per computing bit of ∼ $2.5 \times {10^{ - 3}}{\rm{ fJ}}/{\rm{bit}}$ and $3.8 \times {10^{ - 3}}{\rm{ fJ}}/{\rm{bit}}$ , and 25% crosstalk coupling length of $155{\rm{ \mu m}}$ and $125{\rm{ \mu}} \text{m}$ . These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters.

Antenna Arrays as Millimeter-Wave Wireless Interconnects in Multichip Systems

In this letter, the transmission characteristics between on-chip arrays and their beamforming capabilities for intrachip and interchip communication in multichip systems are simulated and measured using various fabricated arrays on silicon chips. The measured intrachip and interchip maximum transmission coefficients for various arrays without metal sheets range from −37 to −45 dB and −46 to −51 dB, respectively at 60 GHz. The beamforming for arrays with and without feed structures is compared by radiation pattern using simulations. Moreover, the transmission with metal sheets, emulating realistic multicores, shows a reduction of about 10 dB for intrachip communication compared with cases having no sheets. In this letter, we have demonstrated that beamforming and beam steering can be successfully achieved.

NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators

Large-scale neural network (NN) accelerators typically consist of several processing nodes, which could be implemented as a multi- or many-core chip and organized via a network-on-chip (NoC) to handle the heavy neuron-to-neuron traffic. Multiple NoC-based NN chips are connected through chip-to-chip interconnection networks to further boost the overall neural acceleration capability. Huge amounts of multicast-based traffic travel on-chip or cross chips, making the interconnection network design more challenging and become the bottleneck of the NN system performance and energy. In this article, we propose coupling intrachip and interchip communication techniques, called NeuronLink, for NN accelerators. Regarding the intrachip communication, we propose scoring crossbar arbitration, arbitration interception, and route computation parallelization techniques for virtual-channel routing, leading to a high-throughput NoC with a lower hardware cost for multicast-based traffic. Regarding the interchip communication, we propose a lightweight and NoC-aware chip-to-chip interconnection scheme, enabling efficient interconnection for NoC-based NN chips. In addition, we evaluate the proposed techniques on a four connected NoC-based deep neural network (DNN) chips with four field-programmable gate arrays (FPGAs). The experimental results show that the proposed interconnection network can efficiently manage the data traffic inside DNNs with high-throughput and low-overhead against state-of-the-art interconnects.

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding of the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system’s monolithic nature to engineer the channel , this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it , pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and $7.3\times $ , respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case.

Plasmonic interconnects for global wires in integrated circuits

Surface plasmon polaritons (SPPs) are bound electromagnetic waves propagating at a dielectric-metal interface, which have gained attention for high performance and ability for miniaturisation in high-speed dense circuits, due to their subwavelength properties. A dielectric-metal-dielectric (I-M-I) plasmonic waveguide with a 40 nm thick metal or metal-like strip on silicon substrate is proposed for intra-chip communication. The propagation characteristics of the I-M-I waveguide are investigated by numerical simulation and the modes are experimentally verified by scanning near-field optical microscopy. Metal lines as thin as 40 nm can have propagation lengths as large as 239 μm, which has small footprint compatible with the advanced interconnect process.

ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs

The end of Dennard scaling led to the use of heterogeneous multi-processor systems-on-chip (MPSoCs). Heterogeneous MPSoCs provide a high efficiency in terms of energy and performance due to the fact that each processing element can be optimized for an application task. However, the evolution of MPSoCs shows a growing number of processing elements (PEs), which leads to tremendous communication costs, tending to become the performance bottleneck. Networks-on-chip (NoCs) are a promising and scalable intra-chip communication technology for MPSoCs. However, these technological advances require novel and effective programming methodologies to efficiently exploit them. This work presents a novel router architecture called application-specific instruction-set router (ASIR) for field-programmable-gate-arrays (FPGA)-based MPSoCs. It combines data transfers with application-specific processing by adding high-level synthesized processing units to routers of the NoC. The execution of application-specific operations during data exchange between PEs exploits efficiently the transmission time. Furthermore, the processing units can be programmed in C/C++ using high-level synthesis, and accordingly, they can be specifically optimized for an application. This approach enables transferred data to be processed by a processing element, such as a MicroBlaze processor, before the transmission or by a router during the transmission. Moreover, a static mapping algorithm for applications modeled by a Kahn process network-based graph is introduced that maps tasks to the MicroBlaze processors and processing units. The mapping algorithm optimizes the communication cost by allocating tasks to nearest neighboring PEs. This complete methodology significantly simplifies the design and programming of ASIR-based MPSoCs. Furthermore, it efficiently exploits the heterogeneity of processing capabilities inside the routers and MicroBlaze processors.

A joint optimization method for NoC topology generation

The increasing demand on efficient intra-chip communication of multicore systems has driven the interconnection structure to evolve from bus/ring to Network-on-Chip (NoC). NoC design is fundamentally based on network topology generation and floorplanning. This paper proposes a joint optimization method to generate network topologies based on the floorplanning of heterogeneous IP cores for a given application-specific NoC. This method starts with clustering the heterogeneous IP cores according to their communication workloads using fuzzy clustering. It proceeds to apply a genetic algorithm to optimize the floorplanning by minimizing power consumption and/or chip area. By adding a router to each cluster of IP cores, network topologies are further generated via connecting routers based on the principles of scale-free networks. Experiments with a video processing application show that the optimized floorplanning of IP cores can be achieved by either minimizing the power consumption or chip area. An OPNET simulator is used to evaluate the performance of the NoC designed based on the proposed method. Experimental results demonstrate that the performance requirements of the application-specific NoC can be satisfied.

Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications

We propose a novel antenna design enabled by 3-D printing technology for future wireless intrachip interconnects aiming at applications of multicore architectures and system-on-chips. In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated, and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work.

A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems

Computing modules in typical datacenter nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the destination chip over a wireline interconnect fabric. This multihop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to limitations of pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. Here, we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.