Abstract
A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO2 with much smaller and hence denser interconnects, are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of ∼19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ∼ $0.18\text{ ps} $ and $0.19\text{ ps},$ energy dissipation per computing bit of ∼ $2.5 \times {10^{ - 3}}{\rm{ fJ}}/{\rm{bit}}$ and $3.8 \times {10^{ - 3}}{\rm{ fJ}}/{\rm{bit}}$ , and 25% crosstalk coupling length of $155{\rm{ \mu m}}$ and $125{\rm{ \mu}} \text{m}$ . These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters.
Highlights
In the pursuit of Moore’s law for traditional electronic integrated circuits, innovation is required to overcome the challenges in both physics and economics beyond the 10 nm node [1]
Since plasmonic waveguides will substitute for the traditional global wire in an IC chip, we commence by considering the surface plasmon polaritons (SPP) modes in the symmetric investigate the symmetrical multilayer structures (I-M-I) configuration of a thin metal or metal-like strip sandwiched between the dielectric films
An optimized CMOS-compatible dielectric-metal-dielectric (I-M-I) plasmonic waveguides is proposed for intra-chip communication consisting of 40 nm thick Cu or pulsed laser deposition (PLD)-TiN sandwiched between SiO2 with lateral line gap of 950 nm and 400 nm, respectively for lines of up to 100 μm long
Summary
In the pursuit of Moore’s law for traditional electronic integrated circuits, innovation is required to overcome the challenges in both physics and economics beyond the 10 nm node [1]. In the level of asynchronous communication within chip the global wires (top metal layers) are much thicker (thickness, T ∼ 6 μm) and with a wider pitch (∼1 to 11 μm) than the metal layers beneath (local and intermediate wires), in order to decrease the series resistance and improve the Q-factor for broader bandwidth data transport. Since plasmonic waveguides will substitute for the traditional global wire (top metal) in an IC chip, we commence by considering the SPP modes in the symmetric I-M-I configuration of a thin metal or metal-like strip sandwiched between the dielectric films. A spectrum of wave vectors of SPP is generated by a tunnel junction, a single-wavelength SPP wave can be coupled into a definite plasmonic waveguide selectively with the use of a surface grating to improve excitation efficiency, which is not the subject of the current paper
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
