Interposer Wafer Research Articles

3D Heterogenous Integrated Wideband Switchable Bandpass Filter Bank for Millimeter Wave Applications

This article proposes a three-dimensional heterogenous-integrated (3DHI) switchable bandpass filter bank with two independent wideband filter channels that cover 26–40 GHz and 32.5–40 GHz, respectively. An accurate wafer-level process with a high hollowed ratio of the applied 8-inch high-resistivity-silicon (HR-Si) interposer wafers is presented to form both compact filter channels. Above the interdigital filter patterns fabricated on the bottom interposer wafer, deep cavities are etched in the cap interposer wafer to improve the quality factor of the filter bank. Besides the cavities, the cap interposer wafer is 35% hollow inside, which two bare dies of GaAs single-pole double-throw (SPDT) switches and two thin film resistors are attached to the bottom interposer after the wafer-to-wafer (W2W) bonding. To ensure good out-of-band performance, a 3D EM co-simulation of the switch layout at the chip level and filter patterns at the package level is applied. Measurement results show that the switchable filter bank achieves a high isolation of 50 dB and a competitive shape factor (BW30dB/BW3dB) of about 1.3. In addition, the size of the switchable filter bank is only 7.0 mm × 3.5 mm × 0.6 mm, and the weight is only 0.1 g.

Novel Hybrid Bonding Technology Using Ultra-High Density Cu Nano-Pillar for Exascale 2.5D/3D Integration

We propose a novel hybrid bonding technology with a high stacking yield using ultra-high density Cu nano-pillar (CNP) for exascale 2.5D/3D integration. To solve the critical issues of a current standard hybrid bonding technology, we developed scaled electrodes with slightly extruded structure and unique adhesive layer of anisotropic conductive film composed of ultra-high density CNP. Test element group (TEG) dies with 7-mm $\times 23$ -mm size are bonded to interposer wafer by a new hybrid bonding technology. Scaled electrodes with 3- $\mu \text{m}$ diameter and 6- $\mu \text{m}$ pitch are formed in each TEG chip. We confirmed for the first time that a huge number of electrodes of 4 309 200 are successfully connected in series with the joining yield of 100% due to the ultra-high density CNP.

Miniaturization and Biocompatible Encapsulation for Implantable Biomedical Silicon Devices

This paper presents a new strategy of packaging developed for medical applications which includes a sensor and an integrated circuit inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration. The electronic components are placed on a silicon interposer wafer which was bonded by AuSi solder with a silicon wafer lid containing cavities. Different metal stacks of the sealing ring including a barrier and Au have been studied. The gas content and hermeticity of the package were analyzed using Residual Gas Analysis (RGA) and biodegradation were tested in saline solution. The final silicon package was encapsulated with biocompatible materials that have high conformality deposition and act as good bi-directional barrier. Materials behavior that had been reported in literature as biocompatible and compatible with fabrication in standard clean rooms were studied. Finally, packaging materials were tested in cytotoxicity.

Miniaturization and Biocompatible Encapsulation for Implantable Biomedical Silicon Devices

This paper presents a new strategy of packaging developed for medical applications which includes a sensor and an integrated circuit inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration. The electronic components are placed on a silicon interposer wafer which was bonded by the eutectic AuSi with a silicon wafer lid containing cavities. Different metal stacks of the sealing ring including a barrier and Au have been studied. The gas content and hermeticity of the package were analyzed using Residual Gas Analysis (RGA) and biodegradation were tested in saline solution. The final silicon package was encapsulated with biocompatible materials that have high conformality deposition and act as good bi-directional barrier. Materials behavior that had been reported in literature as biocompatible and compatible with fabrication in standard clean rooms were studied. Finally, packaging materials were tested in cytotoxicity.

Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

Thin-Wafer Handling with a Heat-Spreader Wafer for 2.5D/3D IC Integration

Thin-wafer handling is one of the key enabling technologies for 2.5D/3D IC integration. Usually, it temporary bonds the TSV (through-silicon via)/RDL (redistribution layer) wafer (e.g., passive and active interposers) to a supporting carrier wafer with an adhesive, backgrinds the TSV/RDL interposer wafer to very thin (≤100μm), goes through all the necessary processes, and then de-bonds the thin TSV/RDL interposer wafer from the carrier wafer. In this study, a different route will be taken which eliminates the temporary bonding and de-bonding processes. Emphasis is placed on using a heat-spreader wafer as a supporting carrier wafer during the manufacturing processes and after the assembly is completed (diced), the heat-spreader remains on the thin TSV/RDL interposer. This is a very simple and low-cost thin-wafer handling method for 2.5D/3D IC integration.

Performance and Process Comparison between Glass and Si Interposer for 3D-IC Integration

Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed, and has been compared in complete processes and electrical/thermal characteristics with silicon interposer. In order to simulate and measure the electrical/thermal performance, patterned interposer wafer with 30μm diameter and 100μm depth Cu-filled TSVs are designed and prepared in advance. Key technologies include via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation were well developed and integrated to perform for comparison. 30μm via, 60μm pitch, RDL line/space 20μm/30um, 100μm thin wafer/glass and 15um micro-bumping been successfully integrated in the integration platform. The glass interposer was characterized and assessed to have excellent electrical performance and is potentially to be applied for 3D product applications.