Interpoly Dielectric Research Articles

A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor

Floating-gate transistor lies at the heart of many aspects of semiconductor applications such as neural networks, analog mixed-signal, neuromorphic computing, and especially in nonvolatile memories. The purpose of this paper was to design a high-performance nanocrystal floating-gate transistor in terms of a large memory window, low power, and extraordinary erasing speeds. Besides, the transistor achieves a thin thickness of the tunnel gate oxide layer. In order to obtain the high-performance design, this work proposed a set of structure parameters for the device such as the tunnel oxide layer thickness, Interpoly Dielectric (IPD), dot dimension, and dot spacing. Besides, this work was successful in the virtual fabrication process and methodology to fabricate and characterize the 65 nm nanocrystal floating-gate transistor. Regarding the results, while the fabrication process solves the limitation of the tunnel oxide layer thickness with the small value of 6 nm, the performance of the transistor has been significantly improved, such as 2.8 V of the memory window with the supply voltage of ±6 V at the control gate. In addition, the operation speeds are compatible, especially the rapid erasing speeds of 2.03 μs, 28.6 ns, and 1.6 ns when the low control gate voltages are ±9 V, ±12 V, and ±15 V, respectively.

Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review

Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.

Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review

With the increasing number of electronic consumer and information technology, demands for non-volatile memory rapidly grow. This study comprehensively reviewed the challenges related to the floating gate transistor for each component of the gate stack that consists of the tunnel oxide layer, inter-poly dielectric (IPD) oxide layer and poly-Si floating gate until reaching its bottleneck as the floating gate thickness scale to 7 nm. By going through the development of flash memory from its early year, the issues of the floating gate structure are identified. In resolving these issues, several approaches and upcoming flash memory devices are proposed. The prospect of carbon-based floating gate devices covering the graphene flash memory (GFM) and the vertical CNTFET floating gate are thoroughly discussed; reviewing its device performance and transient characteristics, which were extracted from experimental works and compared with recent upcoming technologies such as the HFG and the three-dimensional (3D) vertical flash memory. Reports indicate that graphene flash memory (GFM) capable of rivaling with the upcoming hybrid floating gate (HFG) device. It is found that the carrier concentration, transient characteristics and memory window of GFM are very much comparable to the HFG. Attributes to the high density of states (DOS) of graphene, GFM managed to lower its operating voltage while achieving comparable memory window as HFG. In the case of CNTFET with nanocrystal floating gate, the device performance is lesser than the 3D vertical flash memories in terms of its short channel effect and gate capacitance ratio. But considering its nanometer structure that has ballistic properties, better device performance with a proper definition of metal contact and synthesis can be achieved. Finally, the advantages of using graphene as floating gate are concluded and future work to improve the CNTFET floating gate is proposed.

(Invited) Influence of Post Deposition Annealing on the Electrical Properties of Pt-Ti/HfO2/TiN/Sion/n-Si Capacitor for Flash Memory Applications

To address the cell-to-cell interference in conventional floating gate (FG) flash memory, a fully planar structure demands continuous scaling of poly silicon floating gate thickness. But the reduced FG thickness causes reliability issues due to ballistic current through inter-poly dielectric (IPD) and also decreases the gate coupling ratio (GCR). The introduction of metal FG in flash memory eliminates the problem of poly depletion and ballistic transport even with ultrathin floating gate (<10 nm) and excellent memory performance with 16 V P/E window for 1 nm metal floating gate. Numerous studies on flash memory devices reported that a hybrid FG, transition metal dichalcogenides and multilayer graphene as FG results in improved memory performance such as fast program speed, excellent data retention and endurance characteristics. According to ITRS scaling projections for FG NAND flash, GCR of 0.6-0.7 would be desirable for satisfactory operation. However, in order to obtain adequate GCR, high-k based IPD and/or tunnel barrier has been proposed as mandatory alternatives. The improvement in GCR owed to greater coupling between the control and floating gates as a result of increased dielectric constant. The incorporation of nitrogen into tunnel oxide of NVM through nitridation can enhance the reliability performance of tunnel oxide of charge storage NVM. In this paper, we report the fabrication of Pt-Ti/HfO2/TiN/SiON/n-Si capacitor for flash memory applications with gate coupling ratio (GCR) of 0.68 and 0.71 for as-deposited and annealed SiON respectively. The XRD, AFM, FTIR, FESEM and XPS characterizations have been performed for structural and morphological studies. Program/erase and retention characteristics reveal the largest memory window of approx. 11.2 V after post deposition annealing and excellent data retention at room temperature under ±10 V. The enhanced program/erase speed was due to the fact that annealed SiON tunnelling oxide provides stronger interface against Si dangling bond generation and the decrease in barrier height of both electrons and holes. These results indicate that the SiON tunnelling oxide can be engineered by post deposition annealing for the improvement of metal floating gate memory performance.

Finite-Element Modeling of Retention in Nanocrystal Flash Memories With High- $k$ Interpoly Dielectric Stack

The analysis of retention characteristics is essential for reliability assessment of any type of flash memory. A high- $k$ (HK) material in the Interpoly dielectric (IPD) stack is known to improve the program–erase characteristics and makes the control oxide thicker for better retention time; however, it also brings-in defects along with it, creating undesirable charge loss path that plays a significant role in retention. Accurate modeling of this leakage process is important for optimizing the architecture that is less prone to oxide defects and exhibiting improved charge retention. In this paper, we present a physical model considering all possible charge leakage mechanisms that include inelastic tunneling through multiple traps in addition to direct tunneling (DT). The trap capture process is modeled as an inelastic process from nanocrystal (NC) to trap state, while the trap-to-trap tunneling is calculated by Bardeen’s Transfer Hamiltonian approach. The trap emission process and DT from the spherical NC are modeled by computing the lifetime of quasi-bound states with very small decay widths in the finite-element setup. We show that a single trap model in HK cannot explain the retention characteristics. We propose a new asymmetric IPD structure that show significant improvement in retention time.

(Invited) Floating Gate Type SOI-FinFET Flash Memories with Different Channel Shapes and Interpoly Dielectric Materials

The floating gate (FG)-type silicon-on-insulator (SOI)-FinFET flash memories with triangular-fin (TF) and rectangular-fin (RF) channels and with different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented SOI wafers and orientation dependent wet etching. The electrical characteristics of the fabricated FG-type SOI-FinFET flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 oC have been comparatively investigated. It was experimentally found that the TF channel flash memory with an Al2O3-nitride-oxide (ANO) IPD layer shows a higher P/E speed, a larger memory window, and a lower-voltage operation as compared to the RF channel flash memories with the same ANO IPD layer. Such a high performance of the TF-ANO flash memory is due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF.

(Invited) Floating Gate Type SOI-FinFET Flash Memories with Different Channel Shapes and Interpoly Dielectric Materials

It is well known that the high-k interpoly dielectric (IPD) layer is important for further scaling down of floating gate (FG) type flash memory to improve the gate coupling ratio [1, 2]. Therefore, the high-k Al2O3 layer has already been used as a blocking layer in the charge trapping (CT) type planar and bulk FinFET flash memories [3-5]. However, the high-k Al2O3 has not been used as an IPD layer in the FG type SOI-FinFET flash memories, to our knowledge. In this work, we introduce the high-k Al2O3 into the FG type triangular-fin (TF) and rectangular-fin (RF) channel SOI-FinFET flash memories, and investigate the effects of fin shape and IPD layer material on the electrical characteristics of the fabricated FG type SOI-FinFET flash memories. In the device fabrication, we used (100) and (110) oriented SOI wafers to fabricate TF and RF channels by using the orientation dependent wet etching [6]. A 30-nm-thick n+ poly-Si layer was used as the FG material. Figure 1 shows the cross-sectional STEM images of the fabricated FG-type SOI-FinFET flash memories with different channel shapes and different IPD layers. Figure 2 shows the P/E characteristics of the fabricated 3 kinds of SOI-FinFET flash memories at the same P/E condition. It is clear that a higher P/E speed, a larger memory window and a lower-voltage operation are achieved in the TF-ONA device as compared to the TF-ONO and RF-ONA ones. This result indicates that a high-k Al2O3 layer is very useful for enhancing memory window due to the improved gate coupling, and the TF channel is very suitable for the low-voltage operation thanks to the high-k of Al2O3 and the electric field enhancement at the sharp foot edges of a TF. [1] B. Govoreanu et al., IEDM 2006, p. 479. [2] H.-T. Lue et al., IEDM 2011, p. 203. [3] C. H. Lee et al., IEDM 2003, p. 613. [4] S.-K. Sung et al., VLSI 2006, p.106. [5] B. J. Tang et al., IEDM 2011, p. 219. [6] Y. X. Liu et al., VLSI 2010, p.101. Figure 1

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Floating-gate (FG)-type three-dimensional (3D) fin channel flash memories with triangular fin (TF) and rectangular fin (RF) channels and different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The electrical characteristics of the fabricated FG-type 3D fin channel flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 °C have been comparatively investigated. A higher P/E speed, a larger memory window, and a lower-voltage operation are experimentally obtained in the TF channel flash memories with an Al2O3–nitride–oxide (ANO) IPD layer (TF-ANO) than in the RF channel ones with the same ANO IPD layer (RF-ANO) and the TF channel ones with an oxide–nitride–oxide (ONO) IPD layer (TF-ONO). The larger memory window and lower-voltage operation of TF-ANO flash memories are due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF channels. It was also found that data retention for all fabricated FG-type 3D fin channel flash memories shows a weak dependence on temperature.

Effect of electric field polarity on inter-poly dielectric during cell operation for the retention characteristics

Retention characteristic represents a capability to maintain the storage data and it is related with the reliability of memory device. The retention characteristic is degraded by the leakage of charges from a floating gate to a control gate, and thus the leakage current at low and moderate electric field of inter-poly dielectric (IPD) is one of the important characteristic for floating gate type flash memories. In addition, it is necessary to investigate the effects of the electric field polarity on the electric characteristics of IPD because the electric field polarity is changed as the cell operations such as the programming and erasing. Therefore, in this paper, the variation of the leakage current of IPD at moderate electric field region is measured with varying the previously applied electric field polarity. Based on the result, the effect of sequential change of an applied electric field polarity on the electrical characteristics is analyzed.

Enhancement of electrical characteristics of the coupling ratio and the program/erase operation for NAND flash memories with an asymmetric interpoly-dielectric structure

The electrical characteristics of NAND flash memories with an asymmetric interpoly-dielectric (IPD) structure and a conventional IPD structure were simulated by using a technology computer-aided sentaurus simulation tool to enhance their device performance. The floating gate potential and the on-current level of the NAND memory devices with an asymmetric IPD structure were higher than those with a conventional IPD structure. The maximum electric field formed at the rounding boundary area of the floating gate and the blocking oxide layer in an asymmetric IPD structure was 34% smaller than that in a conventional IPD structure. The trapped charges in the floating gate layer of NAND flash memories with an asymmetric IPD structure increased owing to an increase in the saturation voltage during programming and erasing operation.

Field-dependent charge trapping analysis of ONO inter-poly dielectrics for NAND flash memory applications

The effect of the operation voltage on the leakage current of SiO2/Si3N4/SiO2 (ONO) stack is investigated which is used for the inter-poly dielectric (IPD) of the floating gate (FG) type NAND flash memory. In this work, the field dependent charge trapping mechanism of ONO stack and the effect of the trapped charges on the electrical characteristics are examined. The leakage current density–electric field (J–E) and the capacitance–voltage (C–V) characteristics are measured for various test samples of ONO stack by varying the voltage sweep ranges. The charge trapping/detrapping mechanisms of ONO stack are observed as the range of the applied sweep voltage is increased and then decreased to a given voltage, which is corresponding to the given electric field. The numbers of trapped and detrapped charges are extracted from the difference of J–E curves using the same recursive voltage sweeps and the effects on the electrical characteristics of ONO stack are demonstrated. Moreover, the dominant trapping layer is also investigated by varying the thickness of ONO stack.

Improvement of Bottom Oxide Thickness Scaling of Inter-Poly Dielectric by Floating Gate Top Plasma Nitridation

This letter concerns the electrical properties of floating gate (FG) that has undergone top nitridation, used in NAND flash memory devices As the dimensions are scaled down to 5 nm and beyond, the use of a thinner inter-poly dielectric (IPD) can provide the required gate coupling ratio, leaving more room for the control gate poly filling between the FG. However, the effect of the IPD scaling on data retention capability is the main bottleneck. Two interesting retention failure phenomena are demonstrated in a sample of thin bottom poly oxide (BPO). They are attributed to the enhanced degradation of the electrical field at the top corners of the FG and the potential difference between neighboring FG along the WL direction. These phenomena must be taken into consideration while setting the limits of the BPO in the IPD film scheme. The proposed FG top nitridation overcomes this limitation on the thinning of the bottom oxide improving the data retention characteristics of NAND flash memory devices.

Methodology for improvement of data retention in floating gate flash memory using leakage current estimation

The importance of data retention characteristic is increased as the memory has been scaled down and multi-level programming. The leakage current of the inter-poly dielectric (IPD) at low electric field is related with data retention and the charge of the threshold voltage distribution is increased when the number of storage charges in the floating gate is increased. In order to improve data retention characteristics, the minimization of leakage current variation with respect to the applied electric field on IPD is necessary. In this paper, the effect of the electric potential of IPD on the leakage current is examined and the leakage current at low electric field is predicted. Based on the results, the method for improving the data retention by reducing the leakage current is proposed.

Degradation Mechanisms of the Program Characteristics of 10 nm NAND Flash Memories Due to Cell-to-Cell Interference

The device characteristics of NAND flash memories with gate sizes from 14 to 32 nm were investigated by using a full three-dimensional technology computer-aided design simulator. Simulation results showed that the threshold voltage and the depletion regions of the floating gate (FG) of the 10-nm NAND flash memories increased with decreasing cell size. The electrical potential of the inter-poly-dielectric (IPD) surface and the tunneling layer surface decreased with increasing depletion region of the FG. The program characteristics of the 10-nm NAND flash memories decreased with decreasing electric potential on the IPD surface and the tunneling oxide surface. The electric field between the floating gate of the target cell and that of the neighboring cell increased with decreasing gate size due to a decrease in the distance between the two neighboring cells. The degradation mechanisms for the program characteristics of 10-nm NAND flash memories were clarified by changing the threshold voltage and the voltage shift.

Effect of Intermetal Dielectric Layer On the Interpoly Dielectric Properties of Nonvolatile Memory Devices

This paper describes the influence of water-related species contained in intermetal dielectric layer on the interpoly dielectric properties of nonvolatile memory devices. P-TEOS layer used as an intermetal dielectric enhances degradation of interpoly dielectric of nonvolatile memory devices due to the water-related components contained in the layer.

Read and Pass Disturbance in the Programmed States of Floating Gate Flash Memory Cells With High-&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\kappa$&lt;/tex&gt;&lt;/formula&gt; Interpoly Gate Dielectric Stacks

High-κ stacks have been used in the 20-nm generation of floating gate (FG) flash memory cells as the interpoly dielectric (IPD). However, electron trapping in high-κ materials remains a major concern for the further development of FG technology. For conventional FG cells, read/pass disturbance in the erased states is a major issue. In this paper, for the first time, it is observed that electron trapping/detrapping in the high-κ IPD layers can cause severe abnormal read/pass disturbances in the programmed states. Extensive evidence shows that this instability in programmed states originates from several competing mechanisms, including the redistribution of electron trapping between the IPD and FG and the electron discharging from FG/IPD into the control gate. This issue should be addressed in the development of future generations of FG Flash technology with higher-κ IPD materials.

High-k dielectrics for hybrid floating gate memory applications

ABSTRACTWe report on the materials issues involved in the hybrid floating gate (HFG) device fabrication, where the interpoly dielectric is replaced by an intermetal dielectric (IMD). Indeed, in HFG the dielectric is inserted in between two metal layers in a metal\dielectric\metal stack. The materials of choice were TiN as the metal layer and Al2O3 and HfO2 (and their combination) as IMD. The program/erase performance is discussed based on the dielectric constant and crystallinity of the IMD and the metal-IMD interface characteristics.

Improved Performance of Yttrium-Doped $\hbox{Al}_{2}\hbox{O}_{3}$ as Inter-Poly Dielectric for Flash-Memory Applications

Yttrium-doped Al2O3 (YxAIyO) with different yttrium contents prepared by co-sputtering method is investigated as the inter-poly dielectric (IPD) for flash memory applications. A poor SiO2-like interlayer formed at the IPD/Si interface is confirmed by X-ray photoelectron spectroscopy, and can be sup pressed by Y doping through the transformation of silica into silicate. Compared with Al2O3 and Y2O3 films, the optimized YxAIyO film shows lower interface-state density, lower bulk charge-trapping density, higher dielectric constant, and smaller gate leakage, due to the suppressed interlayer and good thermal property ascribed to appropriate Y and Al contents in the film. Therefore, the optimized YxAIyO film is a promising candidate as the IPD for flash memory.

Leakage Current Reduction Mechanism of Oxide–Nitride–Oxide Inter-Poly Dielectrics through the Post Plasma Oxidation Treatment

High quality oxide–nitride–oxide (ONO) inter-poly dielectrics were successfully fabricated by the optimized plasma oxidation without H2. The bottom low pressure chemical vapor deposition (LPCVD) oxides treated by the conventional N2O annealing step were subjected to the post deposition process using a plasma treatment. This process reduces both the leakage current and the stress-induced leakage current (SILC), while no thickness increase of the bottom LPCVD oxides was observed due to the plasma treatment. Based on the photo electron injection technique, it is found that the O2 plasma oxidation method significantly reduces the defect centers located at 1.67 nm away from the bottom oxide/floating gate interface.

Leakage Current Reduction Mechanism of Oxide–Nitride–Oxide Inter-Poly Dielectrics through the Post Plasma Oxidation Treatment

Leakage Current Reduction Mechanism of Oxide–Nitride–Oxide Inter-Poly Dielectrics through the Post Plasma Oxidation Treatment