Intermediate Voltage Level Research Articles

A Hybrid Boost Converter With Standard CMOS-Compatible 14-V Output for an Ultrasound Imaging System

This paper presents a hybrid boost converter that achieves a 14V regulated output and multiple intermediate voltage levels in standard CMOS, targeted for an ultrasound imaging system (UIS) application. The intermediate voltage levels are regulated at 3.5V, 7V, 10.5V from a 1.5V input. For ease of integration with existing intellectual properties (IPs) and for digital back end (DBE) integration flexibility, all switch stresses are kept within 3.5V for standard CMOS compatibility. Implemented in 180nm 1P6M standard CMOS process, the hybrid boost converter achieves efficiency of 78%.

Floating-capacitor based inverter for open-ended winding induction motor drive with fault-tolerance

ABSTRACT Floating-capacitor-based nine-level inverter topology for open-ended winding induction motor (OWIM) drive is presented in this paper. The proposed multilevel inverter topology (PMLIT) essentially consists of four three-phase two-level voltage source inverters (VSI), three isolated DC sources and a floating-capacitor (FC). Out of four inverters, three inverters are fed from DC sources, and the fourth inverter is connected with the FC. The advantage of the PMLIT is that the maximum output voltage will be twice the source voltage with nine levels across each phase winding. The PMLIT employs least number of components which makes the inverter cost-effective and has lowered control complexity. The PMLIT can deliver seven, five or three-level output voltage with a decrease in modulation index. Conventional sinusoidal pulse-width modulation (PWM) techniques can be employed to generate switch-gate pulses. The intermediate-voltage levels are realised by proper charging and discharging of the FC. The performance of the PMLIT under possible switch faults is investigated, and modified switching logics are proposed to deliver a balanced supply for the OWIM drive in post-fault operation. Simulations are performed in the MATLAB/Simulink environment, and an experimental setup is designed to validate the simulations, and the results are presented.

A single source based multilevel boost inverter with reduced peak standing voltage for renewable energy and EV applications

This paper introduces a nine-level (9L) boost inverter topology with reduced peak standing voltage (PSV) across the switches. The topology consists of a single DC source, two capacitors, a switched-capacitor (SC) and a floating capacitor (FC), and eleven power electronics switches. Due to the inherent voltage boosting capability, the proposed inverter is suitable for low-scale voltage applications such as photovoltaic (PV), fuel cell, and single battery-operated electric vehicles (EVs). A sensorless approach is introduced to stabilize the requisite voltage across the FC for any changes in input voltage. A generalized topology is also presented to obtain n-times voltage gain along with a high number of intermediate voltage levels. The PSV of the switches does not exceed the value of the input DC voltage, irrespective of increase in voltage gain. The results show that the voltage across the FC is unaffected by stepped variations in the modulation indices, power factor of load, pulse width modulation (PWM) techniques, and the operating frequency. Furthermore, when the input voltage changes, the voltage across the FC is automatically adjusted to a new requisite value within 0.6s. The topology works for a wide range of modulation indices (0–1) and loads. A thorough analysis is done to show that the proposed topology is superior to recent topologies.

A switched-capacitor and floating-capacitor (SCFC) based multilevel boost inverter with a single DC power supply and sensor-less voltage balancing method

This paper introduces a nine-level (9L) boost inverter with reduced number of components. The proposed 9L topology comprises a single DC source, eight switches, and two capacitors, namely a switched-capacitor (SC) and a floating capacitor (FC). The topology consists of two converter units: the SC unit and the FC unit. Both units are cascaded to achieve nine voltage levels with a voltage gain of 2. The inherent voltage boosting capability of the proposed topology makes it suitable for low-scale voltage applications like photovoltaics (PV) and electric vehicles (EVs). A sensorless method is introduced to stabilize the requisite voltage across the FC for any undesirable changes in input voltage. The performance reveals that the voltage across the FC does not deviate with changes in the modulation index, power factor of load, pulse width modulation (PWM) methods, or the operating frequency. And, when the input voltage fluctuates, the voltage across the FC is naturally adjusted to the new desired value within 0.6 s. The topology operates over a wide range of modulation indices (0 to 1) and different types of loads. A generalized topology is also developed to get a high output voltage along with a higher number of intermediate voltage levels. A comprehensive analysis is presented to show the effectiveness of the proposed topology over the recent topologies.

Seven-Level Packed U-Cell (PUC) Converter With Natural Balancing of Capacitor Voltages

A seven-level packed U-cell inverter is presented in this article. The converter uses a single dc source and two floating capacitors, whose voltages are balanced in open loop, to produce multilevel output voltage. Peak magnitude of the output phase voltage is equal to the magnitude of dc source. Voltages across floating capacitors add intermediate voltage-levels by establishing an asymmetric ratio (with respect to the available dc voltage in the circuit). The average energy exchange (when the network is in steady state) of the capacitors with the rest of the inverter circuit will be zero. This helps the capacitors to maintain desired voltages and thus create intermediate levels of steady dc voltages. Performance of the converter is validated in simulation by MATLAB/Simulink and testing of the converter is done for resistive as well as inductive loads. Experimental verification of the converter is carried out on a laboratory prototype and the obtained results match well with the simulation.

Development of a Modular Controller to Minimize Current Ripple in Low Inductance Coreless Permanent Magnet Motor

In this paper, a development of a modular controller to minimize current ripple in a low inductance coreless permanent magnet synchronous motor (CPMSM) is described. Based on individual modules, the controller uses a 60 degree commutation scheme instead of the conventional 120 degree. The neutral point of the motor’s windings is connected to an intermediate voltage level provided by a capacitor bank relative to the DC power bus. This feature allows the utilization of a single current sensing point that is used to regulate the motor’s torque by hysteretic current level control. With this simplification of the control strategy it was possible to use a single Programable Logic Device (PLD) to implement all the processing in the controller. The controller was built and tested, and the results showed efficient and smooth operation of the motor.
 Keywords: Current ripple, Permanent magnet motor, Low inductance

Novel Step-Down DC–DC Converters Based on the Inductor–Diode and Inductor–Capacitor–Diode Structures in a Two-Stage Buck Converter

This paper explores and presents the application of the Inductor–Diode and Inductor-Capacitor-Diode structures in a DC–DC step-down configuration for systems that require voltage adjustments. DC micro/picogrids are becoming more popular nowadays and the study of power electronics converters to supply the load demand in different voltage levels is required. Multiple strategies to step-down voltages are proposed based on different approaches, e.g., high-frequency transformer and voltage multiplier/divider cells. The key question that motivates the research is the investigation of the aforementioned Inductor–Diode and Inductor–Capacitor–Diode, current multiplier/divider cells, in a step-down application. The two-stage buck converter is used as a study case to achieve the output voltage required. To extend the intermediate voltage level flexibility in the two-stage buck converter, a second switch was implemented replacing a diode, which gives an extra degree-of-freedom for the topology. Based on this modification, three regions of operation are theoretically defined, depending on the operational duty cycles δ2 and δ1 of switches S2 and S1. The intermediate and output voltage levels are defined based on the choice of the region of operation and are mapped herein, summarizing the possible voltage levels achieved by each configuration. The paper presents the theoretical analysis, simulation, implementation and experimental validation of a converter with the following specifications; 48 V/12 V input-to-output voltage, different intermediate voltage levels, 100 W power rating, and switching frequency of 300 kHz. Comparisons between mathematical, simulation, and experimental results are made with the objective of validating the statements herein introduced.

Generalized Topology of a Hybrid Switched- Capacitor Multilevel Inverter for High- Frequency AC Power Distribution

The generalized topology of a hybrid switched-capacitor multilevel inverter (SCMLI) for high-frequency ac (HFAC) power distribution system is presented. By employing the series–parallel conversion technique, the proposed SCMLI can achieve self-balancing of capacitor voltages and voltage step-up with arbitrary numbers of SC cells. The output power quality is improved by the intermediate voltage levels provided by the bidirectional switched converter connected to the dc source string. Besides, several active switches can be replaced with diodes if the large phase difference between output current and voltage is not required. Since the voltage ripple magnitude of the SC units is inversely proportional to the fundamental output frequency, the proposed SCMLI is more preferable for HFac applications. This paper elucidates the working principle of the proposed inverter with the detailed circuit and switching states’ description under staircase modulation. The mathematical analyses associated with the capacitor voltage ripples, sizing, and power loss are also provided. A 19-level MLI with a voltage gain of three was realized by cooperating two SC units with a voltage source string consisting of three symmetric dc sources. The operation and performance of the proposed inverter have been validated by the simulation and experiment on the inverter. The results showed that the inverter performed better at HFac condition and the power quality was satisfactory with the 19-level staircase output modulated at the fundamental frequency.

Design and Implementation of Transformer-Based Multilevel Inverter Topology With Reduced Components

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included.

Low power SAR ADC switching without the need of precise second reference

In this paper a simple method to reduce the switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register analog-to-digital converters (ADCs) is described. The method is based on the well-known monotonic switching procedure and the use of one intermediate voltage level during switching. Unlike most recently published switching methods the proposed method does not require the intermediate voltage to be accurate. The implementation of digital control and an intermediate voltage-level generator is considered. To evaluate the reduction in switching energy compared to the conventional monotonic switching procedure, the behavioral model of a 10-bit ADC was examined. The additional digital logic, voltage generator, and capacitive DAC were modeled at a transistor level using a 65 nm STM design kit. Simulation results and the subsequent power efficiency gains are presented.

A computational study of the effects of DC electric fields on non-premixed counterflow methane-air flames

Two-dimensional axisymmetric simulations for counterflow non-premixed methane-air flames were undertaken as an attempt to reproduce the experimentally observed electro-hydrodynamic effect, also known as the ionic wind effect, on flames. Incompressible fluid dynamic solver was implemented with a skeletal chemical kinetic mechanism and transport property evaluations. The simulation successfully reproduced the key characteristics of the flames subjected to DC bias voltages at different intensity and polarity. Most notably, the simulation predicted the flame positions and showed good qualitative agreement with experimental data for the current–voltage curve. The flame response to the electric field with positive and negative polarity exhibited qualitatively different characteristics. In the negative polarity of the configuration considered, a non-monotonic variation of the current with the voltage was observed, along with the existence of an unstable regime at an intermediate voltage level. With positive polarity, a typical monotonic current–voltage curve was obtained. This behavior was attributed to the asymmetry in the distribution of the positive and negative ions resulting from ionization processes. The present study demonstrated that the mathematical and computational models for the ion chemistry, transport, and fluid dynamics were able to describe the key processes responsible for the flame-electric field interaction.

Overstress-Free 4 × VDD Switch in a Generic Logic Process Supporting High and Low Voltage Modes

A four-times-VDD switch that supports high and low voltage mode operations is demonstrated in a generic 65 nm logic process. The proposed switch shows the robust operation for supply voltages ranging from VDD to 4 × VDD. A cascaded voltage switch and a voltage doubler based charge pump generate the intermediate supply voltage levels required for the proposed high voltage switch. All the high voltage circuits developed in this work can be implemented using standard logic transistors without being subject to any voltage overstress.

On the Appropriate Handling of Metastable Voltages in FPGAs

The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

Quasi Two-Level Operation of Modular Multilevel Converter for Use in a High-Power DC Transformer With DC Fault Isolation Capability

DC fault protection is one challenge impeding the development of multiterminal dc grids. The absence of manufacturing and operational standards has led to many point-to-point HVDC links built at different voltage levels, which creates another challenge. Therefore, the issues of voltage matching and dc fault isolation are undergoing extensive research and are addressed in this paper. A quasi two-level operating mode of the modular multilevel converter is proposed, where the converter generates a square wave with controllable dv/dt by employing the cell voltages to create transient intermediate voltage levels. Cell capacitance requirements diminish and the footprint of the converter is reduced. The common-mode dc component in the arm currents is not present in the proposed operating mode. The converter is proposed as the core of a dc to dc transformer, where two converters operating in the proposed mode are coupled by an ac transformer for voltage matching and galvanic isolation. The proposed dc transformer is shown to be suitable for high-voltage high-power applications due to the low-switching frequency, high efficiency, modularity, and reliability. The dc transformer facilitates dc voltage regulation and near instant isolation of dc faults within its protection zone. Analysis and simulations confirm these capabilities in a system-oriented approach.

Maximizing Spontaneous Jet Density and Nanofiber Quality in Unconfined Electrospinning: The Role of Interjet Interactions

The interplay between an applied electric field and fluid properties was studied for a polymer solution forming high quality nanofibers via electrospinning. Unconfined electrospinning—in which a fluid thin film or bath exposed to an electric field spontaneously generates many parallel fiber-forming jets—is a practical approach to achieving a high fabrication rate of quality nanofibers as compared to traditional single-needle electrospinning. The density of fiber-forming jets is controlled by surface tension effects at the lowest applied voltages but by jet-to-jet interactions as the voltage amplitude is increased, resulting in an intermediate operating voltage level at which jet number is maximized. This general result is applicable to electric-field-driven fluid instabilities in a wide range of systems. The optimal voltage level occurs when interjet interactions begin to solely determine the characteristic jet spacing, and in this regime, compression of the cone-jet slightly chokes the feed rate, allowing high quality fibers to be formed when the maximum number of jets is present. Spontaneous jet deflection (here, from a linearly arranged source) results in a two-dimensional array at the collector which both minimizes interjet interactions and preserves fiber quality.

Optimal Low-Power Piezoelectric Actuator Control With Charge Recovery for a Microrobotic Leg

This paper describes an efficient control strategy for a piezoelectric microactuator using charge recovery. For piezoelectric actuators, as well as other actuators that behave primarily as capacitive loads, energy consumption can be reduced by minimizing the number of times an actuator is charged and by recovering stored energy when it is turned off. An integer programming-based algorithm is used to drive microrobotic legs powered by piezoelectric actuators to a specified angle in a specified time using minimum energy. Partial charge recovery is incorporated; this allows the use of a more flexible controller than a pure on-off controller, with two or more intermediate voltage levels between the minimum and maximum voltages available to improve positioning accuracy. Simulated and experimental tests show that a prototype piezoelectric robotic leg joint achieved controlled movements with one third of the energy consumed by a pure on-off controller.

Charge pumping and DCIV currents in SOI FinFETs

Charge pumping (ACIV) and direct current–voltage (DCIV) measurements were performed on standard floating-body n-channel FinFETs. The resulting recombination currents are monitored directly at the drain and source contacts, and are found to depend strongly on frequency, gate voltage, and FinFET geometry. The DCIV current reaches a maximum when the body potential transitions from accumulation to inversion in response to the applied gate bias and the body-to-source and body-to-drain diodes become forward biased. The ACIV current is dominated by contributions from interface traps when the surface potential is swept from accumulation to inversion during the gate pulse. It is sensitive to recombination currents at the body-to-source and body-to-drain diodes at intermediate voltage levels. At the highest applied gate voltages, band-to-band tunneling is also observed. We demonstrate that the change in ACIV current with frequency before and after electrical stress allows charge-pumping estimates of stress-induced interface trap densities in standard SOI FinFETs without body contacts.

An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O

This paper describes a new technique for the design of 3-terminal regulators in which the output voltage level can be adjusted without additional terminals or extra off-chip components. This circuit restricts the increase in the number of terminal pins by using a pin as both a voltage supply output and a voltage setup input. The voltage setup information is introduced using a serial control signal from outside the chip. Using the intermediate voltage level between the supply voltage and the regulator output, the adjustment data in the internal nonvolatile memory are safely updated without noise disturbance. To input the setup information into the chip in a stable manner, we developed a new 1-wire serial interface which combines key pattern matching and burst signal detection. To ensure high reliability, we suggested a quantitative method for evaluating the influence of noise in our new interface using a simple model with superimposed random noise. Circuits additional to those for a conventional 3-terminal regulator, include a 1-wire serial communication circuit, a low-capacity non-volatile memory, and a digital to analog (D/A) converter. A test chip was developed using 0.35µm standard CMOS process, and there was almost no overhead to the conventional 3-terminal regulator in both chip area and power dissipation. In an on-board test with the test chip, we confirmed successful output voltage adjustment from 1.0V to 2.7V with approximately 6.5mV precision.

Novel Modulator Topology for Corona Plasma Generation

Gas cleaning using plasma technology is slowly introduced into industry nowadays. Several challenges still have to be overcome: increasing the scale, safety, life-time and reducing costs. In 2006 we demonstrated a 20 kW nanosecond pulsed corona system. The electrical e‐ciency was > 90%. O-radical yields were found to be very high (3{7 mole/kWh). However, to be competitive, high costs of the pulsed power technology are still a major hurdle. Here we present a novel modulator for e‐cient generation of large volume corona plasma. Only a small amount of expensive high-voltage components are required. Switching is done at an intermediate voltage level of 1 kV with standard thyristors. At the high-voltage side, only a diode and a pulse transformer are needed. The estimated costs are about 5 kEuro/kW, whereas for state-of-the-art pulsed power technology these costs usually are about 20{30 kEuro/kW. Detailed investigations on the modulator and a wire-plate corona reactor will be presented. Modulator parameters have been varied systematically as well as reactor parameters (number of electrodes, electrode{plate distance). The O-radical yield was determined from the measured ozone concentrations at the exhaust of the reactor. With a detailed kinetic model, ozone concentrations could be calculated back to the initial O*-yields. The following conclusions will be discussed: for all parameters, an electrical e‐ciency of > 90% could be obtained. With fast imaging, the average streamer width was found to be » 737 „m and an estimate for the plasma volume was made. The obtained yields of O-radicals (1{4 mole/kWh) are excellent. The conditions to obtain high yields will be discussed.

AC/DC/Pulsed-Power Modulator for Corona-Plasma Generation

Gas-cleaning techniques using nonthermal plasma are slowly introduced into industry nowadays. In this paper, we present a novel power modulator for the efficient generation of large-volume corona plasma. No expensive high-voltage components are required. Switching is done at an intermediate voltage level of 1 kV with standard thyristors. Detailed investigations on the modulator and a wire-plate corona reactor will be presented. In a systematic way, modulator parameters have been varied. Furthermore, reactor parameters, such as the number of electrodes and the electrode-plate distance, have been varied systematically. The yield of O radicals was determined from the measured ozone concentrations at the exhaust of the reactor.