Abstract
The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.
Highlights
Asynchronous circuits are receiving more and more interest since they provide a natural way of handling the signicant process, voltage and temperature (PVT) variations seen with modern ASIC technologies and they lend themselves to lowpower design
A value safe solution to handling metastability without upsets in asynchronous circuits can be implemented in the Field Programmable Gate Array (FPGA) prototype
In the context of value-safe designs, the conversion from intermediate voltage level to a late transition is crucial for reliable handling of metastability
Summary
Asynchronous circuits are receiving more and more interest since they provide a natural way of handling the signicant process, voltage and temperature (PVT) variations seen with modern ASIC technologies and they lend themselves to lowpower design Their operation is not based on a rigid global clock but rather on local handshakes, which, in an abstract sense, form control loops for the °ow control. The mission is to safely turn an intermediate voltage level that usually results from metastability into a well-dened HI or LO level by means of high- or low-threshold bu®ers or a Schmitt-trigger These are not available in FPGAs. In this paper, we will analyze this conversion in more detail, investigate which of these measures is required when and we will propose a safe and systematic way of implementing the required functions in an FPGA. A value safe solution to handling metastability without upsets in asynchronous circuits can be implemented in the FPGA prototype
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