Interface Trap Density Research Articles

Charge transfer rates and electron trapping at buried interfaces of perovskite solar cells

<h2>Summary</h2> Identification of electronic processes at buried interfaces of charge-selective contacts is crucial for photovoltaic and photocatalysis research. Here, transient surface photovoltage (SPV) is used to study the passivation of different hole-selective carbazole-based SAMs. It is shown that transient SPV and transient photoluminescence provide complementary information on charge transfer kinetics and trapping/de-trapping mechanisms, and that trap-assisted non-radiative recombination losses originate from electron trapping at the SAM-modified ITO/perovskite interface. The hole transfer rates and the density of interface electron traps, obtained by fitting SPV transients with a minimalistic kinetic model, depended strongly on the SAM's chemical structure, and densities of interface traps as low as 10⁹ cm⁻², on par with highly passivated c-Si surfaces, were reached for Me-4PACz, previously used in record perovskite/silicon tandem solar cells. The extracted hole transfer rate constants and interface trap densities correlated well with the corresponding fill factors and open-circuit voltages of high-efficiency solar cells.

Ultra‐thin Body Buried In 0.35 Ga 0.65 As Channel MOSFETs with Extremely Low Off‐current on Si Substrates

In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al2O3/InP under different annealing conditions. A minimum interface trap density of 3×1011cm-2eV-1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al2O3/InP MOS gate stack, we fabricated ultra-thin body buried In0.35Ga0.65As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200nm gate length device with extremely low off-current of 0.6nA/μm, and on-off ratio of 3.3×105, is demonstrated by employing buried low indium (In0.35Ga0.65As) channel with InP barrier/spacer device structure, giving strong potential for future high-performance and low-power applications.

Comprehensive passivation strategy for achieving inverted perovskite solar cells with efficiency exceeding 23% by trap passivation and ion constraint

Both surface and bottom of perovskite film suffer from high density of trap-assisted recombination losses in perovskite solar cells; therefore, an effective method suitable for minimizing the trap density of perovskite solar cells (PSCs) both at perovskite/hole transport layer interfaces and perovskite/electron transport layer is urgently required. Herein, a comprehensive passivation strategy for achieving high-performance inverted PSCs was demonstrated. The study shows that the inverted PSCs possess dual increase of efficiency by passivation of the surface and bottom, as well as grain boundaries of perovskite active layer. The unencapsulated PSCs from comprehensive passivation strategy achieved the highest power conversion efficiency of 23.33% with remarkable long-term stability when exposed to illumination and humidity. In addition, this work provides an original method to analyze the distribution of the interfacial trap density and ions accumulation density by using the combination process of capacitance–voltage (C-V) and drive-level capacitance profiling (DLCP) measurements, providing the direct evidence for reducing of trap density and inhibiting of ion accumulation at two interfaces of PSCs.

(Invited) Fabrication and Characterization of Ge-Based MIS Structures

Germanium (Ge) is a very attractive channel material for future high-performance metal-insulator-semiconductor (MIS) devices because it exhibits much higher low-field electron (two times higher) and hole (four times higher) mobilities than Si. In addition, the smaller band gap of Ge than that of Si should allow the further reduction of power consumption in advanced integrated circuits and the lower melting point of Ge than that of Si also enables Ge-based device integration at low processing temperatures. However, until the early years of the 2000s, the reported electrical properties of high-k/Ge interfaces had been so poor that one of the critical issues in establishing Ge-based MIS technology was the effective passivation of Ge surfaces by dielectrics with superior interface properties. Although the quality of the Ge-MIS structure has been remarkably improved in the past decade, the relationship between the processing methods and the quality has not been discussed precisely.In this paper, we report on the fabrication of Ge MIS structures with various high-k dielectric materials and interlayer materials through various methods. We also introduce the convenient method to characterize the interface trap densities (Dit's) of the MIS capacitors by spectroscopic measurement of the interface trap density in an insulator/Ge interface at room temperature [1]. The effects of the insertion of interlayers into the interface of high-k insulator/Ge and the application of heat treatment to the Ge MIS structures will be also presented.For instance, the Dit of Ta2O5/GeNx/Ge fabricated by electron-cyclotron-resonance (ECR) plasma nitridation and sputtering was estimated to be 4×1011 cm-2 · eV-1 [2], that of Si3N4/GeNx/Ge by ECR plasma nitridation to be 1×1011 cm-2 · eV-1 [3-6], and that of Al2O3/GeO2/Ge by ECR plasma oxidation and sputtering to be 4.5×1010 cm-2 · eV-1 [7-9]. These results have summarized that the adequate surface preparations of the interfaces and films by the ECR plasma process with low energy plasma irradiation have been effective to realize the low Dit of MIS structures with GeO2 and/or GeNx.These results have expanded to another MIS structures fabricated by more conventional film formation technique such as the atomic layer deposition (ALD) and the radio frequency (RF) magnetron sputtering. The Dit of Al2O3/Al germanate/Ge by ALD with trimethylaluminum (TMA) and microwave-generated atomic oxygen was estimated to be 2×1011cm-2 · eV-1 [10], and that of HfO2/Ge by RF magnetron sputtering to be 5.9×1011 cm-2 · eV-1. These results have summarized that the heat treatment after the fabrication of MIS strucures have affected interface properties of germanate/Ge and oxide/Ge.Although the mechanism by which the process conditions act on the interface state is now under estimation, it has been speculated that the fabrication method, the insertion of the interlayers, and the application of heat treatment have a great influence on the interface characteristics. The structures and the fabrication method of various MIS will be discussed.Part of this work was carried out under the Cooperative Research Project Program of the Research Institute of Electrical Communication, Tohoku University.

Porous p–n junction-induced memory characteristics in low-voltage organic memory transistors

Low-voltage organic memory transistors (LOMTs) as data storage units are crucial for the advancements of future flexible electronics. However, charge storage mechanism remains a great challenge. In this work, we used poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno(3,2-b)thiophene) (PBTTT-C14) as the active layer and incorporated poly(methyl methacrylate) (PMMA) with the PBTTT-C14 through a simple blending process to fabricate LOMTs with porous structure. The function of the porous structure was to improve the carrier traps, which can effectively capture the holes at the charge trapping regions during the programming process. A maximum threshold voltage shift of 1.01 V was achieved when the weight ratio of PBTTT-C14 and PMMA is 7:3, and the LOMTs were operated under the programming process of −4 V/1 s. Impedance-admittance analyses were used to investigate the interfacial trap density of charge trapping regions, which is a supporter of the programming capability of LOMTs. An ultrathin dioctyl perylene tetracarboxylic diimide film was deposited on the active layer with porous structure in LOMTs. This film can increase the carriers’ erasing capability. A wide memory window of 1.64 V was obtained in LOMTs when the devices are operated under the erasing process of bias pulse of 3 V/1 s with the assistance of 2.5 mW cm−2 light irradiation. This study facilitates the development of high-performance LOMT device in fresh-type memory.

High-Performance and Radiation-Hardened Solution-Processed ZrLaO Gate Dielectrics for Large-Area Applications.

Radiation hardness is important for electronics operating in harsh radiation environments such as outer space and nuclear energy industries. In this work, radiation-hardened solution-processed ZrLaO thin films are demonstrated. The radiation effects on solution-processed ZrLaO thin films and InOx/ZrLaO thin-film transistors (TFTs) were systemically investigated. The Zr0.9La0.1Oy thin films demonstrated excellent radiation hardness with negligible roughness, composition, electrical property, and bias-stress stability degradation after radiation exposure. The metal-oxide-semiconductor capacitors (MOSCAPs) based on Zr0.9La0.1Oy gate dielectrics exhibited an ultralow flat band-voltage (VFB) sensitivity of 0.11 mV/krad and 0.19 mV/krad under low dose and high dose gamma irradiation conditions, respectively. The low dose condition had a 103 krad (SiO2) total dose and a 0.12 rad/s low dose rate, whereas the high dose condition had a 580 krad total dose and a 278 rad/s high dose rate. Furthermore, InOx/Zr0.9La0.1Oy thin-film transistors (TFTs) exhibited a large Ion/Ioff of 2 × 106, a small subthreshold swing (SS) of 0.11 V/dec, a small interface trap density (Dit) of 1 × 1012 cm-2, and a 0.16 V threshold shift (ΔVTH) under 3600 s positive bias-stress (PBS). InOx/Zr0.9La0.1Oy TFT-based resistor-loaded inverters demonstrated complete swing behavior, a static output gain of 13.3 under 4 V VDD, and an ∼9% radiation-induced degradation. Through separate investigation of the radiation-induced degradation on the semiconductor layer and dielectric layer of TFTs, it was found that radiation exposure mainly generated oxygen vacancies (Vo) and increased electron concentration among gate oxide. Nevertheless, the radiation-induced TFT instability was mainly related to the semiconductor layer degradation, which could be possibly suppressed by back-channel passivation. The demonstrated results indicate that solution-processed ZrLaO is a high-potential candidate for large-area electronics and circuits applied in harsh radiation environments. In addition, the detailed investigation of radiation-induced degradation on solution-processed high-k dielectrics in this work provided clear inspiration for developing novel flexible rad-hard dielectrics.

Enhanced reliability and uniformity for Ge pMOSFET with low temperature supercritical fluid treatment

Significant improvement on uniformity and reliability characteristics in Ge pMOSFET are achieved with a novel low temperature supercritical phase CO 2 fluid treatment with H 2 O cosolvent. Devices with the proposed treatment also exhibit a lower subthreshold swing, a higher on/off current ratio, and a lower interface trap density. The improvement can be attributed to the reduction of oxygen vacancy and low oxidation states in the interfacial layer (IL), and the quality enhancement on both IL and high-k gate stack. • A low temperature supercritical phase CO 2 fluid with H 2 O cosolvent treatment was proposed. • The uniformity and reliability characteristics of p-channel Ge transistor can be improved. • Improvement can be attributed to reduction of oxygen vacancy and low oxidation states. • The process is promising for the mass production of chip on large-size wafers.

Effects of pre- and post-microwave annealing treatments on pGe MOS device

Effects of pre- and post- microwave annealing (MWA) treatment on electrical characteristics of p-type Ge substrate (pGe) metal-oxide-semiconductor (MOS) devices were investigated in this work. The physical mechanism was studied with an X-ray photoelectron spectroscopy analysis. The pre-MWA treatment, which is similar to conventional post oxidation annealing on interfacial layer (IL), can passivate the oxygen vacancy by chemisorbed oxygen. The excess chemisorbed oxygen atoms may be left at the interface between IL and high-k, which would induce more interface/oxide traps and form more unstable components in IL. The chemisorbed oxygen can be replaced with well-bonded oxygen by using a post-MWA treatment on high-k dielectric , instead of a conventional post deposition annealing. As a result, pGe MOS device with a double-MWA treatment exhibits low equivalent oxide thickness value (~0.65 nm), small frequency dispersion, low interface trap density, and excellent reliability characteristics without increasing the leakage current. The oxygen vacancy passivation and chemisorbed oxygen suppression with a double-MWA treatment are crucial for high performance Ge MOS device and monolithic 3D IC applications. • The effect of pre- and post- microwave annealing (MWA) treatment is compared. • Oxygen vacancy can be passivated by chemisorbed oxygen in pre MWA. • Excess chemisorbed oxygen can be replaced with well-bonded oxygen by post MWA. • A p-type Ge substrate capacitor can be improved by double MWA.

Inorganic Lead-Free B-γ-CsSnI3 Perovskite Solar Cells Using Diverse Electron-Transporting Materials: A Simulation Study.

B-γ-CsSnI3 perovskite solar cells (PSCs) are simulated employing diverse electron-transporting layers (ETLs, including TiO2, ZnO, SnO2, GaN, C60, and PCBM), and a comparative study has been made. Both regular and inverted planar structures are simulated. Effects of the thickness of absorbers and ETLs, doping of ETLs, and interface trap states on the photovoltaic performance are studied to optimize the device structures. The regular structures have larger short-circuit current density (Jsc) than the inverted structures, but the inverted structures have larger fill factor (FF). All of the simulated optimal PSCs have similar open-circuit voltages (Voc) of ∼0.96 V. The PSCs with TiO2 ETLs have the best photovoltaic performance, and the optimum structure exhibits the highest efficiency of 20.2% with a Voc of 0.97 V, Jsc of 29.67 mA/cm2, and FF of 0.70. The optimal PSCs with ZnO, GaN, C60, and PCBM ETLs exhibit efficiencies of 17.88, 18.09, 16.71, and 16.59%, respectively. The optimal PSC with SnO2 ETL exhibits the lowest efficiency of 15.5% in all of the simulated PSCs due to its cliff-like band offset at the SnO2/CsSnI3 interface. Furthermore, the increase of interface trap density and capture cross section is found to reduce the photovoltaic performance of PSCs. This work contributes to designing and fabricating CsSnI3 PSCs.

Study of interface trap density of AlOxNy/GaN MOS structures

GaN metal–oxide–semiconductor structures were fabricated by atomic layer deposition of aluminum oxynitride thin films on bulk GaN substrates with c-, a-, and m-plane surfaces. Capacitance–voltage measurements ranging from 5 kHz to 1 MHz were conducted at room temperature. The interface trap number density (Nit) and interface trap level density (Dit) of the devices were extracted. A Nit of less than 2 × 1011 cm−2 and a Dit of less than 2 × 1011 cm−2 eV−1 were obtained on the a-plane and m-plane samples. Nit and Dit values were larger for c-plane samples, with the largest interface trap density observed on the c-plane sample with the highest dislocation density. The different Nit and Dit values can be attributed to different dislocation densities and dangling bond densities among different samples.

Comparative Study on the Separate Extraction of Interface and Bulk Trap Densities in Indium Gallium Zinc Oxide Thin-Film Transistors Using Capacitance–Voltage and Current–Voltage Characteristics

The interface and bulk trap densities were separately extracted from self-aligned top-gate (SA-TG) coplanar indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) using the low-frequency capacitance–voltage (C–V) characteristics and space-charge-limited current (SCLC) under the flat-band condition. In the method based on the C–V curve, the energy distribution of the interface trap density was extracted using the low-frequency C–V characteristics, and that of the bulk trap density was obtained by subtracting the density of interface trap states from the total subgap density of states (DOS) at each energy level. In the SCLC-based method, the energy distribution of the bulk trap density was extracted using the SCLC under the flat-band condition at high drain-to-source voltages, and that of the interface trap density was obtained by subtracting the density of bulk trap components from the total subgap DOS at each energy level. In our experiments, the two characterization techniques provided very similar interface and bulk trap densities and showed that approximately 60% of the subgap states originate from the IGZO/SiO2 interface at the conduction band edge in the fabricated IGZO TFTs, although the two characterization techniques are based on different measurement data. The results of this study confirm the validity of the characterization techniques proposed to separately extract the interface and bulk trap densities in IGZO TFTs. Furthermore, these results show that it is important to reduce the density of interface trap states to improve the electrical performance and stability of fabricated SA-TG coplanar IGZO TFTs.

Alternatives to aluminum gates for silicon quantum devices: Defects and strain

Gate-defined quantum dots benefit from the use of small grain size metals for gate materials because they aid in shrinking the device dimensions. However, it is not clear what differences arise with respect to process-induced defect densities and inhomogeneous strain. Here, we present measurements of fixed charge, Qf; interface trap density, Dit; the intrinsic film stress, σ; and the coefficient of thermal expansion, α, as a function of forming gas anneal temperature for Al, Ti/Pd, and Ti/Pt gates. We show that Dit is minimized at an anneal temperature of 350 °C for all materials, but Ti/Pd and Ti/Pt have higher Qf and Dit compared to Al. In addition, σ and α increase with anneal temperature for all three metals with α larger than the bulk value. These results indicate that there is a trade-off between minimizing defects and minimizing the impact of strain in quantum device fabrication.

Effect of ferroelectric and interface films on the tunneling electroresistance of the Al2O3/Hf0.5Zr0.5O2 based ferroelectric tunnel junctions

Ferroelectric random-access memory (FRAM) based on conventional ferroelectric materials is a non-volatile memory with fast read/write operations, high endurance, and 10 years of data retention time. However, it suffers from destructive read-out operation and lack of CMOS compatibility. HfO2-based ferroelectric tunnel junctions (FTJ) may compensate for the shortcomings of FRAM by its CMOS compatibility, fast operation speed, and non-destructive readout operation. In this study, we investigate the effect of ferroelectric and interface film thickness on the tunneling electroresistance or ON/OFF current ratio of the Hf0.5Zr0.5O2/Al2O3 based FTJ device. Integrating a thick ferroelectric layer (i.e. 12 nm Hf0.5Zr0.5O2) with a thin interface layer (i.e. 1 nm Al2O3) resulted in an ON/OFF current ratio of 78. Furthermore, to elucidate the relationship between ON/OFF current ratio and interfacial properties, the Hf0.5Zr0.5O2-Al2O3 films and Ge-Al2O3 interfaces are examined via time-of-flight secondary ion mass spectrometry depth profiling mode. A bilayer oxide heterostructure (Hf0.5Zr0.5O2/Al2O3) is deposited by atomic layer deposition (ALD) on the Ge substrate. The ON/OFF current ratio is enhanced by an order of magnitude when the Hf0.5Zr0.5O2 film deposition mode is changed from exposure (H2O) ALD to sequential plasma (sequential O2–H2) ALD. Moreover, the interfacial engineering approach based on the in situ ALD H2-plasma surface pre-treatment of Ge increases the ON/OFF current ratio from 9 to 38 by reducing the interfacial trap density state at the Ge-Al2O3 interface and producing Al2O3 with fewer oxygen vacancies as compared to the wet etch (HF + H2O rinse) treatment of the Ge substrate. This study provides evidence of strong coupling between Hf0.5Zr0.5O2 and Al2O3 films in controlling the ON/OFF current ratio of the FTJ.

Low activation energy field-effect transistors fabricated by bar-assisted meniscus shearing

Here, we study the temperature-dependent transport properties of OFETs with the prototypical OSC 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) co-processed with polystyrene (PS) as the active layer. The active layer is deposited directly on SiO2 using the bar-assisted meniscus shearing (BAMS) method. The co-processing with PS favors a consequential decrease in interfacial trap densities as previously reported. Furthermore, we demonstrate how this processing method leads to devices exhibiting activation energies well below the current state of the art for TIPS-pentacene on SiO2 or other dielectrics. Altogether, our study reports on TIPS-pentacene thin films exhibiting an activation energy (Ea) as low as 15 meV when the active material is blended with PS and processed via BAMS. Such an unprecedentedly low value originates not only from a decrease in the interfacial trap densities but also from trapping energies much shallower than previously reported elsewhere for the same material. This allows us to clarify the previously reported notion that significant passivation of interfacial traps occurs following the separation of PS from TIPS-pentacene into an individual layer at the interface with the insulator and to confirm that the enhanced transport originates from a synergistic effect wherein both trapping density and depth are reduced.

Evaluation of interface traps inside the conduction band of InAs-on-insulator nMOSFET by self-consistent Hall-QSCV method

Interface trap density (Dit) inside the conduction band of (111)-oriented InAs-on-insulator (InAs-OI) n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) was experimentally evaluated by developing a method through a combination of a Hall measurement and quasi-static split C–V (Hall-QSCV). The surface potential and Dit of the InAs-OI nMOSFET were self-consistently calculated by numerically solving the Schrödinger–Poisson equation. The energy distributions of Dit were found to be almost independent of the ultra-thin-body channel thickness and the quantization energy, indicating the validity of the proposed Hall-QSCV evaluation. The energy position of the Dit minimum is in good agreement with the theoretically predicted position of the charge neutrality level, which locates deeply inside the conduction band of InAs. The experimental maximum surface electron density Nsmax at the InAs MOS interface, limited by Fermi level pinning, is 1.2 × 1013 cm−2, which is 2–3 times higher than Nsmax at the In0.53Ga0.47As MOS interfaces, owing to the lower Dit inside the InAs conduction band.

Characteristics of In0.7Ga0.3As MOS Capacitors with Sulfur and Hydrazine Pretreatments

This paper proposes an effective pretreatment process that combines wet ammonium sulfide ((NH4)2S) dipping and hydrazine (N2H4) vapor treatment before high dielectric constant (κ, kappa) deposition to reduce native oxide and elemental arsenic (As) before atomic layer deposition of ammonium oxide (Al2O3) gate dielectrics on n-doped indium gallium arsenide (In0.7Ga0.3As) layers to form metal oxide semiconductor capacitors (MOSCAPs). X-ray photoelectron spectroscopy (XPS) analysis confirms that sulfuration of In0.7Ga0.3As surface by (NH4)2S solution dipping can effectively reduce indium–oxygen (In–O), gallium–oxygen (Ga–O), arsenic–oxygen (As–O) bonds while elemental As still exist at the high-κ/In0.7Ga0.3As interface. Furthermore, N2H4 treatment on sulfurated In0.7Ga0.3As can effectively suppress the native oxides and elemental As. Accordingly, the obtained data indicate that the combination of chemical sulfur pretreatment and N2H4 treatment is advantageous to passivate the trap states on In0.7Ga0.3As metal–oxide–semiconductor capacitors (MOSCAPs). Moreover, forming gas annealing (FGA) process could further improve the capacitance-voltage (C–V) characteristics and the interface trap density (Dit) of In0.7Ga0.3As MOSCAP could be reduced significantly, achieving a value of 1.2 × 1012 cm−2 eV−1.

Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces

We study the impact of the atomic layer deposition high-k gate insulators on metal–oxide–semiconductor (MOS) interface properties of Si0.78Ge0.22 gate stacks with TiN gate electrodes and the physical origins of the reduction in MOS interface defects. The SiGe MOS interface properties of TiN/Y2O3, Al2O3, HfO2, and ZrO2 gate stacks are compared over a wide range of annealing temperatures. It is found that the lowest interface trap density (Dit) is obtained by TiN/Y2O3 stacks with post-metallization annealing (PMA) at 450 °C among the gate stacks with other gate insulators. Moreover, it is revealed that less amount of GeOx in the interfacial layer leads to lower Dit and that the Y2O3 stacks yield further reduction in Dit during PMA at 450 °C. These results can be explained by the reduction in distorted Ge–O bond densities in GeOx in ILs by scavenging and annealing effects during PMA and the suppression of Ge dangling bond generation by incorporating Y atoms into GeOx during PMA at 450 °C.

Defect Characterization in High‐Electron‐Mobility Transistors with Regrown p‐GaN Gate by Low‐Frequency Noise and Deep‐Level Transient Spectroscopy

To investigate the defects from the gate regrowth process, samples with and without regrowth p‐GaN process are fabricated by metalorganic chemical vapor deposition (MOCVD). The DC characteristics indicate larger gate leakage (Igs) between the GaN channel and the p‐GaN gate in the regrowth sample than in the nonregrowth counterpart. In addition, significant Si/O impurities are introduced by the regrowth process at the interface between channel and regrown AlGaN barrier. The low‐frequency noise (LFN) measurement and deep‐level transient spectroscopy (DLTS) are further carried out to investigate the defectivity at the AlGaN barrier and channel interface, giving a 2–3 times higher border trap density in the AlGaN barrier (depth ≈5 nm from the channel interface) and a 10 times increase in interface trap density at the channel interface, corresponding with a band of shallow levels E3 = Ec–0.02–0.15 eV. Three additional bulk traps E2/E5 (Ec–0.8 eV, / Ec–0.17 eV, ) and E4 (Ec–0.23 eV, ) are also found in the regrowth and nonregrowth samples, respectively. Their possible spatial locations and origins are discussed.

Capacitance–voltage analysis of Al2O3/WS2 metal-oxide-semiconductor capacitors

We report the capacitance–voltage analysis of Al2O3/WS2 metal-oxide-semiconductor capacitors fabricated with mechanically exfoliated multilayer WS2 crystals. Capacitance–voltage characteristics indicated n-type conduction in WS2 with both high- and low-frequency behavior between 100 Hz and 1 MHz. Based on capacitance–voltage analysis, we reproducibly obtained electron concentration of ∼1017 cm−3 in WS2 and relatively low minimum trap density of ∼1011–1012 eV−1 cm−2 at Al2O3/WS2 interface. We also observed low dispersion of accumulation capacitance with respect to frequency suggesting relatively low interface trap density. These results provide potentially important implications for using Al2O3/WS2 gate stack validating the usefulness of capacitance–voltage measurement in understanding device operation of WS2 and other transition metal dichalcogenides.

Investigation and optimization of HfO2 gate dielectric on N-polar GaN: Impact of surface treatments, deposition, and annealing conditions

UV-assisted capacitance–voltage (C–V) and current–voltage (I–V) measurements were performed on ∼20 nm HfO2/GaN metal–insulator–semiconductor capacitors. The effects of surface preparation, predeposition treatment, HfO2 deposition process, and post-deposition annealing environment on interface characteristics were studied. Surface preparation by etching in diluted BHF and piranha etch prior to atomic layer deposition (ALD) suppressed the interface states compared to the baseline sample possibly due to the removal of the native oxide and impurities. UV/ozone treatment prior to HfO2 deposition reduced the interface states by one order of magnitude compared to the baseline sample possibly due to the formation of a thin Ga2O3 interlayer. In situ ALD pretreatment with tri-methyl-aluminum/N2 plasma was also found to reduce the surface states significantly compared to the baseline sample. In addition, thermal ALD improved the dielectric constant and breakdown voltage of the dielectric as compared to plasma ALD due to less surface damage. The lowest average interface trap density achieved was 1.64 × 1012 cm−2/eV with an HfO2 dielectric constant of 16 on the sample with UV/ozone and piranha treatment with in situ ALD treatment and thermal ALD deposition.