Interfacial Oxide Thickness Research Articles

Oxygen Scavenging in HfZrOx‐Based n/p‐FeFETs for Switching Voltage Scaling and Endurance/Retention Improvement

AbstractThe authors demonstrate improved switching voltage, retention, and endurance properties in HfZrOx (HZO)‐based n/p‐ferroelectric field‐effect transistors (FeFETs) via oxygen scavenging. Oxygen scavenging using titanium (Ti) in the gate stack successfully reduce the thickness of interfacial oxide between HZO and Si and the oxygen vacancy at the bottom interface of the HZO film. The n/p‐FeFETs with scavenging exhibit an immediate read‐after‐write with stable retention property and improved endurance property. In particular, n‐FeFET with scavenging exhibits excellent endurance property that does not show breakdown up to 1010 cycles. The charge trapping model in the n/p‐FeFETs is presented to explain why the effect of oxygen scavenging is more pronounced in n‐FeFET than in p‐FeFET. Finally, further switching voltage scaling potential is estimated by scavenging and HZO thickness scaling. It is believed that this work contributes to the development of low‐power FeFET and the understanding of FeFET operation.

Interface Engineering of TiO2 Photoelectrode Coatings Grown by Atomic Layer Deposition on Silicon.

Titanium dioxide (TiO2) can protect photoelectrochemical (PEC) devices from corrosion, but the fabrication of high-quality TiO2 coatings providing long-term stability has remained challenging. Here, we compare the influence of Si wafer cleaning and postdeposition annealing temperature on the performance of TiO2/n+-Si photoanodes grown by atomic layer deposition (ALD) using tetrakis(dimethylamido)titanium (TDMAT) and H2O as precursors at a growth temperature of 100 °C. We show that removal of native Si oxide before ALD does not improve the TiO2 coating performance under alkaline PEC water splitting conditions if excessive postdeposition annealing is needed to induce crystallization. The as-deposited TiO2 coatings were amorphous and subject to photocorrosion. However, the TiO2 coatings were found to be stable over a time period of 10 h after heat treatment at 400 °C that induced crystallization of amorphous TiO2 into anatase TiO2. No interfacial Si oxide formed during the ALD growth, but during the heat treatment, the thickness of interfacial Si oxide increased to 1.8 nm for all of the samples. Increasing the ALD growth temperature to 150 °C enabled crystallization at 300 °C, which resulted in reduced growth of interfacial Si oxide followed by a 70 mV improvement in the photocurrent onset potential.

Corrosion Mitigation by Photocatalytic Effect of TiO2 Coating on Low Carbon Steel

In this study, the photoelectrochemical behavior of the carbon steel with TiO2 coating by sol-gel method were investigated to preventing or minimizing the atmospheric corrosion. Various oxide structure of carbon steel and the TiO2 annealing process were also investigated in this study.The crystallinity of TiO2 was analyzed with grazing incident X-ray diffraction (GIXRD) and the interfacial oxide layer composition and thickness were analyzed via the Raman spectroscopy and SEM, respectively. Potential dynamic analyses and open circuit potential (OCP) measurement were carried out under a designated solution to evaluate the corrosion mitigation of the TiO2 coated carbon steel with or without UV illumination. These results indicated that the TiO2 treatment with UV illumination would effectively reduce the carbon steel corrosion rate in atmospheric environments.

Corrosion Mitigation By Photocatalytic Effect of TiO2 Coating on Low Carbon Steel

Titanium dioxide (TiO2) is one of the most commonly used photocatalyst at the field of environmental remediation and energy applications. TiO2 is an n-type semiconductor that can be excited by photon irradiation to generate electron-hole pairs in its space charge layer under UV illumination. The excited electrons in the conduction band are then transferred to the metal surface, leading to decrease in both the corrosion potential and the oxidation reaction rate of the metal.In this study, the photoelectrochemical behavior of the carbon steel with TiO2 coating by sol-gel method were investigated to preventing or minimizing the atmospheric corrosion. Various oxide structure of carbon steel and the TiO2 annealing process were also investigated in this study.The crystallinity of TiO2 was analyzed with grazing incident X-ray diffraction (GIXRD) and the interfacial oxide layer composition and thickness were analyzed via the Raman spectroscopy and SEM, respectively. Potential dynamic analyses and open circuit potential (OCP) measurement were carried out under a designated solution to evaluate the corrosion mitigation of the TiO2 coated carbon steel with or without UV illumination. These results indicated that the TiO2 treatment with UV illumination would effectively reduce the carbon steel corrosion rate in atmospheric environments.

Heterojunction Solar Cell with Carrier Selective Contact Using MoOx Deposited by Atomic Layer Deposition

Hole carrier selective MoOx film is obtained by atomic layer deposition(ALD) using molybdenum hexacarbonyl[Mo(CO)6] as precursor and ozone(O3) oxidant. The growth rate is about 0.036 nm/cycle at 200 g/Nm of ozone concentration and the thickness of interfacial oxide is about 2 nm. The measured band gap and work function of the MoOx film grown by ALD are 3.25 eV and 8 eV, respectively. X-ray photoelectron spectroscopy(XPS) result shows that the Mo6+ state is dominant in the MoOx thin film. In the case of ALD-MoOx grown on Si wafer, the ozone concentration does not affect the passivation performance in the as-deposited state. But, the implied open-circuit voltage increases from 576 °C to 620 °C at 250 g/Nm after post-deposition annealing at 350 °C in a forming gas ambient. Instead of using a p-type amorphous silicon layer, high work function MoOx films as hole selective contact are applied for heterojunction silicon solar cells and the best efficiency yet recorded (21 %) is obtained.

Axial EBIC oscillations at core/shell GaAs/Fe nanowire contacts

Electron beam induced current (EBIC) measurements were carried out in situ in the scanning electron microscope on free-standing GaAs/Fe core–shell nanowires (NWs), isolated from the GaAs substrate via a layer of aluminum oxide. The excess current as a function of the electron beam energy, position on the NW, and scan direction were collected, together with energy dispersive x-ray spectroscopy. A model that included the effects of beam energy and Fe thickness predicted an average collection efficiency of 60%. Small spatial oscillations in the EBIC current were observed, that correlated with the average Fe grain size (30 nm). These oscillations likely originated from lateral variations in the interfacial oxide thickness, affecting the resistance, barrier potentials, and density of minority carrier recombination traps.

Postgrowth Control of the Interfacial Oxide Thickness in Semiconductor–Insulator–Semiconductor Heterojunctions

AbstractThe electronic properties of the heterojunction formed by chemical bath deposition of a thorium‐ and oxygen‐doped PbS nanostructured layer on GaAs substrate as a function of postgrowth thermal treatments are studied. A correlation is found between the heterojunction conductance and the duration of thermal treatment in air. In contrast to previous reports on the effect of air annealing on PbS films, where the conductance increased due to oxygen incorporation within the PbS, in this oxygen‐saturated system, the PbS properties are unaffected by exposure to oxygen. Control over the heterojunction conductance is achieved by tuning the interface oxide thickness, enabled by thermal treatment in air, resulting in the elimination of Fermi level pinning caused by interface induced gap states. The ability to control the interfacial insulator thickness post film‐growth is a unique feature of this system.

DIFFERENTIAL DEPLETION CAPACITANCE APPROXIMATION ANALYSIS UNDER DC VOLTAGE FOR AIR-EXPOSED Cu/n-Si SCHOTTKY DIODES

It is well known that the semiconductor surface is easily oxidized by air-media in time. This work studieds the characterization of Schottky diodes and changes in depletion capacitance, which is caused by air exposure of a group of Cu/n-Si/Al Schottky diodes. First, data for current-voltage and capacitance-voltage were a Ren, and then ideality factor, barrier height, built-in potential ([Formula: see text], donor concentration and Fermi level, interfacial oxide thickness, interface state density were calculated. It is seen that depletion capacitance was calculate; whereafter built-in potential played an important role in Schottky diodes characteristic. Built-in potential directly affects the characteristic of Schottky diodes and a turning point occurs. In case of forward and reverse bias, depletion capacitance versus voltage graphics are matched, but in an opposite direction. In case of forward bias, differential depletion capacitance begins from minus values, it is raised to first [Formula: see text], then reduced to second [Formula: see text] under the minus condition. And it sharply gones up to positive apex, then sharply falls down to near zero, but it takes positive values depending on DC voltage. In case of reverse bias, differential depletion capacitance takes to small positive values. In other respects, we see that depletion characteristics change considerably under DC voltage.

On the mechanisms of cation injection in conducting bridge memories: The case of HfO2 in contact with noble metal anodes (Au, Cu, Ag)

Resistance switching is studied in HfO2 as a function of the anode metal (Au, Cu, and Ag) in view of its application to resistive memories (resistive random access memories, RRAM). Current-voltage (I-V) and current-time (I-t) characteristics are presented. For Au anodes, resistance transition is controlled by oxygen vacancies (oxygen-based resistive random access memory, OxRRAM). For Ag anodes, resistance switching is governed by cation injection (Conducting Bridge random access memory, CBRAM). Cu anodes lead to an intermediate case. I-t experiments are shown to be a valuable tool to distinguish between OxRRAM and CBRAM behaviors. A model is proposed to explain the high-to-low resistance transition in CBRAMs. The model is based on the theory of low-temperature oxidation of metals (Cabrera-Mott theory). Upon electron injection, oxygen vacancies and oxygen ions are generated in the oxide. Oxygen ions are drifted to the anode, and an interfacial oxide is formed at the HfO2/anode interface. If oxygen ion mobility is low in the interfacial oxide, a negative space charge builds-up at the HfO2/oxide interface. This negative space charge is the source of a strong electric field across the interfacial oxide thickness, which pulls out cations from the anode (CBRAM case). Inversely, if oxygen ions migration through the interfacial oxide is important (or if the anode does not oxidize such as Au), bulk oxygen vacancies govern resistance transition (OxRRAM case).

Effect of interfacial oxide thickness on the photocatalytic activity of magnetron-sputtered TiO2coatings on aluminum substrate

The influence of the coating/substrate interface on the photocatalytic behavior of Al-TiO2 coatings was investigated. The TiO2 coatings were prepared by magnetron sputtering. The nanoscale structure of the coating was analyzed using X-ray diffraction; atomic force microscopy; scanning electron microscopy; andtransmission electronmicroscopy. Thephotocatalytic behavior was investigated through optical spectrophotometry studies and electrochemical experiments; as photo voltage; photocurrent; and electrochemical impedance measurements. Consistent results from both optical and electrochemical measurements showed a maximum UV-light absorption by titanium dioxide occurring slightly prior to the energy of the maximum photocurrent. The photocurrent of titanium dioxide decreases with increasing thickness of the aluminum oxide interface layer. Aluminumoxide acts as an insulator; disfavoring the electron transport between the coating and the metallic substrate. The highest photocurrents were indeed obtained when the thickness of interfacial aluminum oxide could be reduced by sputtering a thin Ti layer prior to TiO2 coating. [GRAPHICS] Photocurrent plotted for different photon energy for a TiO2 coating on a Ti interlayer consisting of both rutile and anatase. Two photon-excitation peaks from the TiO2 coating (anatase and rutile) are observed at a potential of 0.34V versus SHE, while only one peak was observed at a potential 0.14V versus SHE closer to the conduction band. (C) 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Influence of interfacial oxide on the optical properties of single layer CdTe/CdS quantum dots in porous silicon scaffolds

Using a combination of continuous wave and time-resolved spectroscopy, we study the effects of interfacial conditions on the radiative lifetimes and photoluminescence intensities of sub-monolayer colloidal CdTe/CdS quantum dots (QDs) embedded in a three-dimensional porous silicon (PSi) scaffold. The PSi matrix was thermally oxidized under different conditions to change the interfacial oxide thickness. QDs embedded in a PSi matrix with ∼0.4 nm of interfacial oxide exhibited reduced photoluminescence intensity and nearly five times shorter radiative lifetimes (∼16 ns) compared to QDs immobilized within completely oxidized, porous silica (PSiO2) frameworks (∼78 ns). The exponential dependence of QD lifetime on interfacial oxide thickness in the PSi scaffolds suggests charge transfer plays an important role in the exciton dynamics.

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

Mobility in high-k/metal-gate Ultra-Thin Body and Box Fully Depleted SOI devices has been extensively investigated by means of multi-scale simulations and experimental data. Split-CV mobility measurements have been performed for various Interfacial Layer Equivalent Oxide Thickness allowing an investigation of the physical mechanisms responsible for the mobility degradation at high-k/Interfacial layer interface. The impact of the back bias on transport properties is investigated and mobility enhancement in the reverse regime (back gate inversion) is studied. A multi-scale simulation strategy is ranging from quantum Non-equilibrium Green’s Functions to semi-classical Kubo Greenwood approach. These advanced solvers made possible a throughout calibration of empirical TCAD mobility models.

Effect of the Interfacial SiO2 Layer on High-k Gate Stacks

Interfacial oxide (IL) /high-k (HK) gate dielectric stack is widely used in 45nm logic technology and beyond nodes. Interfacial oxide, which is buffer layer between silicon substrate and HK dielectric, is a crucial factor to control Silicon/IL, IL/high-k interface charge and high-k film quality. In this work, atom layer deposition (ALD) Hf based HK film is deposited on two classes of IL by thermal oxidation (process A or B) and chemical oxidation (process C or D), respectively. XPS is used to characterize the film bonding energy, while non contact CV and spectroscopic ellipsometry (SE) are used to characterize the interface trap. The electric properties of the film stacks are characterized by C-V and I-V curves. The results reveal that interface trap of chemical oxide film has positive surface voltage and less dense SiOx, as compared with that of thermal oxide. With the same interfacial oxide thickness and HK deposition process, the chemical oxide/HK stack got 3.4A thick EOT, which is about two orders lower leakage than that of thermal oxide/HfO2. It can be explained by the fact that chemical oxide had plenty of O-H bonds, which is good for ALD Hf based HK film nucleation and growth and resulted in good film quality. However, due to the high Si/chemical oxide interfacial charge, the chemical oxide/HfO2 dielectric stack has a disadvantage of the larger C-V hysteresis.

Effects of annealing temperature and interfacial oxide thickness on layer exchange metal-induced crystallization

In this paper, we investigated a layer exchange metal-induced crystallization (LE-MIC) process in detail for various thicknesses of the interfacial oxide (Al2O3: 0, 2, and 5 nm) at different annealing temperatures of 400 °C, 450 °C, 500 °C, and 550 °C, at which the metal-induced germanium melting (MIGM) process can occur. This MIGM mechanism, together with the LE-MIC process improved the quality of the Ge crystallites. Finally, we achieved fairly big (4 ∼ 5 µm) and (111)-oriented Ge crystal grains on a SiO2/Si substrate at 550 °C by combining the LE-MIC and the MIGM processes.

Gate current modelling through high-k gate stack MOSFET for very-large-scale integration logic circuit analysis

In this paper, we present a computationally efficient model for gate tunnelling current through different high-k gate dielectrics stack structures by adjusting two fitting parameters. The proposed model can be used in circuit simulator due to its simplicity in implementation. Various materials of high-k gate dielectrics stack have been examined and compared to analyse the reduction of gate leakage current by considering the effects of interfacial oxide thickness, type of gate stack, on current, off current, drain induced barrier lowering and sub-threshold slope. Consequently an optimised high-k gate dielectrics stack structure is proposed and used to analyse the gate leakage current in CMOS (complementary metal oxide semiconductor) based universal logic gates. The results obtained have been verified with Sentaurus simulation for the purpose of validation.

Gate Current Modelling through High-K Gate Stack MOSFET for Very-Large-Scale Integration Logic Circuit Analysis

In this paper, we present a computationally efficient model for gate tunnelling current through different high-k gate dielectrics stack structures by adjusting two fitting parameters. The proposed model can be used in circuit simulator due to its simplicity in implementation. Various materials of high-k gate dielectrics stack have been examined and compared to analyse the reduction of gate leakage current by considering the effects of interfacial oxide thickness, type of gate stack, on current, off current, drain induced barrier lowering and sub-threshold slope. Consequently an optimised high-k gate dielectrics stack structure is proposed and used to analyse the gate leakage current in CMOS (complementary metal oxide semiconductor) based universal logic gates. The results obtained have been verified with Sentaurus simulation for the purpose of validation.

Improvement in both mobility and bias stability of ZnSnO transistors by inserting ultra-thin InSnO layer at the gate insulator/channel interface

This study examined the effect of the thickness of interfacial indium-tin oxide (ITO) on the performance and bias reliability of zinc-tin oxide (ZTO) thin film transistors (TFTs). The 3.5-nm-thick ITO-inserted ZTO TFTs exhibited superior mobility (43.2 cm2/V s) to that of the ZTO only TFTs (31.6 cm2/V s). Furthermore, the threshold voltage shifts for the ZTO/ITO bi-layer device decreased from 1.43 and −0.88 V (ZTO only device) to 0.46 V and −0.41 V under positive and negative bias stress, respectively. This improvement can be attributed to a decrease in the interfacial trap density for the ITO-inserted ZTO device.

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO2/TiN gate stack (EOT<1nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.

Improvement of Atomic-Layer-Deposited Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/GaAs Interface Quality through a Novel Sulfuration Method

The absence of stable oxide/GaAs interface greatly holds back the step of GaAs-based MOSFETs fabrication. In this letter, we report on the chemical passivation of n-type GaAs surface by introducing a new sulfuration method. X-ray photon-electron spectroscopy (XPS) analyses indicate that most GaAs native oxides and elemental arsenic (As) can be more effectively removed by treating the GaAs surface in CH3CSNH2 solution compared to the traditional (NH4)2S solution. Capacitance-Voltage characteristics of the CH3CSNH2 treated MOS capacitors also presents reduced interfacial layer and equivalent oxide thickness which are well consisted with the conclusion obtained by XPS.

Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-k dielectrics for nanoscale double-gate MOSFETs

Gate-leakage current reduction is the key motivation for the replacement of traditional SiO2 gate insulator with alternative gate dielectrics. In this work, a guideline for the determination of the suitable high-k candidate was reported in the case of a SiO2/high-k gate stack in a nanoscale double-gate (DG) MOSFET. Analytical models of direct tunneling gate leakage current with SiO2 as an interfacial layer have been considered. Using these models, the most promising high-k materials for different conditions were predicted, considering the effects of equivalent oxide thickness (EOT), gate leakage current, electron effective mass, dielectric constant-k value, barrier height and interfacial oxide thickness.