Abstract
In this paper, we present a computationally efficient model for gate tunnelling current through different high-k gate dielectrics stack structures by adjusting two fitting parameters. The proposed model can be used in circuit simulator due to its simplicity in implementation. Various materials of high-k gate dielectrics stack have been examined and compared to analyse the reduction of gate leakage current by considering the effects of interfacial oxide thickness, type of gate stack, on current, off current, drain induced barrier lowering and sub-threshold slope. Consequently an optimised high-k gate dielectrics stack structure is proposed and used to analyse the gate leakage current in CMOS (complementary metal oxide semiconductor) based universal logic gates. The results obtained have been verified with Sentaurus simulation for the purpose of validation.
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