Interface Trap Research Articles

Interfacial charge associated reliability improvement in arsenide/antimonide tunneling interfaced-junctionless TFET

This article focuses on the investigation of reliability improvement in the arsenide/antimonide tunable bandgap tunneling interfaced junctionless TFET (HD-HJLTFET) by introducing positive (donor) and negative (acceptor) localized interfacial trap charges (ITCs) at the semiconductor/oxide (S/O) and semiconductor/semiconductor (S/S) interface. The compound semiconducting materials, InAs (lower bandgap) and AlGaSb (higher bandgap) have been incorporated in the source and channel regions in the proposed device (HJLTFET). Further, to improve the device reliability against ITCs, a hetero dielectric engineered gated device has also been designed and analysed (HD-HJLTFET). In HD-HJLTFET, a high-k dielectric near source to channel (S/C) interface and low-k dielectric region towards drain to channel (D/C) interface has been used. It has been obtained that HD engineering enhances the microwave and harmonic distortion performance of HD-HJLTFET. It has been evaluated that HD-HJLTFET/ HJLTFET delivers ON current of 38.3 μA/14μA, transconductance 108 μS/23.2μS, cut-off frequency 805.8GHz/406.7GHz and gain of 223.5/197.4. Further results show that HD delivers gm2 (∼28% ↓), gm3 (∼9 times), second-order and third-order harmonic distortion (∼42% ↓ and ∼90% ↓), and total harmonic distortion (∼26% ↓) as compared to HJLTFET. The linearity parameters of HD-HJLTFET (VIP2, VIP3, IIP3, 1dB compression point, and IMD3) also showed marked improvement with negligible variation against different ITC polarity than its counter device, making it more reliable for low power microwave and distortion-free wireless communication systems.

A novel solution to improve static and dynamic retention characteristics by enhancing hydrogen passivation with in situ LD-TEOS/TEOS dual layer

We proposed a novel solution to improve both static and dynamic retention characteristics by additional etching of the thickness of Silicon Boron Nitride (SIBN), stopper when oxide etch, with in situ dual low deposition-tetraethyl orthosilicate (LD-TEOS)/TEOS Dual layer. As Dynamic Random Access Memory Cells shrink, it is difficult to obtain reliable retention properties, so it becomes more significant to reduce the number of interface trap (Nit) by hydrogen passivation. In this work, Nit decreased by reducing the thickness of SIBN, which has low hydrogen diffusion coefficients, improve the static and dynamic retention characteristics simultaneously through enhancing hydrogen passivation with in situ LD-TEOS Dual layer compensating for Metal contact to Other Bit line pad distance margin risk.

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

In a vertical TFET structure, controllability over the gate is enhanced because of the favorable electrostatic potential and tunneling under the entire gate region by preventing the direct source to drain tunneling. For an L-shaped TFET, the Band-to-Band-Tunneling (BTBT) is perpendicular and parallel to the channel length. Also, it has a higher I on (ON-current) with suppressed ambipolar current (low I ambi ) and is more scalable than other vertical BTBT mechanism-based TFET structures. The reliability of n-type single gate L-shaped TFET (SG-nLTFET) is investigated by examining: (1) impact of temperature (Temp K ) variation (from 260 K to 460 K) and (2) Interface trap charge (ITCs) polarity at fixed charge density on analog /RF /linearity figure of merits (FOMs). The obtained results reveal that change in polarity of ITCs at the Si/HfO 2 interface,modifies the analogue characteristics of the SG-nLTFET significantly in terms of turn-on voltage as well as I on . The temperature sensitivity of SG-nLTFET device indicates that the ShockleyReadHall (SRH) and Trap-Assisted-Tunneling (TAT) phenomenon dominates at lower gate bias and degrades the I on /I off ratio at high temperatures. On the other hand, the BTBT mechanism predominates in the subthreshold regime of transfer characteristics. Furthermore, the results reveal that the off-state current (I off ) degrades dramatically at high temperatures. According to the empirical analysis, SG-nLTFET is insusceptible to Positive-ITCs (Donor trap charges, P-ITCs) present at Si/HfO 2 interface in comparison to Negative-ITCs (Acceptor trap charges, N-ITCs).

A 2D Cryptographic Hash Function Incorporating Homomorphic Encryption for Secure Digital Signatures.

User authentication is a critical aspect of any information exchange systemwhich verifies the identities of individuals seeking access to sensitive information. Conventionally, this approachrelies on establishing robust digital signature protocolswhich employ asymmetric encryption techniques involving a key pair consisting of a public key and its matching private key. In this article, a user verification platform constructed using integrated circuits (ICs) with atomically thin two-dimensional (2D) monolayer molybdenum disulfide (MoS2 ) memtransistors is presented. First, generation of secure cryptographic keys is demonstrated by exploiting the inherent stochasticity of carrier trapping and detrapping at the 2D/oxide interface trap sites. Subsequently, the ability to manipulate the functionality of logical NOR is leveraged to create a secure one-way hash function which when homomorphically operated upon with NAND, XOR, OR, NOT, and AND logic circuits generate distinct digital signatures. These signatures when subsequently decrypted, verify the authenticity of the receiver while ensuring complete preservation of data integrity and confidentiality as the underlying information is never revealed. Finally, the advantages of implementing a NOR-based hashing techniques in comparison to the conventional XOR-based encryption method are established. This demonstration highlights the potential of 2D-based ICs in developing critical hardware information security primitives.

Post-trench restoration for vertical GaN power devices

The impact of the post-trench restoration on the electrical characteristics of vertical GaN power devices is systematically investigated in this work. Following the achievement of microtrench-free GaN trench structure with modified dry etching conditions, the post-trench tetramethylammonium hydroxide (TMAH)-based wet etching and UV/Ozone-based oxidation process are employed to further refine the trench profile. It is shown that the c-plane trench bottom is restored to the level of unetched surface, as evidenced by the improved Schottky interface. Additionally, the post-trench treatment exhibits the anisotropic characteristics with the preferred rounded corner profile on m-plane sidewall compared to a-plane sidewall. The simulations and experimental results demonstrate that the trench MOS barrier Schottky (TMBS) rectifier based on m-plane sidewall could suppress the electric field crowding at the trench corner and, hence, reduce the reverse leakage current by 1–2 orders of magnitude. Furthermore, the MOSCAP test structures were fabricated on the trenches. The extracted interface trap density (Dit) confirms the effective restoration of trench bottom. However, the sidewall surface exhibits the relatively large Dit, which emphasizes the necessity of optimizing the sidewall, particularly for devices incorporating sidewall channel. The demonstrated post-trench restoration technique improves the surface quality and trench structure for the significantly enhanced electrical performances, which is essential for the development of vertical GaN power devices.

Investigation of atomic layer deposition methods of Al2O3 on n-GaN

In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states.

Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si0.7Ge0.3 Source Region at Device and Circuit Level

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si[Formula: see text]Ge[Formula: see text] material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high-[Formula: see text] dielectric material HfO2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices.

Effects of Varying Annealing Ambient towards Performance of Ternary GaxCeyOz Passivation Layers for Metal-Oxide-Semiconductor Capacitor

In this work, different annealing ambient (nitrogen-oxygen-nitrogen (N2-O2-N2), forming gas-oxygen-forming gas (FG-O2-FG), and argon-oxygen-argon (Ar-O2-Ar)) were explored to investigate the feasibility of employing the annealed ternary GaxCeyOz passivation layer (PL) for development of Si-based metal-oxide-semiconductor (MOS) capacitors. The impact of nitrogen and/or hydrogen in hindering the growth of silicon dioxide (SiO2) interfacial layer (IL) was quantitatively evaluated. The combination of effects brought by nitrogen attached to oxygen vacancies, nitrogen-silicon bonding, and nitrogen accumulation at the GaxCeyOz/Si interface effectively minimized the formation of SiO2 IL. Consequently, among all the samples, the GaxCeyOz PL annealed in N2-O2-N2 ambient exhibited superior MOS characteristics in terms of low effective oxide charge, slow trap density, interface trap density, and interface state density, which have translated into good leakage current density-electric field characteristics.

Impact of Noise and Interface Trap Charge on a Heterojunction Dual-Gate Vertical TFET Device

Impact of Noise and Interface Trap Charge on a Heterojunction Dual-Gate Vertical TFET Device

Study on the Hydrogen Effect and Interface/Border Traps of a Depletion-Mode AlGaN/GaN High-Electron-Mobility Transistor with a SiNx Gate Dielectric at Different Temperatures.

In this study, the electrical characteristics of depletion-mode AlGaN/GaN high-electron-mobility transistors (HEMTs) with a SiNx gate dielectric were tested under hydrogen exposure conditions. The experimental results are as follows: (1) After hydrogen treatment at room temperature, the threshold voltage VTH of the original device was positively shifted from -16.98 V to -11.53 V, and the positive bias of threshold was 5.45 V. When the VDS was swept from 0 to 1 V with VGS of 0 V, the IDS was reduced by 25% from 9.45 A to 7.08 A. (2) Another group of original devices with identical electrical performance, after the same duration of hydrogen treatment at 100 °C, exhibited a reverse shift in threshold voltage with a negative threshold shift of -0.91 V. The output characteristics were enhanced, and the saturation leakage current was increased. (3) The C-V method and the low-frequency noise method were used to investigate the effect of hydrogen effect on the device interface trap and border trap, respectively. It was found that high-temperature hydrogen conditions can passivate the interface/border traps of SiNx/AlGaN, reducing the density of interface/border traps and mitigating the trap capture effect. However, in the room-temperature hydrogen experiment, the concentration of interface/border traps increased. The research findings in this paper provide valuable references for the design and application of depletion-mode AlGaN/GaN HEMT devices.

Miniaturized spectrometer with intrinsic long-term image memory

Miniaturized spectrometers have great potential for use in portable optoelectronics and wearable sensors. However, current strategies for miniaturization rely on von Neumann architectures, which separate the spectral sensing, storage, and processing modules spatially, resulting in high energy consumption and limited processing speeds due to the storage-wall problem. Here, we present a miniaturized spectrometer that utilizes a single SnS2/ReSe2 van der Waals heterostructure, providing photodetection, spectrum reconstruction, spectral imaging, long-term image memory, and signal processing capabilities. Interface trap states are found to induce a gate-tunable and wavelength-dependent photogating effect and a non-volatile optoelectronic memory effect. Our approach achieves a footprint of 19 μm, a bandwidth from 400 to 800 nm, a spectral resolution of 5 nm, and a > 104 s long-term image memory. Our single-detector computational spectrometer represents a path beyond von Neumann architectures.

Reliability Instability Assessment with Interfacial Trapping Analysis for the Optimization of Al Composition in AlxGa1−xN/GaN High Electron Mobility Transistors

This study investigates the trapping characteristics present at the interface of AlxGa1−xN/GaN high electron mobility transistors (HEMTs) and explores the influence of the Al composition within the AlxGa1−xN barrier on the device's performance. Using a single pulse ID–VD characterization technique, the reliability instability is evaluated in two different AlxGa1−xN/GaN HEMTs: one with an Al composition of 25% (Al0.25Ga0.75N/GaN) and the other with an Al composition of 45% (Al0.45Ga0.55N/GaN). The results unveil a notable higher drain current degradation (ΔID) in Al0.45Ga0.55N/GaN devices, attributed to fast transient charge trapping. Conversely, the Al0.25Ga0.75N/GaN device exhibits a substantial 35% reduction in interface trap density (Dit) and an impressive 73% decrease in border trap density (Nbt), solidifying its reduced trapping behavior compared to Al0.45Ga0.55N/GaN due to the rougher barrier/channel interface of the latter device. Furthermore, load‐pull measurements unveiled a noteworthy 60% power‐added efficiency for the Al0.25Ga0.75N/GaN device, presenting a 10% performance improvement over the Al0.45Ga0.55N/GaN device. These findings provide valuable insights into the trapping phenomena within AlGaN/GaN HEMTs, paving the way for enhanced device design and performance optimization.

Design and simulation of a germanium source dual‐metal dopingless tunnel FET as a label‐free biosensor

AbstractThis study presents a new dual‐metal dopingless tunnel field effect transistor with a Germanium source (GeS‐DM‐DLT) for label‐free biomolecule detection. Introducing a Ge source and dual‐metal gate provides improved drain current. We have considered an L‐shaped cavity at the top and bottom source metal region for investigating the sensitivity. The biosensor's sensitivity has been measured using the neutral biomolecules' dielectric constants (varying the k‐values in the cavity). The sensor's DC performance is investigated using transfer characteristics, BTBT rate, energy band, and electric field variation for different k‐values. The sensitivity performance of the proposed biosensor is evaluated in terms of different DC parameters (drain current, surface potential, subthreshold swing, interband tunneling rate, electric field) and RF parameters (parasitic capacitance, transconductance, cut‐off frequency, maximum frequency). The suggested biosensor offers a much‐improved SON of 9.86 × 108 and SRATIO of 1.94 × 104 for a dielectric constant of 22.0 at room temperature. Further research has been done to study the effects of dielectric materials, interface trap carriers (ITC), and temperature on drain current, drain current sensitivity, and other sensitivity parameters. The article also includes investigating the influence of the fill factor on sensitivity performance. The GeS‐DM‐DLT sensor performs best in fully‐filled conditions compared to the partially‐filled condition inside the cavity region.

Effect of Temperature-Dependent Low Oxygen Partial Pressure Annealing on SiC MOS.

Oxygen post annealing is a promising method for improving the quality of the SiC metal oxide semiconductor (MOS) interface without the introduction of foreign atoms. In addition, a low oxygen partial pressure annealing atmosphere would prevent the additional oxidation of SiC, inhibiting the generation of new defects. This work focuses on the effect and mechanism of low oxygen partial pressure annealing at different temperatures (900-1250 °C) in the SiO2/SiC stack. N2 was used as a protective gas to achieve the low oxygen partial pressure annealing atmosphere. X-ray photoelectron spectroscopy (XPS) characterization was carried out to confirm that there are no N atoms at or near the interface. Based on the reduction in interface trap density (Dit) and border trap density (Nbt), low oxygen partial pressure annealing is proven to be an effective method in improving the interface quality. Vacuum annealing results and time of flight secondary ion mass spectrometry (ToF-SIMS) results reveal that the oxygen vacancy (V[O]) filling near the interface is the dominant annealing mechanism. The V[O] near the interface is filled more by O2 in the annealing atmosphere with the increase in temperature.

TID response of hybrid FinFET with modified gate dielectric

The total ionizing dose response of hybrid FinFET with a modified gate stack (GS) is investigated and examined for the various ultra-thin body (UTB) layers and combination of gate oxide stacks. Incorporation of UTB layer to the conventional FinFET enhances the mechanical strength of the device. While being irradiated, conventional FinFET with UTB layer reduces the accumulation of trap charges to a certain level. Further, reduction of these charges can be achieved by using a high-k dielectric with UTB layer. This reduction in interface trap charges enhance the OFF-state performance while maintaines the positive threshold voltage of the device. The combination of UTB and GS in SOI-FinFET renders it more reliable and tolerant to ionizing dose.

Influence of charge traps on charge plasma-germanium double-gate TFET for RF/Analog & low-power switching applications

The device reliability on account of charge traps at the Al2O3/Ge interface is a main distress for the Ge-based Tunnel Field Effect Transistor (TFET). Here, the influence of Interface Trap Charges (ITC) on the charge plasma-based Ge-Double-Gate TFET (CP-Ge-DGTFET) and conventional Ge-DGTFET's DC, Analog/RF, and linearity characteristics have been inspected using technology-computer-aided-design (TCAD) simulations for the donor (positive) and acceptor (negative) ITC. The charge plasma concept is adopted to induce excess carrier concentration within the source region on the integration of optimum work function metal electrodes. To recognize the impact of ITC, several figures of merits have been investigated, such as transfer characteristics, electric field, transconductance, cut-off frequency, parasitic capacitance, and linearity performance parameters (VIP2, VIP3, IIP3, and IMD3). The CP-Ge-DGTFET device structure revealed superior performance and reliability in comparison to Ge-DGTFET, even under the influence of ITC at the Al2O3/Ge interface. Therefore, the CP-Ge-DGTFET device structure is a sturdy contender for Analog/RF and low-power switching applications.

Influence of post fabrication annealing on device performance of InAlN/GaN high electron mobility transistors

In this study, effect of post-fabrication annealing (PFA) on the electrical performance of the InAlN/GaN high electron mobility transistors (HEMTs) has been investigated. With PFA, the gate Schottky barrier height increases by 94 % (from 1.03 eV to 2.00 eV) and the interface trap state density (Dit) is reduced by 27 %. Compared with the device without PFA, a higher on-current (11 %), a larger on/off current ratio (∼1 order), a higher transconductance (3 %), a reduced gate leakage current (84 %) and a lower subthreshold swing (10 %) are recorded in device with PFA. In addition, the improved electron mobility is observed and the reduction of polarization Coulomb field (PCF) scattering is proven in device with PFA due to the enhancement of polarization electrical field in InAlN/GaN heterostructure.

Effective passivation of p- and n-type In0.53Ga0.47As in achieving low leakage current, low interfacial traps, and low border traps

We have attained low leakage current, low interfacial traps, and low border traps by effectively passivating both p- and n-In0.53Ga0.47As (InGaAs) surfaces using the same gate dielectrics of ultra-high-vacuum deposited Al2O3/Y2O3. Gate leakage currents below 2 × 10−7 A/cm2 at gate fields of ±4 MV/cm were obtained after 800 °C rapid thermal annealing, demonstrating the intactness of the interface and heterostructure. Negligibly small frequency dispersions in the capacitance–voltage (C–V) characteristics of p- and n-type metal-oxide-semiconductor capacitors (MOSCAPs) were obtained from accumulation, flatband, to depletion as measured from 300 K to 77 K, indicative of low border and interfacial trap density; the C–V frequency dispersions in the accumulation region are 1.5%/dec (300 K) and 0.19%/dec (77 K) for p-InGaAs, and 2.2%/dec (300 K) and 0.97%/dec (77 K) for n-InGaAs. Very low interfacial trap densities (Dit's) of (1.7–3.2) × 1011 eV−1cm−2 and (6.7–8.5) × 1010 eV−1cm−2, as extracted from the conductance method, were achieved on p- and n-InGaAs MOSCAPs, respectively.

Effect of Proton Irradiation on Complementary Metal Oxide Semiconductor (CMOS) Single-Photon Avalanche Diodes

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 108 MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO2 interface trap generated by ionization.

Study of interface-trap and near-interface-state distribution in a 4H-SiC MOS capacitor with the full-distributed circuit model

In this research, the full-distributed circuit model was used to classify the contribution of interface traps (ITs) and near-interface states to the electrical characteristics of a 4H-SiC MOS capacitor over a wide range of operation. By fitting the measured capacitance and conductance at a certain value of applied gate voltage when the frequency varied from 1 kHz to 1 MHz, the density of both near-interface states and ITs was determined. The results reveal that, at RT, the frequency dispersion of capacitance in the depletion condition is mainly caused by the contribution of ITs. Nevertheless, in the strong accumulation condition, near-interface states become dominant for the frequency dispersion of the capacitance. Furthermore, the full-distributed circuit model also successfully explained the electrical characteristics of a 4H-SiC MOS capacitor when operating at 500 °C.