Interface-trap Buildup Research Articles

Effects of irradiation temperature on MOS radiation response

Effects of irradiation and annealing temperature on radiation-induced charge trapping are explored for MOS transistors. Transistors were irradiated with 10-keV x rays at temperatures from -25 to 100/spl deg/C and annealed at 100/spl deg/C for times up to 3.6/spl times/10/sup 6/ s. Transistor data were analyzed for the contributions of radiation-induced charge due to oxide traps, border traps, and interface traps. Increased irradiation temperature resulted in increased interface-trap and border-trap buildup and decreased oxide-trapped charge buildup during irradiation. Interface-trap buildup immediately following irradiation for transistors irradiated at 100/spl deg/C was equivalent to the buildup of interface traps in transistors irradiated at 27/spl deg/C and annealed for one week at 100/spl deg/C (standard rebound test). For the p-channel transistors, a one-to-one correlation was observed between the increase in interface-trap charge and the decrease in oxide-trapped charge during irradiation. This may imply a link between increased interface-trap buildup and the annealing of oxide-trapped charge in these devices. The observed data can be explained in terms of increased hydrogen ion transport rates to the Si/SiO/sub 2/ interface during elevated temperature irradiations. These results have implications on hardness assurance testing and potentially may be used to reduce costs associated with rebound qualification.

Latent interface-trap generation in commercial power VDMOSFETs

Latent interface-trap generation is one of the most controversial post-irradiation effects in MOSFETs, which can have a significant impact on device performance and reliability in radiation environments. In this paper, we present new experimental evidence of latent interface-trap buildup in commercial power VDMOSFETs: its dependencies on dose, temperature and gate bias applied during irradiation and annealing. We discuss several models for latent interface-trap buildup and show that the most consistent is one which involves the diffusion of molecular hydrogen from structures adjacent to the gate oxide (CVD oxide, poly-Si gate), and its cracking on positive charge centers in the oxide. The cracking reaction liberates hydrogen ions, which drift to the Si/SiO/sub 2/ interface to form interface traps. Some hypothesis from the recently proposed H-W model for post-irradiation behavior of interface traps may help resolve the question of the source of hydrogen sufficient to cause up to 800% increase in interface-trap density, experimentally observed. The implications of latent interface-trap generation for hardness assurance test methods are also discussed.

Modelling of kinetics of creation and passivation of interface traps in metal-oxide-semiconductor transistors during postirradiation annealing

The dependencies of creation–passivation processes of interface traps in irradiated n-channel metal-oxide-semiconductor transistors on the temperature and gate bias during annealing have been investigated. The experimental results, which are explained by the hydrogen–water (H–W) model, show the influence of both the annealing temperature and gate bias on these processes. The modelling of creation–passivation kinetics of interface traps, based on bimolecular theory and numerical analysis, is also performed. Numerical modelling shows that the H–W model can include the temperature and gate bias dependencies of creation of interface traps, latent interface trap buildup and the decrease of interface trap density.

Charge pumping analysis of radiation effects in LOCOS parasitic transistors

We have performed current-voltage and charge pumping measurements on LOCOS parasitic transistors submitted to X-ray irradiation. The electrical behavior and the charge pumping response of these non-planar structures have been analyzed by two-dimensional computer simulations. We report how this experimental approach allows us to obtain quantitative information about oxide charge and interface trap densities in different parts of the complete structure. Our results show a maximum of oxide charge trapping and interface trap buildup in the bird's beak regions after irradiation. The generation of radiation-induced interface and border traps along the LOCOS SiO/sub 2//Si interface is discussed, in terms of trap density and frequency response.

1/f noise, hydrogen transport, and latent interface-trap buildup in irradiated MOS devices

A large, delayed increase is observed in the postirradiation 1/f noise of Oki pMOS transistors prior to the onset of latent interface-trap buildup. Both effects are evidently due to similar thermally activated processes involving hydrogen. The increased noise through irradiation and anneal is found to be caused not only by the generation of defects at or near the Si/SiO/sub 2/ interface, but also by an apparent transition from buried to surface channel conduction. This is evidently triggered by the passivation of dopants in the Si by hydrogen transport during irradiation and anneal. Switched bias annealing confirms many of these effects are reversible. Three types of hydrogen transport are identified in MOS oxides: dispersive transport leading to two-stage interface-trap buildup, retarded transport leading to latent interface-trap buildup, and blockaded transport leading to proton confinement in SiO/sub 2/. The nature of the transport appears to correlate with O vacancy density and the temperature at which hydrogen is incorporated into the SiO/sub 2/. Implications are discussed for enhanced bipolar low dose rate response, the sensitivity of pMOS dosimeters, and protonic nonvolatile memory elements.

Processes in N-channel mosfets during postirradiation thermal annealing

The processes during postirradiation thermal annealing of γ-ray irradiated n-channel MOSFETs with both wet and dry gate oxides are investigated. For both analysed technologies, a so called “latent” interface trap buildup is observed, followed at very late annealing times by the decrease in the interface-trap density. A model is proposed that successfully accounts for the experimental results. Implications of observed effects for total dose hardness assurance test methods implementation are discussed.

Correlation between latent interface trap buildup and 1/f noise in metal–oxide–semiconductor transistors

A long-term delayed increase in the 1/f noise of p-channel metal–oxide–semiconductor (MOS) transistors is observed in devices that show significant latent interface-trap buildup after exposure to ionizing radiation. During positive-bias postirradiation anneal, the noise increases by more than an order of magnitude above the level observed after irradiation. The increase in noise precedes the latent buildup of interface traps by at least 4.5 days during room-temperature annealing, and by ∼1 h during 100 °C annealing. The time and temperature dependencies of the increases in noise and interface trap buildup are consistent with the thermally activated motion of protons into the near-interfacial region of the oxide, followed by increases in border trap and interface trap densities. These results suggest hydrogen-related species can significantly affect the 1/f noise of MOS devices.

Formation and passivation of interface traps in irradiated n-channel power VDMOSFETs during thermal annealing

The annealing of γ-ray irradiated commerical n-channel power VDMOSFETs at elevated temperature is investigated. Rebound effect, observed in the samples annealed with positive gate bias, is primarily the consequence of a very long-term postirradiation interface-trap buildup. At later annealing times, a significant decrease in the number of interface traps is observed. In order to explain obtained results, we propose a modification to the hydrogen ion transport model for the formation of interface traps. According to our model, H + ions created during irradiation are responsible only for the initial fraction of the total interface-trap buildup. The other fraction is attributed to H + ions produced when molecular hydrogen, released at the SiSiO 2 interface in interface-trap creation reaction, diffuses back into the bulk of the oxide and is cracked at positive charge centres. Simultaneously with the generation of interface traps, their passivation also takes place. Passivation, probably caused by hydrogen atoms and water molecules, becomes predominant at later annealing times, leading to the decrease in interface-trap density.

Radiation-induced interface traps in hardened MOS transistors: an improved charge-pumping study

Different electrical characterization (subthreshold current-voltage measurements, 3-level and multi-frequency charge pumping) combined with isochronal anneals have been used to investigate the generation and the evolution of interface traps in radiation-hardened MOS transistors following exposure to 10 keV X-rays. The evolution of the interface state density (D/sub it/) during the anneal is found to be field-dependent and consistent with models involving a drift of positive species towards the Si-SiO/sub 2/ interface. The energy-resolved distributions of D/sub it/ in the silicon bandgap show the emergence of two broad structures located at /spl sim/E/sub V/+0.35 eV and /spl sim/E/sub V/+0.75 eV immediately after irradiation and during the first steps of the isochronal anneal (up to /spl sim/175/spl deg/C). At higher anneal temperatures, it is shown that the recovery of D/sub it/ is not uniform in the two halves of the silicon bandgap. In particular, the separation of the D/sub it/ distribution related to the lower part of the bandgap in two distinct peaks (at E/sub V/+0.30 eV and E/sub V/+0.45 eV) agrees well with the energy distributions of P/sub b0/ and P/sub b1/ centers. These results are consistent with Electron Spin Resonance (ESR) studies which have shown that P/sub b/ centers play a dominating role in the interface trap build-up and recovery mechanisms. Since ESR measurements are only accurate to /spl sim//spl plusmn/30% in absolute number, P/sub b/ centers do not probably account for all the electrically active interface trap defects, as also suggested by the evident asymmetry of the D/sub it/ distributions in the bandgap. Finally, we investigate the post-irradiation response of border traps by reducing the charge pumping frequency to low values. The implication of these results on the nature of border traps is discussed.

A dose rate independent pMOS dosimeter for space applications

A dual-dielectric pMOS dosimeter (RADFET) has been recently designed at Sandia. The RADFET consists of a thermally grown oxide and a CVD deposited nitride. With a negatively applied bias, holes are generated in the SiO/sub 2/ transport and are trapped at the SiO/sub 2//Si/sub 3/N/sub 4/ interface producing a measurable threshold-voltage shift. Because holes are trapped away from the Si/SiO/sub 2/ interface, hole neutralization by tunneling and interface-trap buildup are minimized resulting in little fade or annealing of the RADFET output response. RADFETs were irradiated at dose rates from 0.002 to 50 rad(Si)/s with biases from -5 to -20 V. RADFETs were also annealed for times up to 10/sup 7/ s at temperatures up to 100/spl deg/C. Within experimental uncertainty, no difference in RADFET output response at a given bias was observed over the dose rate range examined and for 25/spl deg/C anneals. At an anneal temperature of 100/spl deg/C only a 20% decrease in RADFET output response was observed. These results show that Sandia's RADFETs exhibit little or no fade of their output characteristics and are ideal for low dose rate space applications.

Radiation effects at low electric fields in thermal, SIMOX, and bipolar-base oxides

We have performed thermally-stimulated-current (TSC) and capacitance-voltage measurements on 370-1080 nm thermal, SIMOX, and bipolar-base oxides as functions of bias, dose rate, and temperature during irradiation. Base oxides built in a development version of Analog Devices' RF25 process show much more interface-trap buildup than XFCB oxides. Both net-oxide-trap and interface-trap charge densities for RF25 capacitors are enhanced significantly during low-dose-rate or high-temperature irradiation at 0 V over high-rate, 25/spl deg/C exposures. TSC measurements show the increase in net-oxide-trap charge density is due to a decrease in trapped electron density with decreasing dose rate or increasing irradiation temperature (at least to 125/spl deg/C), and not by increased trapped hole density. Similar enhancement of net-oxide-trap and interface-trap charge density with decreasing dose rate is found for soft thermal oxides irradiated at 0 V, but not 5 V. These results strongly suggest that space charge effects associated with holes metastably trapped in the bulk of the oxide can cause the enhanced bipolar gain degradation seen at low dose rates and/or high temperatures in many technologies. No enhanced radiation-induced charge trapping is observed for low-dose-rate or high-temperature, 0 V irradiation of SIMOX capacitors. Implications for hardness assurance tests are discussed.

Analysis of the Processes in Power MOSFETs during γ-Ray Irradiation and Subsequent Thermal Annealing

The processes in n-channel power MOSFETs during γ-ray irradiation and subsequent annealing at elevated temperature are investigated. The creation of positive oxide-trap charge dominates during irradiation, leading to a negative threshold voltage shift. The so-called ‘latent’ interface-trap buildup, observed during annealing, is identified as the main contributor to the threshold voltage rebound. At very late annealing times, a significant decrease in the number of interface traps occurs. Possible mechanisms for the observed effects, as well as their implications for hardness assurance are discussed.

Rebound effect in power VDMOSFETs due tolatent interface-trap generation

The rebound effect, observed in commercial n-channel power VDMOSFETs during biased thermal annealing, following γ-radiation exposure, is analysed. Rebound is caused predominantly by ‘latent’ interface-trap generation, which occurs in transistors irradiated and annealed with positive bias applied to the gate, after initial apparent saturation of the interface-trap density. Latent, interface-trap buildup may cause difficulties in predicting device response in low dose rate environments, such as space.

The improvement of MOSFET prediction in space environments using the conversion model

The modeling of MOS device response to a low dose rate irradiation has been performed. The existing conversion model based on the linear dependence between positive oxide charge annealing and interface trap buildup accurately predicts the long time response of MOSFETs with relatively thick oxides but overestimates the threshold voltage shift for radiation hardened MOSFETs with thin oxides. To give an explanation to this fact. We investigate the impulse response function for threshold voltage. A revised model, which incorporates the different energy levels of hole traps in the oxide improves the fit between the model and data and gives an explanation to the fitting parameters dependence on oxide field.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effects of burn-in on radiation hardness

Transistors and ICs were irradiated with or without pre-irradiation elevated-temperature biased stresses (i.e., burn-in). These stresses lead to larger radiation-induced transistor threshold-voltage shifts and increases in IC static power supply leakage current (two orders of magnitude) in stressed ICs than for ICs not subjected to a stress. In addition, these stresses led to reduced degradation in timing parameters. The major cause of the differences is less radiation-induced interface-trap buildup for transistors subjected to an elevated-temperature biased stress. These results were observed for two distinctly different technologies and have significant implications on hardness assurance testing. One could significantly (1) overestimate degradation in timing parameters resulting in the rejection of acceptable ICs and increased system cost, or (2) underestimate the increase in static supply leakage current of ICs leading to system failure. These results suggest that radiation qualification testing must be performed on integrated circuits that have been subjected to all high-temperature biased stresses experienced in normal production flow or system use. >

Accounting for time-dependent effects on CMOS total-dose response in space environments

Time-dependent charge buildup and annealing processes cause the ionizing radiation response of CMOS devices and circuits to depend strongly on the dose rate of the exposure. Oxide-trap charge annealing and interface-trap buildup in nMOS transistor can lead to positive threshold voltage shifts in a space environment, while negative threshold voltage shifts are commonly observed after irradiations at typical laboratory dose rates [50–300 rad(Si)/s]. Thus, devices that pass laboratory testing can fail at the low dose rates encountered in space due to positive nMOS transistor threshold-voltage shifts above preirradiation values, i.e. “rebound”. We summarize how this issue can be addressed in total-dose hardness assurance test methods for space. An example of such a guideline is the revised U.S. military-standard ionizing-radiation-effects test method (MIL-STD 883D, Test Method 1019.4).

Time-dependence of the interface trap build-up in deuterium-annealed oxides after irradiation

The rate of interface trap Nit build-up after irradiation has been studied in metal-oxide semiconductor oxides which were annealed in either deuterium or hydrogen. The build-up rate is found to be substantially retarded in the deuterium-annealed oxide. This result demonstrates conclusively that the Nit build-up rate is determined by the rate of H+ (D+) drift through the oxide to the Si-SiO2 interface.

Latent interface-trap buildup and its implications for hardness assurance (MOS transistors)

Long-term anneals at temperatures from 25 degrees C to 135 degrees C were performed on irradiated MOS transistors. Following the normal saturation of interface-trap density (within 10/sup 2/ to 10/sup 5/ s after irradiation), large increases in the number of interface traps were observed for both commercial and radiation-hardened transistors at very long times after irradiation (>10/sup 6/ s at 25 degrees ). This latent buildup of interface traps can be significant, up to a factor of four times larger than the normal saturation value. The latent buildup is thermally activated with an activation energy of 0.47+or-0.08 eV. As a natural consequence of the delay between the normal and the latent buildup, there is a window in time in which little or no interface-trap buildup occurs. Two possible mechanisms for the latent buildup are explored: (1) the direct conversion of oxide traps into interface traps or border traps and (2) the diffusion of molecular hydrogen into the gate oxide from adjacent structures. The latent buildup of interface traps can degrade the performance of ICs in space systems and may cause IC failure at long times. Recommendations are provided for characterizing latent interface-trap buildup.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Interface-trap building rates in wet and dry oxides

The time-dependent buildup of radiation-induced interface-trap charge was characterized in polysilicon gate MOS transistors with wet and dry gate oxides with thicknesses varying from approximately 20 to approximately 100 nm. The buildup was characterized in terms of the time required to achieve 50% of the saturated density of interface traps. For both types of oxides, an approximate t/sub ox//sup 0.4/ dependence of the interface-trap buildup rate is observed following +1 MV/cm irradiation and anneal, and an approximate t/sub ox//sup 1.7/ dependence is observed following -1 MV/cm irradiation and +1 MV/cm anneal. The fact that these thickness dependences differ from recent literature reports suggests that the manner in which hydrogen is incorporated in the oxide during processing may play a key role in determining whether H/sup +/ is released in the bulk of the oxide, or near an interface. At any given oxide thickness and irradiation condition, the buildup rate was found to be faster in the dry gate oxides than the wet gate oxides. >

Latent thermally activated interface-trap generation in MOS devices

A large increase in interface-trap density (up to a factor of five) has been observed in commercial MOS devices at very long times after irradiation (>10/sup 6/ s). This latent buildup occurs after an initial apparent saturation of interface-trap density, which occurs typically within approximately 10/sup 2/-10/sup 4/ s after irradiation. The latent buildup is thermally activated. with an activation energy of approximately 0.47 ev. Within experimental uncertainty, this is equal to the activation energy ( approximately 0.45 eV) for the diffusion of molecular hydrogen in bulk fused silica. Latent interface-trap buildup can degrade the performance of devices in low-dose-rate radiation environments (e.g. space). >