Interface Chip Research Articles

An ASIC-based system-in-package MEMS gas sensor with impedance spectroscopy readout and AI-enabled identification capabilities

The main advantages of micromachined metal oxide semiconductor (MOX) gas sensors, in particular their low cost, high sensitivity, miniaturization and low power consumption, are compromised by lack of selectivity and long-term sensor signal drifts, which often hinder their application in real-world sensing applications. To increase the sensor data dimensionality, temperature cycled operation (TCO) and impedance spectroscopy (IS) readout was proposed, enabling the acquisition of large datasets from a single sensor, as suitable to be exploited by machine learning techniques. Furthermore, recent studies have shown how the IS readout minimizes the issues represented by the sensor long-term signal drift.The aim of this work is the development of a smart system-in-package, integrating a state-of-the-art micromachined MOX gas sensor based on a wafer-level nanostructured sensing layer with a novel versatile sensor interface chip, capable of high performance IS readout. We propose a miniaturized sensing device, which is a small, lightweight low power consumption chemical sensing micro-system with fast and accurate classification capabilities, suitable to be deployed in long multi-node sensing cables or on unmanned aerial vehicles. A software suite comprising a sensor training wizard was also developed, enabling users with no technical background to train the sensing system.

A 382nVrms 100GΩ@50Hz Active Electrode for Dry-Electrode EEG Recording.

This article describes a low noise and ultra-high input impedance active electrode (AE) interface chip for dry-electrode EEG recording. To compensate the input parasitic capacitance and the ESD leakage, power/ground/ESD bootstrapping is proposed. This design integrates chopping stabilization technique to suppress flicker noise of the amplifier which has never been tackled in previous bootstrapped AE design. Both on-chip and off-chip input routing is active shielded to minimize wire parasitic. Fabricated in a 0.18μm CMOS process, the AE core occupies about 0.056mm2 and draws 17.95μA from a 1.8V supply. The proposed AE achieves 100GΩ input impedance at 50Hz and over 1GΩ at 1kHz with a low input-referred noise of 382nVrms integrated from 0.5Hz to 70Hz. This design is the first 100GΩ@50Hz input impedance chopper stabilized AE compared to the state-of-the-art. Dry-electrode EEG recording capability of the proposed AE are verified on three types of experiments including spontaneous α-wave, event related potential and steady-state visual evoked potential.

A Low-Intensity Pulsed Ultrasound Interface ASIC for Wearable Medical Therapeutic Device Applications

Low-intensity pulsed ultrasound (LIPUS) is a non-invasive medical therapy that has attracted recent research interest due to its therapeutic effects. However, most LIPUS driver systems currently available are large and expensive. We have proposed a LIPUS interface application-specific integrated circuit (ASIC) for use in wearable medical devices to address some of the challenges related to the size and cost of the current technologies. The proposed ASIC is a highly integrated system, incorporating a DCDC module based on a charge pump architecture, a high voltage level shifter, a half-bridge driver, a voltage-controlled oscillator, and a corresponding digital circuit module. Consequently, the functional realization of this ASIC as a LIPUS driver system requires only a few passive components. Experimental tests indicated that the chip is capable of an output of 184.2 mW or 107.2 mW with a power supply of 5 V or 3.7 V, respectively, and its power conversion efficiency is approximately 30%. This power output capacity allows the LIPUS driver system to deliver a spatial average temporal average (SATA) of 29.5 mW/cm2 or 51.6 mW/cm2 with a power supply of 3.7 V or 5 V, respectively. The total die area, including pads, is 4 mm2. The ASIC does not require inductors, improving its magnetic resonance imaging (MRI) compatibility. In summary, the proposed LIPUS interface chip presents a promising solution for the development of MRI-compatible and cost-effective wearable medical therapy devices.

Broadside-Coupled Niobium Flexible Cables

We have developed fine-pitch, multilayer, superconducting wiring for routing around a ninety-degree corner terminated with wirebonding interfaces. The component-level testbed for the Advanced Telescope for High Energy Astrophysics (ATHENA) X-Ray Integral Field Unit (X-IFU) focal plane requires compact, high-density, low-crosstalk wiring fanout to connect the detectors in the focal plane array with NIST-fabricated SQUID time domain multiplexing (TDM) readout chips. The full assembly baselines two interface chips: a flexible interface chip bending around the corner and a planar silicon carrier chip. The TDM readout is indium bump-bonded to the silicon carrier and afterward the flexible chip is clipped in place and wirebonded to the detector and fanout wiring on the carrier. This assembly is repeated for each side of the hexagonal focal plane structure. As conventional commercial cables are not able to achieve the fine-pitch, low-crosstalk, superconducting wiring required, we fabricate these flexible interface chips in-house via lithographic patterning and etching of sputter deposited thin films to create broadside-coupled superconducting niobium microstrips. Within the chip, the wiring on the flexible polyimide region transitions to silicon substrate for the closely spaced wirebond pads. The Nb microstrip wiring climbing a thick polyimide sidewall presents a fabrication challenge which we shall discuss in this paper. We describe the function of these components to build an effective engineering testbed for the ATHENA X-IFU.

A CNN-Based E-Nose Using Time Series Features for Food Freshness Classification

In this article, a convolutional neural network (CNN)-based electronic nose system is proposed, which utilizes time series features to classify the freshness of food. The electronic nose is composed of three elements: a highly sensitive miniaturized micro-electromechanical systems (MEMS) metal–oxide (MOX)–semiconductor gas sensor array, a complementary metal–oxide–semiconductor (CMOS) integrated circuit, and a CNN-based classification unit. The gas sensors exhibit exceptional sensitivity, low power consumption, and a small size. The interface circuit for sensor readout is fabricated using a standard 180-nm CMOS process, with an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.5$ </tex-math></inline-formula> mm. The interface chip mainly consists of an analog-to-digital converter (ADC), an electrically erasable programmable read-only memory (EEPROM), an oscillator (OSC), power management, a heater driver, and a digital control circuit. Fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}{(}{t}{)}$ </tex-math></inline-formula> exposures are taken at specific intervals under gas input and output conditions. Time series features are extracted from a diverse set of sensor signals, which allows the subtle differences in various food odors at different freshness levels to be identified. The incorporation of time series feature extraction extends the data features, resulting in enhanced classification accuracy with a limited number of sensors. An abstract odor map input to the CNN is formed by combining the steady-state and transient information of the gas sensor response. The final freshness classification accuracy of 20 types of foods is 97.3%. The accuracy is improved by 6.5% after the implementation of time series feature extraction, demonstrating the significance of instantaneous fluctuation information for classification accuracy.

LFP polarity changes across cortical and eccentricity in primary visual cortex.

Local field potentials (LFPs) can evaluate neural population activity in the cortex and their interaction with other cortical areas. Analyzing current source density (CSD) rather than LFPs is very significant due to the reduction of volume conduction effects. Current sinks are construed as net inward transmembrane currents, while current sources are net outward ones. Despite extensive studies of LFPs and CSDs, their morphology in different cortical layers and eccentricities are still largely unknown. Because LFP polarity changes provide a measure of neural activity, they can be useful in implanting brain-computer interface (BCI) chips and effectively communicating the BCI devices to the brain. We hypothesize that sinks and sources analyses could be a way to quantitatively achieve their characteristics in response to changes in stimulus size and layer-dependent differences with increasing eccentricities. In this study, we show that stimulus properties play a crucial role in determining the flow. The present work focusses on the primary visual cortex (V1). In this study, we investigate a map of the LFP-CSD in V1 area by presenting different stimulus properties (e.g., size and type) in the visual field area of Macaque monkeys. Our aim is to use the morphology of sinks and sources to measure the input and output information in different layers as well as different eccentricities. According to the value of CSDs, the results show that the stimuli smaller than RF's size had lower strength than the others and the larger RF's stimulus size showed smaller strength than the optimized stimulus size, which indicated the suppression phenomenon. Additionally, with the increased eccentricity, CSD's strengths were increased across cortical layers.

Biomedical materials benefit health

Biomedical engineering is acclaimed as the most effective technological advancement—the stepping- stone toward better human health. An in-depth look into biomedical engineering reveals that emerging materials are recognized as the turbocharger for its progress and the source of innovation. For example, the application of advanced nanomaterials in drug delivery, bioimaging, gene therapy, and so on are pioneering new ways to diagnose and treat cancer and other diseases; tissue repair and organ regeneration are no longer dreams, but attainable miracles because of 3D bioprinted scaffold materials; flexible electronic materials and brain-computer interface chips remove barriers in human-computer interaction, enabling scientists to better interpret the mysteries of life. In addition, functional materials construct diverse diagnosis and treatment equipment, such as microfluidics and major medical devices. Evolving from the deep integration of materials science and biomedical engineering, this popular and innovative research field will enormously benefit people's life and health. Upholding the philosophy of “BME Materials Benefit Health,” BMEMat was launched under the auspices of Shandong University and Wiley. With a commitment to building the most valuable international platform to share knowledge and information, BMEMat covers all research advances related to functional materials for biomedical applications. The article types include Original Articles, Review Articles, Editorials, Short Communications, and Letters to the Editor (author guidelines are available at https://onlinelibrary.wiley.com/page/journal/27517446/homepage/author-guidelines). BMEMat adopts an open-access publishing model and will expand the coverage of Wiley's current materials science journals into biomedical engineering. BMEMat creates an active community by attracting interdisciplinary research in biomedical engineering and materials science. Our professional editorial board comprises the most experienced scientists in the BME field. The Editor-in-Chief, Prof. Hong Liu from State Key Laboratory of Crystal Materials, Shandong University, is the winner of National Outstanding Youth Fund and is among the world's highly-cited scientists. We have nine Associate Editors on board to assist the Editor-in-Chief to expediate the peer review process: Prof. Xiaogang Liu from the National University of Singapore (Singapore), Prof. Wenbo Bu from Fudan University (China), Prof. Chuanbin Mao from University of Oklahoma (USA), Prof. Fan Yi from Shandong University (China), Prof. Andreu Cabot from Catalonia Institute for Energy Research (Spain), Prof. Xiaohu Gao from University of Washington, Seattle (USA), Prof. Angus Johnston from Monash University (Australia), Prof. Xingjie Liang from University of Chinese Academy of Sciences (China), and Prof. Xuebin Yang from University of Leeds (UK). The elite editorial team with their diversity of insights and expertise will provide efficient peer review services and post-acceptance processes to our authors and reviewers, and present our readers with the most important, in-depth, and frontier basic and applied research achievements. We sincerely look forward to welcoming you—as a reader, author, reviewer or commenter—to engage with our journal. We believe that BMEMat will become one of the leading international publishing platforms in the interdisciplinary area of material science, biochemistry, biology, biomedical engineering, and medicine, by providing information on the most important advances in this field to a broader group of researchers and engineers from both academia and industry. The authors declare no conflicts of interest.

A Real-Time Data Acquisition System for Single-Band Bathymetric LiDAR

Bathymetric light detection and ranging (LiDAR), which uses a laser with narrow pulse width and a high-repetition-rate, requires a real-time data acquisition system (RTDAQS) for quickly transmitting data with the characteristic of high sampling rates, high resolution and high accuracy. However, none of the RTDAQS in the world has reached these requirements. For this reason, this paper presents a RTDAQS with high speed SerDes data transfer technology based on the architecture of ADC+FPGA+ZYNQ. This RTDAQS consists of acquisition board and storage board. The acquisition board integrates high-speed analog-to-digital converter (ADC) acquisition module, Input/Output (I/O) control module, data transmission module, and Field Programmable Gate Array (FPGA) chip module. The storage board integrates FPGA Mezzanine Card (FMC) interface, solid state and ZYNQ chips. The corresponding software includes configuration for high-speed ADC acquisition module, I/O control module, data transmission module, and FMC interface module. The RTDAQS, which is embedded in the LiDAR with laser pulses width of 2.5ns ± 0.2ns and frequency of 500 Hz, has been verified by the experiments in indoor sink, outdoor pond, river, reservoir, Beihai Bay of the Pacific Ocean. The experimental results and comparison experiments demonstrate that the presented RTDAQS can reach a sampling rate of 2 GSPS and a sampling resolution of 14 bits and a sampling accuracy of 6 LSB with an acquisition error within 0.1 m, which meet the demands of high sampling rate with high accuracy data acquisition and quick data transmission in practice and can be applied to various devices.

Switch-Beam Antenna Techniques for Bridge Structural Health Monitoring With GaAs-Based Solar Energy Harvesting

<bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The structural health monitoring (SHM) of bridges with wireless sensor networks (WSNs) is addressed by leveraging two distinct but interrelated aspects: GaAs-based solar energy harvesting and switched-beam antenna strategies in combination with asynchronous media access control (MAC) protocols. The joint optimization of solar energy harvesting and switched-beam directional antennas at the nodes is considered and compared with an equivalent omnidirectional antenna network. To address the limited energy budget in battery-based sensor nodes which is a serious limitation in long-lived applications such as bridge SHM, an efficient solar harvesting solution is put forth based on the good performance of GaAs cells even under low-light conditions. Given the current state of the art in GaAs cells, single-junction cells were selected due to the cost of double-or triple-junction versions. The simulation model includes the residual energy capacity with GaAs-based solar energy harvesting of actual selected components (microcontroller, radio interface chip). The model was implemented on top of the Omnet<inline-formula> <tex-math notation="LaTeX">$++$</tex-math> </inline-formula> and Silvaco Atlas simulator. The comparative study in this article provides insights into realistic bridge SHM sensor networks, leveraging solar energy harvesting and switched-beam antennas.</b>

Machinability investigation of Chromoly steel using TiN/Al2O3/TiCN/TiOCN multilayer coated tungsten carbide tool inserts with artificial neural network methodology

AbstractEnhancing the machining efficiency of hardened steel using four‐layer coated tungsten carbide tools has gained a lot of interest among manufacturing engineers. This paper reports the machining performance of AISI 4140 steel using TiN/Al2O3/TiCN/TiOCN multilayer coated tungsten carbide tool inserts. The impact of cutting speed, depth of cut, and the nose radius on machining force, tool chip interface temperature, surface roughness, and chip forms was ascertained using full factorial machining experiments and artificial neural network (ANN) methodology. The machining force evaluated using Logistic Sigmoid activation function resulted in the highest root mean square error (RMSE) of 4.076 and regression value of 0.998. The maximum error between the ANN predicted results and experimental results for machining force, cutting temperature and surface roughness was about 2.4%, 5.3%, and 2.07%, respectively. The best architecture for ANN was “3‐6‐4” which had a coefficient of regression value of 0.97. However, in case of chip form, some of the ANN predicted values could not be mapped to ISO standard chip form and hence prediction accuracy of 80% was achieved.

A Mode-Matched DRG Realized by Monolithic Integrated Interface Circuit Design

This article proposes a novel design method for the mode-matched disk resonator gyroscope (DRG) realized by the monolithic integrated interface circuit. The mode-mismatched dynamics model of DRG is simplified by introducing the analysis method of “slow” dynamics, the effect of mode mismatching is quantified, and the automatic mode-matched interface circuit is designed based on the analysis of the simplified model. The force-rebalance loop is designed based on a self-clock circuit that releases the chip from the dependence on external clocks, avoids the design of multipliers, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs), and improves the integration of the chip. The highly integrated automatic mode-matching loop is realized by the designing of a quadrature loop and stiffness tuning loop on the basics of the mode-matching theory. The design method is applied to develop a monolithic integrated interface chip of DRG with an area of 4.2 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times4.3$ </tex-math></inline-formula> mm and power consumption of 90 mW. The DRG integrated circuit achieves the bias instability (BI) of 0.38°/h and the angle random walk (ARW) of 0.0354°/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd \text{h}$ </tex-math></inline-formula> within a full scale of ±300°/s, which provides a highly integrated circuit design scheme for DRG’s extensive application.

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

In order to solve the problems of small signal acquisition range and poor acquisition accuracy of the existing multichannel acquisition system, a multisensor energy data fusion transformer acquisition system simulation method based on FPGA is proposed, and key hardware functions are designed and implemented. The system uses FPGA to control the core logic, synchronously collects and controls the energy data of the CCD camera and the laser rangefinder, organizes and uses an external large-capacity SDRAM group for buffering, and uses a dedicated PCI interface chip PLX9656 to achieve high-speed data transmission. Two pieces of sensor energy data and PCI bus energy data are stored in real time using a large-capacity disk array composed of multiple SATA hard disks. The function and performance of the energy data acquisition and storage system were tested. After the actual system test, the experimental results show that the transmission speed of the system through the PCI bus exceeds 200 MB/s, the writing speed of the continuous disk array is 240 MB/s, and the real-time acquisition and recording speed is 100 MB/ss. Conclusion. The system effectively solves the problems of high-speed data acquisition and storage and large capacity data transmission of key sensor nodes.

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300°C

Abstract Sensors are the key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently, the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow the reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project “eHarsh” to overcome this hurdle. In the course of the project, an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor fron-tend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high-temperature 0.35-micron SOI-CMOS technology focusing operating temperatures up to 300°C. The chipset is assembled on a multilayer ceramic low-temperature cofired ceramics (LTCC) board using flip chip technology. The ceramic board consists of four layers with a total thickness of approximately 0.9 mm. The internal wiring is based on silver paste while the external contacts were alternatively manufactured in silver (sintering/soldering) or in gold alloys (wire bonding). As an interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high-quality flip chip interconnects can be generated.

Compact dual-polarization silicon integrated couplers for multicore fibers.

Compact fiber-to-chip couplers play an important role in optical interconnections, especially in data centers. However, the development of couplers has been mostly limited to standard single-mode fibers, with few devices compatible with multicore and multimode fibers. Through the use of state-of-the-art optimization algorithms, we designed a compact dual-polarization coupler to interface chips and dense multicore fibers, demonstrating, for the first time, coupling to both polarizations of all the cores, with measured coupling efficiency of -4.3dB and with a 3 dB bandwidth of 48 nm. The dual-polarization coupler has a footprint of 200µm2 per core, which makes it the smallest fiber-to-chip coupler experimentally demonstrated on a standard silicon-on-insulator platform.

A Device Performance Data Acquisition System Based on Data Fusion Method

The data acquisition system is a system which collects the analog signal from the sensor, converts it into digital signal, then sends it to the computer for processing, and outputs the processing results in the form of demand. Based on the research of USB technology, this paper describes a data acquisition system based on data fusion technology, including hardware design, firmware design, device driver design and host application design. In the part of hardware design, this paper first describes the performance and characteristics of data acquisition chip, FPGA and USB2.0 interface chip, and then gives the specific hardware design scheme. In the part of firmware design, this paper first introduces the firmware architecture of FX2, and then introduces the firmware design of GPIF interface mode in detail. In the driver development part, this paper first introduces the WDM driver development model, and then completes the USB device driver design of the data acquisition system. Finally, the device performance data acquisition system based on data fusion method is completed with driver.

Bimodal neural probe for highly co-localized chemical and electrical monitoring of neural activities in vivo

Investigation of the chemical and electrical signals of cells in vivo is critical for studying functional connectivity and brain diseases. Most previous studies have observed either the electrical signals or the chemical signals of cells because recording electrical signals and neurochemicals are done by fundamentally different methods. Herein, we present a bimodal MEMS neural probe that is monolithically integrated with an array of microelectrodes for recording electrical activity, microfluidic channels for sampling extracellular fluid, and a microfluidic interface chip for multiple drug delivery and sample isolation from the localized region at the cellular level. In this work, we successfully demonstrated the functionality of our probe by monitoring and modulating bimodal (electrical and chemical) neural activities through the delivery of chemicals in a co-localized brain region in vivo. We expect our bimodal probe to provide opportunities for a variety of in-depth studies of brain functions as well as for the investigation of neural circuits related to brain diseases.

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300 °C

Abstract Sensors are key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow a reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project ‘eHarsh’ to overcome this hurdle. In the course of the project an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor frontend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high temperature 0.35 micron SOI-CMOS technology focusing operating temperatures up to 300 °C. The chipset is assembled on a multilayer ceramic LTCC-board using flip chip technology. The ceramic board consists of 4 layers with a total thickness of approx. 0.9 mm. The internal wiring is based on silver paste while external contacts were alternatively manufactured in silver (sintering/soldering) or in gold-alloys (wire bonding). As interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high quality flip chip interconnects can be generated.

Direct observations of tribological behavior in cutting with textured cutting tools

As widely reported in the literature, the micro-texturing technique has a significant potential to improve the performance of cutting tools by reducing cutting forces, friction, temperature, and tool wear, and further, by improving tribological behavior at the tool-chip and tool-workpiece interface. However, it is also known that the effects of textures on the cutting tool surface strongly depend on the texture geometry and dimensions, and that the application of indiscriminate surface textures to cutting tools often results in adverse effects on cutting performance, indicating that an improved understanding of surface phenomena is required to further develop textured cutting tools. This paper summarizes recent advances in tool surface texturing in metal cutting fields, and continues to describe how the textured surface of a cutting tool influences the deformation fields of the workpiece material, including both primary and secondary shear zones, by means of direct in-situ observation using particle image velocimetry analysis to understand the behavior in the vicinity of the textured surfaces during the cutting process. The experimental results with the textured cutting tool reveal that the effect of the grooved rake face on the cutting force differs depending on the relative position of the microgroove with respect to the undeformed chip thickness. The friction condition and where the texture is located determine the performance of the surface texture. The link between the interface friction and chip flow mode is discussed, and it is demonstrated that surface textures can alter the chip flow mode from a segmented flow with redundant deformation to a steadier homogeneous flow with lower cutting energy.

Retracted] Research on Recognition Method of Basketball Goals Based on Image Analysis of Computer Vision

Moving target detection is involved in many engineering applications, but basketball has some difficulties because of the time‐varying speed and uncertain path. The purpose of this paper is to use computer vision image analysis to identify the path and speed of a basketball goal, so as to meet the needs of recognition and achieve trajectory prediction. This research mainly discusses the basketball goal recognition method based on computer vision. In the research process, Kalman filter is used to improve the KCF tracking algorithm to track the basketball path. The algorithm of this research is based on MATLAB, so it can avoid the mixed programming of MATLAB and other languages and reduce the difficulty of interface design software. In the aspect of data acquisition, the extended EPROM is used to store user programs, and parallel interface chips (such as 8255A) can be configured in the system to output switch control signals and display and print operations. The automatic basketball bowling counter based on 8031 microprocessor is used as the host computer. After the level conversion by MAX232, it is connected with the RS232C serial port of PC, and the collected data is sent to the workstation recording the results. In order to consider the convenience of user operation, the GUI design of MATLAB is used to facilitate the exchange of information between users and computers so that users can see the competition results intuitively. The processing frame rate of the tested video image can reach 60 frames/second, more than 25 frames/second, which meet the real‐time requirements of the system. The results show that the basketball goal recognition method used in this study has strong anti‐interference ability and stable performance.

Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces.

This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13[Formula: see text] CMOS process. To reduce thermal noise folding ratio, and suppress kT/C noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress kT/C noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and In-Vivo experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8[Formula: see text] from 1[Formula: see text] to 300[Formula: see text], and 2.3[Formula: see text] from 300[Formula: see text] to 8 kHz respectively, and In-Vivo experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20[Formula: see text]. In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.