Board Interconnects Research Articles

Broadband packaging solution in embedded wafer level ball grid array technology for D-band PMCW radar

Abstract A system-in-package for a wideband digital radar, in D-band, requires broadband, high-gain antennas combined with broadband chip-to-package and package-to-printed circuit board (PCB) interconnects. This paper demonstrates a wideband, low-loss quasi-coaxial signal transition, and a novel electric split ring resonator (eSRR)-based antenna-in-package (AiP) with a modified reflector concept, for improved gain, in embedded wafer level ball grid array (eWLB) technology. A complete chip-to-package-to-PCB interconnect is also demonstrated by combining the quasi-coaxial transition with a chip-to-package interconnect. The quasi-coaxial signal transition has the largest impedance bandwidth among ball grid array-based quasi-coaxial signal transitions. For the modified reflector concept, a horn-shaped cavity is micromachined in the PCB substrate and remetallized with aerosol-jet printing, placing the reflector 0.25λ from the antenna. The antenna gain is improved with up to 5.3 dB. The AiP with the horn-shaped reflector is the single element with the highest gain, in eWLB technology, above 100 GHz.

224-Gbit/S 4-PAM Operation of Compact DC Block Circuit Integrated Hi-FIT AXEL Transmitter With Low Power Consumption

We previously developed a semiconductor optical amplifier (SOA) assisted extended reach electroabsorption modulator integrated distributed feedback (EADFB) laser (AXEL) to increase the optical modulation output power and a high-frequency integrated design based on the flip-chip interconnection technique (Hi-FIT) to obtain a high modulation bandwidth. We achieved a high-output power 224-Gbit/s 4-level pulse-amplitude-modulation (4-PAM) operation of a Hi-FIT AXEL module. In this paper, we developed a compact DC block circuit integrated into Hi-FIT AXEL module to decrease chip-power consumption without increasing the sub-assembly size and degrading the modulation bandwidth. We designed a Hi-FIT AXEL sub-assembly, that include a flip-chip interconnection board with a DC block circuit that affects the modulation bandwidth. We achieved a 3-dB bandwidth of up to 64 GHz for this designed sub-assembly. The fabricated Hi-FIT AXEL module has a 3-dB bandwidth of more than 62 GHz and a flat frequency response up to 50 GHz. For the 224-Gbit/s 4-PAM operation, the fabricated Hi-FIT AXEL module has a chip-out average output power of +10.0 dBm with a transmitter eye-closure quaternary (TECQ) of 1.9 dB. The integrated compact DC block circuit can reduce chip power consumption by up to 17%.

Board Level Reliability of Flipchip Package

In the world of electronic materials, solder is a critical material that plays an important role in the first level (silicon to package substrate) and second level (package to printed circuit board) interconnection. As a joining material in electronic assemblies, solder provides electrical and mechanical connections. The increasing need for reliable electronic devices for harsh environment triggers the need for reliable solder joints. This study focuses on reliability of second level interconnections between package and printed circuit boards. Board level temperature cycling and mechanical drop performance of a 15 mm x 15 mm FCBGA test vehicle were evaluated with different package construction (lidded vs non-lidded), and BGA solder alloys (SA1, SA2, and SA3). Daisy chain packages were assembled on 1.0 mm thick PCB. Mounted units were thermally cycled between from -40C to 125C. Additional samples were evaluated in mechanical drop test conditions following JEDEC standards. Results showed that packages with SA2, and SA3 BGA had significantly higher board-level thermal cycling life compared to SA1. The best drop performance was achieved with SA1 solder. The performance trend among different solder alloys was found to be similar between lidded vs non lidded package. However, lidded package showed improved board-level reliability performance compared to a non-lidded package.

The preparation of anisotropic conductive paste and its application in FOB interconnection

PurposeThe purpose of this study is to investigate the reliability of flex-on-board (FOB) interconnection connected with an anisotropic conductive paste (ACP), which is prepared by dispersing nickel balls in the epoxy-curing system.Design/methodology/approachDifferential scanning calorimetry was used to evaluate the curing characteristics of the paste. And the contact resistances of bonding joints and 90º peel adhesion were tested before and after high temperature and high humidity test (85°C, 85% humidity), thermal cycling (−45°C∼125°C, 30min/cycle) and pressure cooker test (PCT, 121°C, 100% humidity 2 atm) to evaluate the flex on board (FOB) interconnection reliability.FindingsIt is found that FOB test vehicles have been successfully bonded by using ACP for the first time. And the ACP bonding joint of FOB has good reliability and can meet the requirements of FOB interconnection. Compared with conventional anisotropic conductive film (ACF), this ACP interconnection provides higher adhesion strength, higher joint current carrying capability and higher reliability performance and lower cost for FOB interconnection.Originality/valueACP is applied in the interconnection of FOB. It has the higher reliability performance and lower cost for than the conventional ACF.

A Compact On-Chip Pad Structure With an Embedded Capacitor for Broadband Millimeter-Wave Bond-Wire Interconnection

This article presents a compact on-chip pad structure with an embedded capacitor for millimeter-wave bond-wire interconnection, which is realized by 65-nm complementary metal–oxide–semiconductor (CMOS) process and able to compensate the parasitic inductance introduced by bonding wires. The proposed pad structure implemented by metal stacking is equivalent to an on-chip series capacitor. Moreover, a deep N-well structure is loaded at the bottom of the pad to reduce the parasitic pad-to-ground capacitance. This pad structure has been applied to the chip-to-chip interconnection with a measured minimum insertion loss (IL) of 2.179 dB and a measured 3-dB bandwidth of 11.9 GHz from 35.6 to 47.5 GHz. In addition, it has been applied to the chip-to-printed circuit board (PCB) interconnect ion with a measured one-sided loss of 1.7475 dB and a measured 3-dB bandwidth of 12 GHz from 22.7 to 34.7 GHz. Both applications using bond-wire interconnections prove that the proposed pad structure can compensate bond-wire inductance and realize broadband low-loss impedance matching.

Electrochemical behavior of through-hole electrodeposition inhibitor EO-PO under periodic pulse reverse

Uniform electrodeposition of through-hole (TH) with a high aspect ratio is the key to the reliability of printed circuit board (PCB) interconnection. Inhibitors produce stronger inhibition at high potentials during TH electrodeposition and thus reduce the difference in electrodeposition rates between inside and outside the TH. In this paper, the electrochemical behavior of an ethylene oxide propylene oxide random copolymer (EO-PO) as an inhibitor on the cathode during periodic pulse reverse (PPR) electrodeposition was systematically studied. The results show that EO-PO will rotate under the effect of reverse pulse, and adsorb more strongly on the cathode surface, which inhibits the "cathode stripping" process of the reverse pulse. Through the electrodeposition experiments, compared with direct current (DC) electrodeposition, the PPR method effectively eliminates the copper nodule and improves the concentration window of EO-PO. The results pave the way for regulating and controlling TH electrodeposition with other additives.

Silicon circuits for chip‐to‐chip communications in multi‐socket server board interconnects

Multi-socket server boards (MSBs) exploit the interconnection of multiple processor chips towards forming powerful cache coherent systems, with the interconnect technology comprising a key element in boosting processing performance. Here, we present an overview of the current electrical interconnects for MSBs, outlining the main challenges currently faced. We propose the use of silicon photonics (SiPho) towards advancing interconnect throughput, socket connectivity and energy efficiency in MSB layouts, enabling a flat-topology wavelength division multiplexing (WDM)-based point-to-point (p2p) optical MSB interconnect scheme. We demonstrate WDM SiPho transceivers (TxRxs) co-assembled with their electronic circuits for up to 50 Gb/s line rate and 400 Gb/s aggregate data transmission and SiPho arrayed waveguide grating routers that can offer collision-less time of flight connectivity for up to 16 nodes. The capacity can scale to 2.8 Gb/s for an eight-socket MSB, when line rate scales to 50 Gb/s, yielding up to 69% energy reduction compared with the QuickPath Interconnect and highlighting the feasibility of single-hop p2p interconnects in MSB systems with >4 sockets.

TAN modelling of HH-shape microstrip interconnect tree

This paper develops an unfamiliar modelling of printed circuit board (PCB) interconnect behaving as HH-tree. The developed model is based on the tensorial analysis of networks (TAN) formalism. The HH-tree is implemented with the equivalent LC-network based on Hammerstad-Jensen modelling. The unfamiliar TAN methodology is described by starting from the equivalent graph topology. The HH-tree TAN model is established from the branch and mesh spaces implementation of voltage, current and impedance tensorial objects. Then, the HH-tree PCB problem is reformulated with the tensorial electrical system metric. The solution of the metric problem is validated with commercial tool simulation from DC up to 2.5 GHz with a microstrip circuit proof-of-concept. As expected, computed and simulated results are in good agreement.

Stepped laser-ablation fabrication of concave micromirrors in rectangular optical waveguides for low loss vertical coupling.

In this report, we present a stepped laser-ablation method for the fabrication of concave micromirrors in rectangular optical waveguides. The numerically simulated vertical coupling loss of the reflection of the concave micromirror can be reduced to 1.53 dB. The processing parameters of the utilized excimer laser, such as the step number, width, and depth, were optimized to fabricate the concave micromirrors. After the thermal reflow process, the measured curve of the circular concave micromirrors obtained using a 3D optical profiler agreed well with a standard circle with a surface roughness of 39.56 nm. Furthermore, vertical coupling for 62.5 µm MMF revealed that the loss of the circular concave micromirror coated with a 50 nm thick Au film is as low as 1.83 dB, corresponding to a high coupling efficiency of 65.61%. This new, convenient, and efficient fabrication technology for the fabrication of concave micromirrors can be applied to vertical coupling for optical printed circuit board (OPCB) interconnection technology.

Standard development update: IEEE P370 — electrical characterization of printed circuit board and related interconnects at frequencies up to 50 GHz

The IEEE P370 standard development achieved a critical milestone in 2019 when the first ballot was conducted. The ballot return rate was 97%, and the approval rate was 92%, well above the requirement for return rate and approval rate. I would like to use this opportunity to thank the IEEE P370 working group and task-group officers and members for their several years of dedicated hard work since 2015!

Stretchable strain-tolerant soft printed circuit board: a systematic approach for the design rules of stretchable interconnects

ABSTRACTReported herein is a stretchable strain-tolerant soft printed circuit board (SPCB) following optimized circuit design rules. Inkjet-printed interconnects with a wrinkled structure and rigid epoxy patterns allow the outstanding stretchability and strain distribution controllability of the SPCB, respectively. The prototype circuits show reliable operation under various mechanical deformations, even in the 180° folding state and the irregular deformed state with 25% tensile strain. This research paves a promising route for the realization of highly reliable soft printed circuits with a high degree of design freedom, which can thus be used for driver chip mounting or driver board interconnection for the stretchable display applications.

Design of microstrip ultrafast pulses interconnect for THz-analog and digital applications

In this article, the propagation characteristic of transient pulses over the designed microstrip THz interconnects by various conducting materials is analyzed. The Fourier inverse transformation approach is used to visualize the effect of propagation of transient pulses over THz interconnects made by the various conducting materials which are widely used in Complementary Metal Oxide Semiconductor (CMOS) technology named Copper, Gold, Aluminum, Tungsten, Tungsten-Silicide (W-Si2) and Poly-Si respectively. All parameters of transient pulse like rising time, fall time, propagation delay, settling time, overshoot, undershoot and ringing, etc. have calculated using the proposed circuit model and it has been verified with Finite Elements Method based EM-Simulation results. The distortion due to geometrical dispersion is significant; while a loss could be an important factor depending on the dielectric loss of the substrate. This information could be useful in designing both on board and on-chip interconnects. The proposed circuit model of microstrip THz interconnects and algorithmic frameworks proved the usefulness of rapid design, which is extremely challenging when using conventional methods. To the awareness, this is the attempt to efficient solving of this type of design problems; especially in the context of explicit THz interconnect design for CMOS technology.

Performance of the CMS ECAL data acquisition system at LHC Run II

Abstract During 2017, the Large Hadron Collider provided proton–proton collisions up to an integrated luminosity of 50/fb and the Compact Muon Solenoid (CMS) experiment was able to record 90.3% of this data. The electromagnetic calorimeter (ECAL) of CMS was able to achieve excellent data collection efficiency owing to its reliable data acquisition (DAQ) system. The modular and scalar schema followed by the ECAL DAQ system means that ECAL crystals are divided in sectors, each of which is controlled by three interconnected boards. A multi-machine distributed software configures the electronic boards and follows the life cycle of the acquisition process. The increase in instantaneous luminosity during Run II has resulted in an increase in the number of occasional errors due to radiation effects. To combat this, ECAL DAQ has been equipped with automatic recovery procedures and monitoring services.

EMC standards activity

In this issue of the EMC Magazine, this column reviews what is involved in EMC Society standardization including examples of the EMC Society Standards Committee scopes and activity as seen by the leadership of the activity. Part of their contribution is to ask for assistance in technical work and part is seeking out more involvement with other standards developers that generate EMC standards outside of the IEEE. So you are encouraged to read the complete articles herein to see where an activity lies that you can contribute to or at least follow. We also provide an example of the work on a particular standard and describe the technical needs. For that, scroll down to the description of the work on P370, which is entitled: IEEE draft electrical characterization of printed circuit board and related interconnects at frequencies up to 50 GHz.

InGaAs/GaAsP strain quantum well spatial light modulator with low voltage and high contrast ratio

We report a spatial light modulator (SLM) which consisted of 40 pairs of InGaAs/GaAs/GaAsP multiple-quantum wells (MQWs) that embedded in an asymmetric Fabry-Perot (FP) cavity formed by highly reflective back distributed Bragg reflectors (DBRs) and moderate reflective top DBRs. The center wavelength of FP cavity was designed to have a 20 nm redshift in comparison to the luminescence peaks of MQWs. The relationship between optical absorption spectrum of MQWs and the applied negative voltages was modeled based on the quantum-confined stark effect (QCSE). Large area SLMs with 3 mm diameter were fabricated, which exhibited a high contrast ratio of 12:1 at ≃940 nm with only 2 V bias. The QCSE effect varying with the applied voltage and the cavity resonant wavelength shifting with the incident angle were also analyzed theoretically and experimentally. The device is promising to improve system performance and reduce power consumption of fast emerging high-speed data transmission within data centers and short board to board interconnects.

Machine Learning for the Performance Assessment of High-Speed Links

This paper investigates the application of support vector machine to the modeling of high-speed interconnects with largely varying and/or highly uncertain design parameters. The proposed method relies on a robust and well-established mathematical framework, yielding accurate surrogates of complex dynamical systems. An identification procedure based on the observation of a small set of system responses allows generating compact parametric relations, which can be used for design optimization and/or stochastic analysis. The feasibility and strength of the method are demonstrated based on a benchmark function and on the statistical assessment of a realistic printed circuit board interconnect, highlighting the main features and benefits of this technique over state-of-the-art solutions. Emphasis is given to the effects of the initial sample size and of input noise on the model estimation.

Trends of Next Generation Interconnection Boards

Trends of Next Generation Interconnection Boards

Equivalent Capacitance Approach to Calculate Effective Roughness Dielectric Parameters for Copper Foils on Printed Circuit Boards

Effective roughness dielectric (ERD) is a homogeneous lossy dielectric layer of certain thickness with effective (averaged) dielectric parameters. The ERD layer is used to model copper foil roughness in printed circuit board interconnects by being placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. This work derives the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The gradual variation can be structured as thin layers that are obtained using the equivalent capacitance approach. The concentration profile is extracted from scanning electron microscopy or high-resolution optical microscopy. As the concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be discerned: an insulating (prepercolation) region and a conducting (percolation) region. The rates of increase in effective loss (or corresponding conductivity) in these two regions differ significantly. The proposed model of equivalent capacitance with gradient dielectric is applied to a number of different types of copper foils. The frequency-dependent dielectric parameters of the homogenized ERD are calculated from the equivalent capacitance. The results are validated using 3D numerical electromagnetic simulations. There are two types of numerical models: with homogeneous ERD parameters and layered. Both models show excellent agreement with measurements.

Comparison of power cycling reliability of flexible PCB interconnect smaller/thinner and larger/thicker power devices with topside Sn-3.5Ag solder joints

The power cycling reliability of flexible printed circuit board (PCB) interconnect smaller/thinner (ST) 9.5 mm × 5.5 mm × 0.07 mm and larger/thicker (LT) 13.5 mm × 13.5 mm × 0.5 mm single Si diode samples have been studied. With the assumption of creep strain accumulation-induced fatigue cracking as the failure mechanism of the Sn-3.5Ag solder joints, finite element (FE) simulations predicted a higher power cycling reliability of soldering the flexible PCB on a ST Si diode than on a LT Si diode under similar power cycling conditions. Then the power cycling test results of 10 samples for each type are reported and discussed. The samples were constructed with commercially available ST Si diodes with 3.2/0.5/0.3 μm thick AlSiCu/NiP/Pd topside metallization and LT Si diodes with 5/0.1/1/1 μm thick Al/Ti/Ni/Ag topside metallization. In contradiction with the FE prediction, most ST Si diode samples were less reliable than those LT Si diode samples. This can be attributed to the fact that the failure of the ST diode samples was associated with the weak bonding and hence the shear-induced local delamination of the topside solder joints from the AlSiCu metallization, while the failure of the LT diode samples was mainly caused by the creep strain accumulation-induced fatigue cracking within the solder joints. Such results can be used to not only provide better understanding of the different failure mechanisms, but also demonstrate the importance of employing an appropriate topside metallization on the power devices.

Mechanism analysis of microvia filling based on multiphysics coupling

PurposeCopper electrodeposition acts as a crucial step in the manufacture of high-density interconnect board. The stability of plating solution and the uniformity of copper electrodeposit are the hotspot and difficulty for the research of electrodeposition. Because a large number of factors are included in electrodeposition, experimentally determining all parameters and electrodeposition conditions becomes unmanageable. Therefore, a multiphysics coupling technology was introduced to investigate microvia filling process, and the mechanism of copper electrodeposition was analyzed. The results provide a strong theoretical basis and technical guidance for the actual electroplating experiments. The purpose of this paper is to provide an excellent tool for quickly and cheaply studying the process behavior of copper electrodeposition without actually needing to execute time-consuming and costly experiments.Design/methodology/approachThe interactions among additives used in acidic copper plating solution for microvia filling and the effect on the copper deposition potential were characterized through galvanostatic measurement (GM). The adsorption behavior and surface coverage of additives with various concentrations under different rotating speeds of working electrode were investigated using cyclic voltammetry (CV) measurements. Further, a microvia filling model was constructed using multiphysics coupling technology based on the finite element method.FindingsGM tests showed that accelerator, inhibitor and leveler affected the potential of copper electrodeposition, and bis(3-sulfopropyl) disulfide (SPS), ethylene oxide-propylene oxide (EO/PO) co-polymer, and self-made leveler were the effective additives in acidic copper plating solution. CV tests showed that EO/PO–Cu+-Cl− complex was adsorbed on the electrode surface by intermolecular forces, thus inhibiting copper electrodeposition. Numerical simulation indicated that the process of microvia filling included initial growth period, the outbreak period and the stable growth period, and modeling result was compared with the measured data, and a good agreement was observed.Research limitations/implicationsThe research is still in progress with the development of high-performance computers.Practical implicationsA multiphysics coupling platform is an excellent tool for quickly and cheaply studying the electrodeposited process behaviors under a variety of operating conditions.Social implicationsThe numerical simulation method has laid the foundation for mechanism of copper electrodeposition.Originality/valueBy using multiphysics coupling technology, the authors built a bridge between theoretical and experimental study for microvia filling. This method can help explain the mechanism of copper electrodeposition.