Interconnect Bandwidth Research Articles

100×100 optoelectronic cross-connect interconnects using OPTOBUS

This paper demonstrates an OPTOBUS-based fully packaged optoelectronic cross-connect interconnect technique for data communication applications. Optical insertion loss of the compact 100/spl times/100 cross-connect interconnect device ranges from 0.4 to 2.9 dB among all possible connections. Optical transmissions with bit error rate (BER) of >10/sup -12/ can be maintained at per channel bandwidth of 900 Mb/s. The system is expected to have an aggregated interconnect bandwidth near 100 Gb/s when being fully connected with the OPTOBUS chips.

Evaluation of design issues for optoelectronic cores: a case study of the WARRP II router

The continuing improvement of processor performance has increased the demand on interconnection bandwidth at a rate that outpaces the bandwidth provided by conventional electrical interconnects. By combining a high-bandwidth optical interconnect technology with the ubiquitous high-performance CMOS technology, optoelectronic routers show the potential to supply greater bandwidth capacity as well as complex functionality suitable for developing high-performance interconnection networks demanded by current and next-generation processors. However, developing optoelectronic chips at this level of complexity is not conventional and, hence, there are several issues to be investigated. In this work we evaluate design issues regarding the integration of complex CMOS core circuitry with optoelectronic SEEDs using a semi-analytical model. Our results show that complex optoelectronic chips can still yield better interconnection bandwidth compared to high-performance CMOS chips, albeit at the expense of decreased transister density and increased critical paths.

Frequency-dependent crosstalk simulation for on-chip interconnections

An extensive study of crosstalk simulation issues for on-chip interconnections was performed for representative six-layer Al(Cu) structures. Guidelines are given for the range of conditions when R(f)L(f)C versus RLC versus RC circuit representations are valid. Examples are also given of realistic short and long coupled-section interactions and the effect of in-plane neighboring connections is discussed. A frequency-dependent crosstalk simulation technique is shown. All simulation results are verified through measurement of a comprehensive set of experiments built with a large range of line widths and spaces on various layers with both in-plane and vertical coupling. Signal propagation and crosstalk are analyzed over the temperature range -160/spl deg/C to +100/spl deg/C and interconnect bandwidth limitations predictions are given.

Design issues for core-based optoelectronic chips: a case study of the WARRP network router

We review trends in interconnect bandwidth requirements for multiprocessor systems and technologies proposed to meet these requirements. The benefits and costs of core-based optoelectronic chips are discussed using CMOS-SEED implementations of the WARRP network router as a case study. Results indicate that transistor density and on-chip clock rates of optoelectronic core-based designs can be reduced by as much as 40% and 30%, respectively, but aggregate off-chip bandwidth can be increased by as much as an order of magnitude as compared to all-electronic chip designs.

The ideal light source for datanets

The appetite for ever increasing computing power and interconnection bandwidth could be sated by vertical-cavity, surface-emitting lasers (VCSEL) for optical data communication. Made inexpensively using IC processing techniques, they can be diced in planar or linear arrays, such as in the wavelength-division multiplexer. The author discusses the essentials of semiconductor light sources, epitaxial growth of the surface-emitting laser and its interior design. The characteristics and operation of the VCSEL are described.

A 2.6-GByte/s multipurpose chip-to-chip interface

A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special I/O circuits are used to guarantee 800 Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible interconnect bandwidth.

Improvement in bit-error rate for optoelectronic multicomputer interconnection networks using cyclic redundancy code error detection

This letter presents testing results of an integrated optoelectronic (OE) channel employing hop-by-hop error control circuitry based on cyclic redundancy codes (CRC) to improve the effective bit-error rate (BER). The use of OE interconnect in place of wires in multicomputer networks becomes more attractive as channel bandwidth and power efficiency are increased. But these improvements must be accomplished while maintaining an acceptable channel BER. Test results of an integrated OE channel incorporating CRC-based error control circuitry demonstrate a BER reduction of two orders of magnitude while incurring a 20% bandwidth overhead. This may lead to higher bandwidth and higher efficiency OE interconnects.

Effectiveness of Dynamic Prefetching in Multiple-Writer Distributed Virtual Shared-Memory Systems

We consider a network of workstations (NOW) organization consisting of bus-based multiprocessors interconnected by a high latency and high bandwidth interconnect, such as ATM, on which a shared-memory programming model using a multiple-writer distributed virtual shared-memory system is imposed. The latencies associated with bringing data into the local memory are a severe performance limitation of such systems. To make the access latencies tolerable, we propose a novel prefetch approach and show how it can be integrated into the software-based coherence layer of a multiple-writer protocol. This approach uses the access history of each page to guide which pages to prefetch. Based on detailed architectural simulations and seven scientific applications we find that our prefetch algorithm can remove a vast majority of the remote operations, which improves the performance of all applications. We also find that the bandwidth provided by ATM switches available today is sufficient to accommodate prefetching. However, the protocol processing overhead of available ATM interfaces limits the gain of the prefetching algorithms.

The Mercury Interconnect Architecture

This paper presents HAL's Mercury Interconnect Architecture, an interconnect infrastructure designed to link commodity microprocessors, memory, and I/O components into high-performance multiprocessing servers. Both shared-memory and message-passing systems, as well as hybrid systems are supported by the interconnect. The key attributes of the Mercury Interconnect Architecture are: low latency, high bandwidth, a modular and flexible design, reliability/availability/serviceability (RAS) features, and a simplicity that enables very cost-effective implementations. The first implementation of the architecture links multiple 4-processor Pentium™ Pro based nodes. In a 4-node (16-processor) shared-memory configuration, this system achieves a remote read latency of just over 1 µs, and a maximum interconnect bandwidth of 6.4 GByte/s. Both of these parameters far outpace comparable SCI-based solutions, while utilizing much fewer hardware components.

An architectural framework for the support of integrated services by broadband customer premises equipment

The ATM customer premises equipment (CPE) architecture proposed in this paper supports a broad range of user applications with varying service requirements. A backplane bus was chosen as a cost effective, reliable means of providing the necessary internal interconnection bandwidth. Incorporating a novel access mechanism and graceful performance degradation under fault conditions, this bus provides a foundation for Quality of Service provision. Essential functions including traffic management, connection admission control and signalling are then built on top of this. A prototype system which uses a semi-custom ASIC to implement the backplane access mechanism is briefly described. The architecture provides a flexible basis for service provision, allowing a single CPE device to meet a variety of end user requirements. Results of simulations showing the effectiveness of internal bandwidth access mechanisms are presented.

COMMUNICATION PIPELINING IN HYPERCUBES

Many parallel algorithms exhibit a hypercube communication topology. Such algorithms can easily be executed on a multicomputer with a hypercube interconnection topology. However, in most cases these parallel algorithms only make use of a small fraction of the interconnection bandwidth offered by the multicomputer. In particular, each processor of a hypercube multicomputer is connected to d different neighbors by d different links. Nevertheless, hypercube algorithms usually do not use more than one of these d links at the same time. This paper presents a technique called communication pipelining that enables a more efficient use of the interconnection network and, in consequence, a significant reduction in the execution time. This technique is based on a transformation of the original algorithm. The resulting equivalent algorithm makes use of several links of each node simultaneously. Given a particular problem and a particular architecture. the degree of pipelining to be applied is a design parameter that must be decided when transforming the original algorithm. The paper presents analytical models that allow for an optimal choice of the degree of pipelining for each problem and a given architecture. To illustrate the performance of the communication pipelining technique, its application to the FFT computation is presented as an example. It is shown that an optimal choice of the degree of pipelining can achieve a reduction by a factor of d in the communication overhead of the algorithm.

Systolic processor designs using single-electron digital circuits

The possibility of using single-electron digital circuits (SEDCs) to achieve ultra-high performance digital signal processing is explored. SEDCs are highly-scalable Coulomb blockade-based circuits that operate in the discrete limit where bits are represented by single electrons. Such circuits are well-suited to implementing bit-level systolic processing algorithms because the local connectivity of systolic arrays translates into locally-interconnected hardware. By relieving interconnect bandwidth limitations this enables circuits that can fully exploit the extreme scaling possible with the single-electron devices. Errors associated with co-tunneling, thermal fluctuations, etc. are an important issue in single-electron circuits, especially for a digital application. The systolic arrays are, however, amenable to simple error-correction techniques which may make computing with these unreliable components possible. Nevertheless, it must be emphasized that realization of these complex circuits depends on tremendous advances in fabrication technology, particularly to meet their stringent uniformity requirements.

A time domain approach for avoiding crosstalk in optical blocking multistage interconnection networks

Crosstalk in multistage interconnection networks can be avoided by ensuring that a switch is not used by two connections simultaneously, in order to support crosstalk-free communications among N inputs and N outputs, a space domain approach dilates an N/spl times/N network into one that is essentially equivalent to a 2N/spl times/2N network. Path conflicts, however may still exist in dilated networks. This paper proposes a time domain approach for avoiding crosstalk. Such an approach can be regarded as dilating a network in time, instead of space. More specifically, the connections that need to use the same switch are established during different time slots. This way, path conflicts are automatically avoided. The time domain dilation is useful for overcoming the limits on the network size while utilizing the high bandwidth of optical interconnects. We study the set of permutations whose crosstalk-free connections can be established in just two time slots using the time domain approach. While the space domain approach trades hardware complexity for crosstalk-free communications, the time domain approach trades time complexity. We compare the proposed time domain to the space domain approach by analyzing the tradeoffs involved in these two approaches. >

Multitasking in high-speed interconnection systems

This paper focuses on high-speed connection-oriented communication among high-end multitasking systems. This environment is characterized by very high interconnection bandwidth and by large, variable size data blocks. The HIPPI standard is being designed to provide a base for communication in such an environment. Multitasking in members of the system complex requires multiple source buffers for the interconnection system, an unusual feature of connection-oriented communication that requires special consideration in the design and performance evaluation. We define two connection management policies, the centralized and the broadcast policy and two service disciplines, the ALL discipline and the FIFO discipline. We then develop analytic models that can represent the salient features of such interconnection systems, including, the management policy, the service discipline and the number of buffers. The models are validated by comparing their results to results from simulations. The models are then used to evaluate the impact of the connection management policies, the service disciplines, and the number of buffers on the performance of these interconnection systems.

Organization of information flow in computation for efficient utilization of high information flux communication media

We discuss the importance of organizing information flow in computation in a manner enabling multiplexing of signal paths with distinct source and destination localities. This allows efficient use of high bandwidth interconnection media, leading to a decrease in system size and propagation delay for communication limited layouts. Among the three methods we consider towards this end, the fat-tree architecture is found to be near optimal.

Passive Polymeric Waveguide Materials for Optical Interconnects

AbstractThe need for higher bandwidth interconnect schemes to relieve the communications bottleneck caused by the ever increasing speeds of discreet electronic devices has led to a renewed interest in thin film optical waveguides as interconnect media. This paper reviews some of the polymeric materials that have been investigated for use as thin film passive optical waveguides over the past ten years. Several proposed applications for these waveguides are presented and the specific material requirements of these applications are discussed. The strengths and weaknesses of specific polymeric materials are considered in view of these requirements. While reference is made to a variety of polymers that have been considered for these applications, emphasis is placed on the relative merits of polyimide and acrylate polymer based systems.

Technologies for low latency interconnection switches

This paper presents an engineering design for a low latency high bandwidth interconnection network which will form the switching substrate for a multi-model parallel processing system. The performance is enhanced with a variety of approaches covering interconnection protocols, routing, fault tolerance, advanced packaging, and electrical interconnection techniques. The synergistic application of these technologies leads to a high performance design.

Evaluation of reduced bandwidth multistage networks

This paper presents and evaluates a class of buffered interconnection networks which provide performance and cost levels intermediate to a bus and a delta network. These networks, referred to as hybrid networks, are formed by beginning with a delta network and substituting buses for the final stages of the network. The choice of the number of stages replaced determines the bandwidth of the network. The reduction of network bandwidth is accompanied by a corresponding reduction in network cost. Hybrid networks provide the system architect with a cost-effective solution to design problems in which the required interconnection bandwidth is greater than that of a bus but less than that of a full delta network. The performance of hybrid networks is investigated by developing a numerical model and by using simulation. Two features of the model, buffers of arbitrary length at network switches and resource service times greater than interstage transfer delays, have not been included in previous analytical models of delta networks. Results show that in some cases, the expense of a multistage network is not required in order to maintain the maximum level of system performance.

A Traffic Scheduling Technique for Metropolitan Area Gateways

In the future, metropolitan area networks (MAN's) will provide high bandwidth interconnection between local access networks in high density office, industrial, and residential settings. In these systems, the metropolitan area gateway (MAG) is responsible for coordinating the flow of traffic in and out of the metropolitan subnetwork. In certain environments, it is expected that the traffic will possess distinct characteristics. In this paper, a technique called SWIFT is proposed which efficiently schedules these traffic flows when the local access network is based upon broadband CATV-type cable technology. SWIFT satisfies the important constraint that it is compatible with existing CSMA/CD packet data network adapters which means that it may be implemented in previously installed systems. In this paper, a throughput model is given for the proposed technique. Also, an analytic model is given which approximates the mean remote delay when the traffic is moderately to heavily remote-bound. The performance results presented indicate that a system operating the SWIFT algorithm can achieve much reduced delays at higher throughput than would otherwise be possible.

The Effects of Problem Partitioning, Allocation, and Granularity on the Performance of Multiple-Processor Systems

In this paper we analyze the effects of the problem decomposition, the allocation of subproblems to processors, and the grain size of subproblems on the performance of a multiple- processor shared-memory architecture. Our results indicate that for algorithms where both the computation and the communication overhead can be fully decomposed among N processors, the speedup is a nondecreasing function of the level of granularity for arbitrary interconnection structure and allocation of subproblems to processors. For these algorithms, the speedup is an increasing function of the level of granularity provided that the interconnection bandwidth is greater than unity. If the bandwidth is equal to unity, then the speedup converges to the value equal to the ratio of processing time to communication time. For algorithms where the computation is decomposable but the communication overhead cannot be decomposed, the speedup is a nondecreasing function of the level of granularity for the best case bandwidth only. If the bandwidth is less than N, the speedup reaches its maximum and then decreases approaching zero as the level of granularity grows. For algorithms where the computation consists of parallel and serial sections of code and the communication overhead is fully decomposable, the speedup converges to a value inversely proportional to the fraction of time spent in the serial code even for the best case interconnection bandwidth.