Abstract
The continuing improvement of processor performance has increased the demand on interconnection bandwidth at a rate that outpaces the bandwidth provided by conventional electrical interconnects. By combining a high-bandwidth optical interconnect technology with the ubiquitous high-performance CMOS technology, optoelectronic routers show the potential to supply greater bandwidth capacity as well as complex functionality suitable for developing high-performance interconnection networks demanded by current and next-generation processors. However, developing optoelectronic chips at this level of complexity is not conventional and, hence, there are several issues to be investigated. In this work we evaluate design issues regarding the integration of complex CMOS core circuitry with optoelectronic SEEDs using a semi-analytical model. Our results show that complex optoelectronic chips can still yield better interconnection bandwidth compared to high-performance CMOS chips, albeit at the expense of decreased transister density and increased critical paths.
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