Interconnect Delay Research Articles

Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme

In this article, we propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme including system architecture and hardware structure. The proposed scheme embeds processing units into the logic layer of the high bandwidth memory (HBM) to expose an excess dynamic random access memory (DRAM) bandwidth. With parallelized DRAM architecture and a high-speed through-silicon via (TSV) structure, the proposed scheme successfully extends the DRAM bandwidth of processing-in-memory (PIM). Also, the total energy consumption is decreased by the reduced interconnection and capacitance-reduced channel structure. We designed the overall architecture and structure with physical feasibility for application to the current HBM. The logic layer and DRAM layers in the HBM are configured to embed the processing units and parallelize the DRAM channels. For high-speed data transfer with low interconnect energy, the TSV and silicon interposer channels are designed and analyzed in consideration of signal integrity (SI). Based on the physical design, we obtained the interconnect length in detail. The interconnect energy and delay of the silicon interposer and on-chip interconnect were modeled through a SPICE simulation. We analyzed the accurate effects of interconnect reduction caused by PIM. For overall system performance and efficiency analysis, a cycle-level architectural simulation was conducted. We successfully evaluated and analyzed the system performance for memory-intensive applications. As a result, the proposed PIM-HBM achieves 53% and 10.4% improvement on average in computing performance and energy efficiency compared to the conventional graphic processing unit of high bandwidth memory (GPU-HBM).

Decentralized full-state constrained adaptive tracking control for interconnected time delay systems with input saturation

In this article, the problem of decentralized full-state constrained adaptive tracking control is investigated for interconnected time delay systems with input saturation. The extreme learning machine is applied to approximate the unknown nonlinear function in the design process. By selecting the appropriate Lyapunov–Krasovskii function, the time delay interconnection term could be compensated. A unified barrier function is introduced to ensure that the constraints imposed on all states are not violated. The Nussbaum function is introduced to deal with the problem of input saturation. By applying adaptive backstepping procedures, a novel decentralized full-state constrained adaptive tracking control strategy is proposed for the considered interconnected time delay systems. In terms of Lyapunov stability theory, it is proved that all the signals of the closed-loop systems are semi-global ultimately uniformly bounded and all state variables could be constrained within the time varying asymmetric boundaries. Finally, the effectiveness of the proposed scheme is illustrated by a simulation example of a two-stage chemical reactor.

Crosstalk Delay and Noise Optimization in Nanoscale Multi-line Interconnects Based on Repeater Staggering in Ternary Logic

In this study, the crosstalk effects are minimized in coupled multi-line wires based on repeater staggering in ternary logic. For more accuracy, the impact of the coupling capacitance is also considered in our calculations. Our results indicate that the number of repeaters required for optimizing the delay of the multilayer graphene nanoribbon (MLGNR) interconnect is, on average, 43% lower than multi-walled carbon nanotube (MWCNT) interconnect. Moreover, the optimized delay of the MLGNR interconnect is, on average, 48% lower than MWCNT interconnect. The ternary repeater insertion reduces the delay of the MWCNT and MLGNR interconnects carrying ternary signals by 61% and 51%, respectively. The staggered repeater insertion is applied as a practical approach for eliminating the crosstalk noise in the transmitted ternary signals in a multi-line coupled structure. Our results demonstrate that the delay and energy of the staggered repeater-inserted MLGNR interconnects are, on average, 42% and 37% lower than their MWCNT counterparts. Furthermore, the impacts of the process variations are investigated using comprehensive Monte Carlo simulations and the optimized ternary multi-line MLGNR interconnect functions correctly and considerably robustly compared to their MWCNT counterpart.

Prescribed performance adaptive fault tolerant control approach for nonlinear large‐scale systems with time delay interconnection and dead zone input

AbstractIn this study, a prescribed performance adaptive fault tolerant tracking control scheme is presented for a class of nonlinear large‐scale systems with time delay interconnection, dead zone input, and actuator fault. The radial basis function neural networks are used to approximate unknown nonlinear functions. Different from the barrier Lyapunov functions used to achieve the symmetrical prescribed performance, a new error transformation is introduced in this study to achieve the desired asymmetrical prescribed performance. In addition, Nussbaum function is introduced to solve the difficulties caused by dead zone input and actuator fault. Based on the appropriate Lyapunov–Krasovskii functions, the effect of time delay interconnection could be compensated. By using backstepping procedures, an adaptive fault tolerant tracking control approach is developed for the considered large‐scale systems, and the stability of the closed‐loop systems is analyzed by Lyapunov theory. Meanwhile, the prescribed performance of the tracking error could be guaranteed. Finally, the effectiveness of the proposed control approach is illustrated by two simulation examples.

Decentralised fault-tolerant tracking control for interconnected nonlinear time delay systems using dynamic event triggering mechanism

In this study, a novel decentralised fault-tolerant control strategy is developed for a class of interconnected nonlinear time delay systems with unmeasurable state variables and actuator faults by using dynamic event triggering mechanism. The interconnected system model includes nonlinear time delay functions and unstructured uncertainties, which could be identified by the radial basis function neural networks approximation technique. The adaptive nonlinear observer is designed for each interconnected subsystem to obtain the estimated values of unmeasurable state variables and unknown system faults simultaneously. Then, a decentralised fault-tolerant tracking controller is designed for the considered interconnected time delay systems using both backstepping control procedures and a dynamic event triggering mechanism, which has the smaller event trigger frequency by comparing the traditional static event-triggered control scheme, such that the tracking error signals converge to a small neighbourhood near the origin and all the signals of the closed-loop system are globally bounded. Finally, a chemical reactor example is given to illustrate the feasibility and significance of the designed control scheme.

Crosstalk aware transient error correction coding technique for NoC links

In Deep Sub Micron (DSM) technology, the critical issues in the NoC interconnect design are to meet the performance, power consumption requirements of the SoC and to address reliability simultaneously, interconnect delay, power consumption and crosstalk noise. It is essential to select an optimal coding technique to improve communication reliability and reduce self and coupling switching activities. In this paper, Crosstalk Aware Transient Error Correction (CATEC) coding technique is proposed to handle the reliability issues and flit dependent switching activities. The achievable reliability and reduction of switching activities are evaluated using real-time traffics. It is proved that the CATEC technique corrects all the error patterns with one or two transient error bits and few error patterns with six to nine transient error bits. Furthermore, 99% of the error patterns with three, four and five transient error bits are too corrected for a 32 bit flit. This technique considerably reduces flit dependent self and coupling transitions. This results in low power NoC link and even avoids crosstalk to a greater extent.

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

PurposeAdvancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).Design/methodology/approachThis paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.FindingsThis paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.Practical implicationsThis paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.Originality/valueThis paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Discussion on the Security Mechanism of Energy Internet in 5G network

With the coming of 5G network, it is possible for energy Internet to achieve high bandwidth and low delay interconnection. At the same time, it also brings new security problems. The core elements of 5G - virtualization, cloud migration, network slicing, Internet of Things, 5G gateway and even related software development may become security vulnerabilities. Aiming at the possible security problems in the application of 5G in the energy Internet, including the overall security architecture, industry security subdivision, Internet of Things security operation and maintenance, and the application of new security mechanisms, this paper expounds the relevant concepts and threats. This paper puts forward that in security architecture, we should make full use of security mechanisms such as logical isolation and access control to achieve in-depth defense; in industry segmentation, we should have customized security capability response for different application scenarios of different industries; in the security operation and maintenance of the Internet of Things, we should aim at the complex network environment and topology of mass terminals. In the new security mechanism, it should be combined with large data analysis and AI intelligent processing to enhance the ability of security early warning. Finally, combined with the application scenario of the energy internet, this paper proposes a comprehensive solution to the energy Internet Security in the 5G.

Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects

We introduce a Nyquist stability analysis of coupled mixed CNT bundle (MCB) for sub-threshold interconnects. In this analysis, the dependence of relative stability of sub-threshold MCBs with specific and probabilistic distribution of CNTs, on the geometry and probability of metallic CNTs, has been obtained. Using the proposed ABCD model and Nyquist stability criterion for sub-threshold MCBs, we show that, by increasing the diameter of each individual CNT and the length of MCB, the sub-threshold MCB interconnect system becomes more stable, while a densely packed MCB reduces the relative stability. Moreover, the crosstalk impact results in the greater stability of sub-threshold MCB system in comparison to a single interconnect. The crosstalk delay of MCB and composite Cu-MWCNT interconnects is also compared at various lengths. This is, so far, the first instance that such an analysis has been presented for coupled sub-threshold MCB interconnects.

Sol–gel deposited xerogel, aerogel and porogen based porous low-k thin films: A comparative investigation

Low dielectric constant (Low-[Formula: see text]) films are used as inter layer dielectric (ILD) in nanoelectronic devices to reduce interconnect delay, crosstalk noise and power consumption. Tailoring capability of porous low-[Formula: see text] films attracted more attention. Present work investigates comparative study of xerogel, aerogel and porogen based porous low-[Formula: see text] films. Deposition of SiO2 and incorporation of less polar bonds in film matrix is confirmed using Fourier Transform Infra-Red Spectroscopy (FTIR). Refractive indices (RI) of xerogel, aerogel and porogen based low-[Formula: see text] films observed to be as low as 1.25, 1.19 and 1.14, respectively. Higher porosity percentage of 69.46% is observed for porogen-based films while for shrinked xerogel films, it is lowered to 45.47%. Porous structure of low-[Formula: see text] films has been validated by using Field Emission Scanning Electron Microscopy (FE-SEM). The pore diameters of porogen based annealed samples were in the range of 3.53–25.50 nm. The dielectric constant ([Formula: see text]) obtained from RI for xerogel, aerogel and porogen based films are 2.58, 2.20 and 1.88, respectively.

A Review of Recent Research on Heat Transfer in Three-Dimensional Integrated Circuits (3-D ICs)

Three-dimensional integrated circuits (3-D IC) technology has emerged in the past few decades, driven in part by the techno-economic difficulties of dimensional scaling and the increasing interconnect delay in microelectronics. In a 3-D IC, vertical integration of multiple transistor planes, either through monolithic integration or through bonding of multiple strata, offers reduced interconnect delay and enhanced design flexibility. However, vertical integration in a 3-D IC also results in severe thermal management challenges. Thermal management of a 3-D IC is exacerbated by the multilayer nature of the 3-D IC. Furthermore, new components such as through-silicon vias (TSVs) offer opportunities for novel thermal management. This article presents a critical review of research literature related to heat transfer in 3-D ICs, focusing specifically on thermal modeling, thermal-electrical codesign, and thermal management of a 3-D IC. Key literature from recent years is categorized and summarized. A discussion on the future outlook for research in these areas is presented. It is expected that this review article will be helpful for researchers in academia and industry for understanding the state-of-the-art in various areas related to heat transfer in 3-D ICs.

High Speed and Performance analysis of Multiplier in Field Programming Gate Array

This paper reads pipelined increase procedures for execution on FPGAs with accentuation on the usage of FPGA equipment asset. Execution of multiplier usage are estimated for monetarily accessible FPGA designs where two inborn issues are presented and examined. These being the lopsidedness of basic interconnect delay between broad directing and static convey interconnects, and the measure of FPGA rationale region utilized and its helpless usage. For every one of these issues proposals are proposed and researched.

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs.

Despite an increasing adoption of high-level synthesis (HLS) for its design productivity advantages, there remains a significant gap in the achievable frequency between an HLS design and a handcrafted RTL one. A key factor that limits the timing quality of the HLS outputs is the difficulty in accurately estimating the interconnect delay at the HLS level. This problem becomes even worse when large HLS designs are implemented on the latest multi-die FPGAs. To tackle this challenge, we propose AutoBridge, an automated framework that couples a coarse-grained floorplanning step with pipelining during HLS compilation. First, our approach provides HLS with a view on the global physical layout of the design, allowing HLS to more easily identify and pipeline the long wires, especially those crossing the die boundaries. Second, by exploiting the flexibility of HLS pipelining, the floorplanner is able to distribute the design logic across multiple dies on the FPGA device without degrading clock frequency. This prevents the placer from aggressively packing the logic on a single die which often results in local routing congestion that eventually degrades timing. Since pipelining may introduce additional latency, we further present analysis and algorithms to ensure the added latency will not compromise the overall throughput. AutoBridge can be integrated into the existing CAD toolflow for Xilinx FPGAs. In our experiments with a total of 43 design configurations, we improve the average frequency from 147 MHz to 297 MHz (a 102% improvement) with no loss of throughput and a negligible change in resource utilization. Notably, in 16 experiments we make the originally unroutable designs achieve 274 MHz on average. The tool is available at https://github.com/Licheng-Guo/AutoBridge.

Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits

The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To this end, we propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. In summary, our synthesis framework is able to reduce the prediction error by 54% and 19% on average over that using the conventional critical path replica and using the conventional method exploiting gate sizing only, respectively.

An extensive survey on future direction for the reduction of noise coupling problem in TSV based 3-dimensional IC integration

Over the period of meticulous scaling IC’s are crucially waiting for a platform which is planar. The most important and actual restriction is nothing, but delay of interconnect is almost approximate to that of devices. To achieve the demands of system performance, new interconnecting materials along with experimental architectures need to be developed. A new integration approach is developed which is nothing but 3D integration technology because this technology is most advantageous and famously used in comparisons to other technologies. Also 3-D technology has a capacity to ensemble with CMOS application because it can easily connect many devices in layers and can be stacked vertically with interconnecting wires having higher thickness among the layers. In this TSV’s plays an important job, which can enable 3-D IC platform. Noise coupling from TSV-to-TSV and TSV-to-Substrate is estimated inside the heterogeneous integration. A vertical TSV pattern is developed to decrease the area per TSV, capacitive coupling and make constructive inductance compared to other design patterns. By developing the vertical TSV patterns in 3D IC the functionality became easier with lesser TSV’s.

Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic

This research paper presents a novel circuit modeling and analysis of ternary logic for MWCNT bundle interconnects with active shielding under the influence of temperature variations. The far end crosstalk-induced noise and propagation delay of MWCNT bundle interconnects has been analyzed with and without the effect of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at output. The temperature-dependent analysis is also carried out at different temperatures such as 300, 400 and 500 K. The temperature-dependent comparative analysis for MWCNT bundle, SWCNT bundle and copper interconnects with and without shielding is also performed. It has been observed that MWCNT bundle with active shielding outperforms the SWCNT and Cu by 75.7% and 84.4%, respectively. Similarly, the power dissipation is substantially reduced in the case of MWCNT bundle with respect to the Cu and SWCNT interconnects. It is also reported that the noise margin is marginally stable in ternary interconnects under the influence of temperature variation.

Embedding delay‐based physical unclonable functions in networks‐on‐chip

Physical unclonable functions (PUFs) are emerging as security primitives by exploiting the intrinsic device features in various hardware security solutions. This article proposes a mechanism to embed delay-based PUFs, namely arbiter PUF and ring-oscillator PUF, in the network-on-chip (NoC) architecture. These embedded PUFs are constructed by reusing already available hardware resources in NoCs, such as the crossbar switches. Pass transistors, which work as control components, have been added into the delay paths. A 5-port NoC router has been considered and the corresponding 5 × 5 crossbar switches have been analysed after obtaining a suitable layout to embed the delay-based PUFs. The embedded PUFs have been qualitatively analysed for their robustness against variations in supply-voltage. Furthermore, a qualitative study on generating secret keys from the embedded PUFs has been presented. A PUF-specific layout has been considered for implementing the NoC crossbar switches, and for extracting the RC interconnection delays. Monte Carlo simulations have been performed to evaluate the quality metrics of the proposed embedded PUFs for a 64-bit response. Area overheads incurred for realizing the proposed embedded PUFs have been found to be 6.38% and 2.68%, for arbiter PUF and ring-oscillator PUF, respectively. Furthermore, by incorporating the pass transistors in the control components, the reliability metrics have been found to be reasonably improved over traditional constructions of the arbiter and the ring-oscillator PUFs.

A study on the interfacial adhesion energy between capping layer and dielectric for cu interconnects

Recently, Cu interconnect and low-k materials have been applied to reduce the interconnect resistive-capacitive delay issue. However, as the process node size is reduced to a few nanometers, high leakage currents appear through the dielectric under high electric fields. Therefore, issues of Cu diffusion at the interface between the dielectric and the capping layer have been reported. This study investigated interfacial adhesion energy change at the film level between dielectric (low-k, tetraethyl orthosilicate (TEOS)) and capping layer (SiCN, SiN) taking into account the correlation between interfacial adhesion energy and interconnect reliability. In the capping layer/low-k interface, when low-k is applied to the top layer, it shows high interfacial adhesion energy (> 34.31 ± 3.49 J/m2) due to the presence of an O-rich thin layer. But when low-k is applied to the bottom layer, due to the SiC bond, it shows low interfacial adhesion energy (< 5.60 ± 2.46 J/m2). The interface between TEOS and SiN has high interfacial adhesion energy (> 32.54 ± 1.97 J/m2) regardless of the stacking order and CMP process. It clearly shows that low-k dielectrics will affect the deterioration of the interfacial adhesion energy and O-rich layer will greatly improve the interfacial adhesion energy in dielectric/capping layers.

A Novel Approach to Reduce the Crosstalk in Graphene Based Interconnects Using Ternary Logic

This paper presents a novel approach to reduce the impact of crosstalk in multi-layered GNR (MLGNR), single walled CNT (SWCNT), multiwalled CNT (MWCNT) and mixed CNT bundle (MCB) based three-line bus architecture system. The proposed system primarily comprises of active shielding, repeater insertion and asymmetric triggering of the input signal. At the far end of the bus architecture, the crosstalk induced noise and propagation delay of MLGNR, SWCNT, MWCNT and MCB interconnects have been analyzed with and without the impact of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at the output. Using the specified output, a temperature dependent comparative analysis is also performed for MLGNR and bundled CNT interconnects with and without shielding. Using industry standard HSPICE circuit simulations, it can be observed that the MLGNR offers a lower paracitic values even in higher temperature in comparison to the SWCNT, MWCNT and MCB interconnects. It primarily leads to a lesser delay and crosstalk using a bus interconnect system. The analysis has also extended for delay and crosstalk analysis for different interconnect lengths and temperatures with an insertion of shielding, repeaters and asymmetric triggering of bus architecture system. Under these conditions, it is also proved that an MLGNR based bus architecture offers a lesser crosstalk induced delay and noise compared to CNT bundle interconnects.

(Invited) Copper Surface Passivation for Low Temperature Cu-to-Cu Bonding Applications

As the IC devices are rapidly scaled down, IC integration has faced several technical bottlenecks: further miniaturization, power delivery and distribution, signal/power integrity, and heat dissipation. In this regard, chip or wafer stacking processes have attracted attention to improve an interconnect delay and an inter-die bandwidth, reduce a form factor, and decrease manufacturing costs. Vertically stacking technology not only enhances device performance, but also can realize heterogeneous packaging systems for the next generation heterogeneous integration. Of the three unit processes in the vertical stacking system, Cu-to-Cu bonding has emerged as a core technology for efficient power density, high bandwidth, and fine-pitch connecton.Various Cu-to-Cu bonding studies have been reported, such as thin metal passivation on Cu surface, self-assembled monolayer that passivates Cu surface with alkane-thiol, surface activated bonding that removes surface oxide layers and contaminants by plasma treatment, and direct bonding interconnect that enables Cu/SiO2 hybrid bonding. Despite many studies, Cu surface oxidation and high bonding temperature are still major issues to be resolved in high volume manufacturing. Sustainable, oxidization-free copper surface prior to Cu-to-Cu bonding is critical, especially since chip-to-chip bonding must still be performed in the air. Therefore, in this study, the copper surface passivation using the two-step plasma treatment has been investigated.The Cu-to-Cu bonding process of less than 300℃ was investigated using the copper nitride passivation. The copper nitride passivation layer was formed on 8-inch Si/SiO2/50nm Ti/1μm Cu using the two-step Ar-N2 plasma treatment process. The purpose of two step plasma treatment is first to remove copper oxides and any contaminants through Ar plasma, activate the Cu surface, and then form a copper nitride layer through N2 plasma. This metastable passivation of couple nanometer thickness prevents further oxidation and reduces surface roughness. In addition, since a copper nitride tends to decompose at 300oC or lower it does not adversely affect Cu bonding interface. The two-step plasma treatment was optimized to improve Cu bonding quality, and optimization was systematically carried out by the response surface methodology (RSM) based on a central composite design (CCD) in design of experiment (DOE). It has been found that copper nitride passivation lasts at lasts for 1 week.. The two-step plasma treatment showed the Cu2O removal and Cu4N formation on the Cu surface. Under the optimized two step Ar-N2 plasma treatment at 300℃, Cu-to-Cu bonding quality has significantly improved compared to the Cu-to-Cu bonding without any surface treatment. The interfacial strength measured by 4-point bending test and shear test and electrical measurements will be discussed.