Inter Process Research Articles

Performance optimization opportunities in the Android software stack

The smartphone hardware and software ecosystems have evolved very rapidly. Multiple innovations in the system software, including OS, languages, and runtimes have been made in the last decade. Although, performance characterization of microarchitecture has been done, there is little analysis available for application performance bottlenecks of the system software stack, especially for contemporary applications on mobile operating systems.In this work, we perform system utilization analysis from a software perspective, thereby supplementing the hardware perspective offered by prior work. We focus our analysis on Android powered smartphones, running newer versions of Android. Using 11 representative apps and regions of interest within them, we carry out performance analysis of the entire Android software stack to identify system performance bottlenecks.We observe that for the majority of apps, the most time-consuming system level thread is a frame rendering thread. However, more surprisingly, our results indicate that all apps spend a significant amount of time doing Inter Process Communication (IPC), hinting that the Android IPC stack is a ripe target for performance optimization via software development and a potential target for hardware acceleration.

Reliability-Based Heuristic-Based Algorithm for Task Execution in Multiprocessor Systems

Objective: This study implements a combination of heuristicbased algorithm and finding variable neighborhoods, thereby reducing make-span and improving reliability. Methods/statistical analysis: The bi-objective algorithm is proposed for a static planning strategy to achieve high performance in heterogeneous multiprocessor systems. The reliability of a system is based on the probability in which resources of the system execute tasks without any failure. Findings: Here, a genetic algorithm integrated using single neighborhood structure Genetic Variable Neighbourhood Search (GVNS) is implemented to improve the efficient search quality. Applications and improvements: Simulation is performed to maintain better performance parameters when compared with conventional algorithms. Keywords: Directed Acyclic Graph, Inter Process Communication, Evolutionary Algorithm.

Implementation of Improved Synchronization in Inter Process Communication using Threads for Microkernel and Distributed Operating Systems

Interprocess Communication (IPC) is used by the cooperating processes for communication and synchronization. With the advent of Distributed Systems and Microkernel Operating systems, IPC has been used for designing the system for cooperation. This raised the requirements for improving the communication and synchronization for the better performance of the system. Here, a mechanism of synchronization between the processes to reduce the waiting time of process using POSIX (Portable Operating System Interface) threads has been proposed to perform and synchronize the given task.

Online learning early skip decision method for the HEVC Inter process using the SVM‐based Pegasos algorithm

High efficient video coding (HEVC), the latest coding standard, has an encoding complexity much higher compared with H.264/advanced video coding (AVC). The greater efficiency in HEVC is obtained at much greater computational cost compared with AVC. A fast coding unit (CU) splitting algorithm is proposed for the HEVC encoder, which early terminates the CU partitioning process based on an adaptive classification model. This model is generated by an online learning method based on a Pegasos (primal estimated sub-gradient solver for SVM) algorithm. The proposed method is implemented over the HEVC reference implementation on its version 16.7. Experimental results show that the proposed method reduces the computational complexity of HEVC encoder to 35% without any loss, resulting in a 1% of Bjøntegaard Delta-rate gain in the low delay B configuration without any offline training phase.

A New Approach for Inter Process Communication with Hybrid of Message Passing Mechanism and Event based Software Architecture

In this paper, we use software architecture style based on event-driven and message passing communication method and determine a framework for interaction among practicable processes on Operating System (OS). In the proposed method, the required data are sent to the process or other processes in a standard message frame and with determined structure to the OS, then, the OS distributes the received message considering its recipient processes in the system, rather a process communicates directly with other specific process. The major features of the proposed method include the synchronization among the processes, the simplicity of implementation, easy extensibility, remote access which finally can improve the interaction between the OS and processes. Along with producing the systems based on an integrated frame, we obtain a determined standard in Inter Process Communication (IPC) by mediating an OS. Keywords: Event-driven, IPC, Message Passing, OS, Software Architecture

CDMA Technique with Inter-process Communication

A novel implementation of Inter process communication in CDMA NOC is proposed. In this study, the orthogonality properties of a Walsh code are used to route data packets between the IP-Cores.The asynchronous circuit design with combinational logic (Gate level design) is used for transmission and receiving circuits, along with ip-cores and reduces the processing time and resource utilization. The use of asynchronous pipelined core design process increases the operating frequency as well. The data transfers over IP-Core based interconnect is implemented on gate level. The latency and throughput values are obtained for variable payload size. The performance of asynchronous and synchronous communication are measured and analyzed.

Comparison of Collision Avoidance Algorithm for a Mobile Robot using a Simulation

This paper compares two collision avoidance algorithms using a simulator. The collision avoidance is vital for autonomous navigation of a mobile robot. Artificial potential field method and elastic force method are major approaches for the collision avoidance. The two algorithms are compared in the respect of the time for motion completion and the length of the motion path. The simulator is developed based on IPC(Inter Process Communication) and a differential drive mobile robot is used for the comparison.

Observations on Effect of IPC in GA Based Scheduling on Computational Grid

Computational Grid (CG) provides a wide distributed platform for high end compute intensive applications. Inter Process Communication (IPC) affects the performance of a scheduling algorithm drastically. Genetic Algorithms (GA), a search procedure based on the evolutionary computation, is able to solve a class of complex optimization problems. This paper proposes a GA based scheduling model observing the effect of IPC on the performance of scheduling in computational grid. The proposed model studies the effects of Inter Process Communication (IPC), processing rate () and arrival rate (). Simulation experiment, to evaluate the performance of the proposed algorithm is conducted and results reveal the effectiveness of the model.

Pre-applied Inter Chip Fill Material and Process for Advanced 3D Chip Stack

AbstractTo pursue further performance improvement of semiconductor devices, threedimensional (3D) chip integration with TSV would be one of the key technologies in the next decade. Inter Chip Fill (ICF) is a resin to fill gaps between chips, and it would be an important component for highly reliable and durable 3D integrated devices. High performance 3D devices require fine pitch interconnections with small bumps for high pin count with high bandwidth. Smaller bumps lead to narrow gap design between stacked chips inevitably, and the narrow gap is expected to reduce heat resistance and thermo-mechanical stress. However it makes resin filling and flux cleaning processes harder. A preapplied ICF process is one of the potential methods to fill the narrow gaps with a resin. The material is halfcured resin applied on a wafer by spin-coating or film-lamination before chip integration. Flux cleaning process can be eliminated by adding fluxing function in the resin components. Major concerns of multiple chip 3D stacking process are repeated high temperature cycles of metal-joining, and long process time as a result. We are proposing “Stack Joining process” that enables 3D multi chip joining at one time instead of sequential chip by chip joining. In this process, multiple chips are aligned and temporarily stacked sequentially using adhesivity which the ICF has between Tg and initiation temperature of polymerization, and finally all metal bumps of stacked chips are melted and joined altogether. This process can substantially reduces repeated high temperature cycles and process time. As a result this technique could mitigate degradation of device materials.We successfully stacked chips by using the pre-applied ICF which was designed for advanced 3D chip stack having full area array and narrow gap (less than 10um) connections. In this paper, we explain the Stack Joining process flow and conditions. We also discuss the cause of mechanical stress within the stacked chip and required material features of the pre-applied ICF and device structure to reduce the stress.

Remote scheduling of production activities: tools, paradigms and performance

Remote scheduling is a fast growing area of research in the wider area of Production Planning and Control (PP&C). Many solutions have been reported in the literature and many scheduling tools are currently available, however, the criteria for their evaluation and comparison remain loosely defined. This paper proposes an overview of existing solutions, highlighting their advantages and limitations, to support academics and industrial users in their choices of scheduling techniques and Inter Process Communication (IPC) solutions for the remote and online scheduling of production. This paper also proposes design guidelines and performance measures against which production managers can evaluate and improve their solutions.

GMAL:An Logic Programming Language for the Inter Process Communication in Distributed Environment

GMAL:An Logic Programming Language for the Inter Process Communication in Distributed Environment

Applications of CORBA in the ATLAS prototype DAQ

This paper presents the experience of using the Common Object Request Broker Architecture (CORBA) in the ATLAS prototype DAQ project. Many communication links in the DAQ system have been designed and implemented using the CORBA standard. A public domain package, called Inter-Language Unification (ILU) has been used to implement CORBA based communications between DAQ components in a local area network (LAN) of heterogeneous computers. The CORBA Naming Service provides the principal mechanism through which most clients of an ORE-based system locate objects that they intend to use. In our project, conventions are employed that meaningfully partition the name space of the Naming Service according to divisions in the DAQ system itself. The Inter Process Communication (IPC) package, implemented in C++ on the top of CORBA/ILU, incorporates this facility and hides the details of the naming schema is described. The development procedure and environment for remote database access using IPC is described. Various end-user interfaces have been implemented using the Java language that communicate with C++ servers via CORBA/ILU. To support such interfaces, a second implementation of IPC in Java has been developed. The design and implementation of such connections are described. An alternative CORBA implementation, ORBacus, has been evaluated and compared with ILU.