Interlayer Dielectrics Research Articles

300 mm wafer-level hybrid bonding for Cu/interlayer dielectric bonding in vacuum

Wafer bonding technology is one of the key technologies for high-density three-dimensional integration. We demonstrated 300 mm wafer-level hybrid bonding with Cu and an interlayer dielectric (ILD) layer with the design of 1 × 1 μm2 pads with 2 μm pitch. In this sequence of the bonding process, the structure of Cu bonding pads was controlled to be precisely convex to the ILD layer by chemical-mechanical polishing. Then the bonding process was performed in vacuum. Lastly, the bonded wafers were annealed at 200 °C for the postannealing process. As a result, hybrid wafer bonding with few voids was successfully accomplished.

Inter-tier electrostatic coupling effects in 3D sequential integration devices and circuits

This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.

Semi-aromatic thermosetting polyimide resins containing alicyclic units for achieving low melt viscosity and low dielectric constant

Semi-aromatic thermosetting polyimide resins containing alicyclic units were prepared by the polymerization of 1,2,4,5- cyclohexanetetrcarboxylic dianhydride (HPMDA), aromatic diamines and nadic anhydride (NA) served as reactive capping agent. To obtain the homogeneous poly (amic ester) (PAE) matrix resins, the 2-methoxyethanol (EGME) was used to esterify HPMDA. The chemical structure of PAE resins dried at different temperatures were characterized in detail by FT-IR, 1H NMR and TGA-GCMS. Compared with the full-aromatic API-1, the alicyclic units with less Pi(π) bonds and twisted structure endow the semi-aromatic PI resins with loose polymer chains packing and weak intermolecular forces, which contribute to low melt viscosities, good solubility and excellent dielectric properties. The cured semi-aromatic PI resins show low dielectric constants ranging from 2.8 to 3.0 and dielectric loss of <0.01 at a range of frequencies from 1GHz to 12GHz. The results indicate the semi-aromatic thermosetting PI resins are promising dielectric interlayer materials for high frequency substrates.

Structural, Optical and Dielectric Properties of Aluminoborosilicate Glasses

Glass samples with composition 50AO-5Al2O3-30B2O3-15SiO2 (A = Ba, Sr, Ca, Zn) have been synthesized by conventional melt quenching technique. The amorphous nature of glasses has been confirmed from the x-ray diffraction patterns. The structural behavior of the glasses investigated using Fourier transform infrared spectra show a number of absorption peaks due to the bending of Si-O-B linkages, stretching vibrations of Si-O-Si and B-O-B in SiO4 and BO4 structural units, respectively. The Fourier Transform Raman spectra of all glasses exhibit different spectral bands and intensities of all bands change with the doping of cations (Ba2+, Sr2+, Ca2+ and Zn2+).The optical properties studied using UV–visible absorption spectra, give Urbach energy values in the range 0.51–0.59 eV. The microhardness of the glass samples measured by indentation technique shows a higher value for all glasses (7.68–9.25) GPa, reflecting higher bond strength. The co-efficient of thermal expansion of the glasses lies within the range 8.5–11.5 × 10−6°C−1. Dielectric constant varies from 3.4 to 1.6 and dielectric loss from 0.0016 to 0.0342 at 1 MHz for 50AO-5Al2O3-30B2O3-15SiO2 (A = Ba, Sr, Ca, Zn) glasses. The good thermal, mechanical and dielectric properties show that these glasses can be considered as suitable candidates for interlayer dielectrics in microelectronic applications.

High-performance solution-processed colloidal quantum dots-based tandem broadband photodetectors with dielectric interlayer

Recently, great attention has been paid to IV–VI colloidal quantum dots (CQDs) for their high photosensitivity, solution processability and low cost. Also, metal halide perovskites are very promising materials to realize the high-performance solution-processed visible-light photodetectors due to their cost-effective manufacturing, tunable absorption and photoluminescence in whole visible spectrum. In this paper, we present solution-processed CQDs-based tandem broadband photodetectors with low dark-current and high-sensitivity by inserting dielectric Polymethyl methacrylate (PMMA) interlayer between two sub-detectors. Our experimental data showed that the tandem broadband photodetector ITO/PEDOT:PSS/CsPbBr3:PbS0.4Se0.6/ZnO/PVK/CsPbBr3:PbS0.4Se0.6/ZnO/Au showed a maximum specific detectivity of 6.8 × 1013 Jones with a responsivity of 27 A W−1 under 57.8 μW cm−2 980 nm illumination. The device performance can be further enhanced by inserting a 50 nm dielectric PMMA layer between the two sub-photodetectors. As the result, the tandem photodetector ITO/PEDOT:PSS/CsPbBr3:PbS0.4Se0.6/ZnO/PMMA(50 nm)/PVK/CsPbBr3:PbS0.4Se0.6/ZnO/Au exhibits a maximum specific detectivity of 1.32 × 1014 Jones with a responsivity of 27.72 A W−1 under 57.8 μW cm−2 of 980 nm laser. Further, the physical mechanisms for the enhanced performance are discussed in detail.

Benzoxazine Based High Performance Materials with Low Dielectric Constant: A Review

Interlayer dielectrics with low dielectric constant are the key to unlock the high arithmetic speed of integrated circuit, one of the kernels of modern industry. Polybenzoxazine, derived from benzoxazine precursor, is a new generation of phenolic resin that is considered as an ideal potential candidate for electronic materials due to its unique properties. However, for developing higher speed supercomputers, the dielectric property of conventional polybenzoxazine becomes the Achilles’ heel. Fortunately, the versatile design flexibility of benzoxazine chemistry provides the possibility to reduce the dielectric constant of the material. This review focuses on the recent attempts to synthesize low dielectric benzoxazine and the properties of the corresponding polybenzoxazine materials. Methods including fluorination, hydrocarbon introduction, heterocycle generation, molecular weight tailoring, copolymerization and organic-inorganic hybridization are introduced.

Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

AbstractThe developments in advanced interconnect technology for semiconductor logic devices for the mitigation of plasma‐induced damage to low‐dielectric‐constant (low‐k) materials, including fluorosilicate glass and carbon‐doped silicon oxide is reviewed. The chemical bond structures of low‐k materials are summarized to help mitigate the k value degradation caused by moisture uptake after plasma processes. Damage suppression is accomplished by integrating deposition chemistries, pattern etch transfer, and post‐etch cleaning technologies. On the basis of analyses results, a discussion on the bond engineering of low‐k materials and their degradation during plasma processing is given. Challenges facing low‐k interconnect technology are also addressed.

Hyperbranched‐polysiloxane‐based hyperbranched polyimide films with low dielectric permittivity and high mechanical and thermal properties

ABSTRACTA series of hyperbranched polysiloxane (HBPSi)‐based hyperbranched polyimide (HBPI) films with low dielectric permittivity and multiple branched structures are fabricated by copolymerizing 2,4,6‐triaminopyrimidine (TAP) with 4,4′‐(hexafluoroisopropylidene)diphthalic anhydride, 4,4′‐diaminodiphenyl ether, and HBPSi via the two‐step polymerization method. The dielectric permittivity of HBPSi hyperbranched polyimide films decreases with increasing TAP fraction, namely, from 3.28 for sample PI‐1 to 2.80 for PI‐4, mainly owing to the enlarged free volume created by the incorporation of multiple branched structures. Moreover, HBPSi HBPI possesses desirable solubility and good mechanical properties and thermal stability. PI‐4 not only has low dielectric permittivity (2.80, 1 MHz), excellent solubility (soluble in several common organic solvents), and remarkable thermal properties (glass‐transition temperature of 273 °C, 5% weight loss temperature of 498 °C in N2 and 486 °C in O2), but it also demonstrates admirable mechanical properties with a tensile strength of 103 MPa, elongation at break of 7.3%, and a tensile modulus of 2.16 GPa. HBPSi HBPI might have potential applications in interlayer dielectrics and other microelectronics fields. © 2019 Wiley Periodicals, Inc. J. Appl. Polym. Sci. 2019, 136, 47771.

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

As a possible pathway to continue Moore’s law indefinitely into the future as well as unprecedented beyond-Moore heterogeneous integration, we examine the prospects of building monolithic 3D integrated circuits (M3D-IC) with atomically-thin or 2D van der Waals materials in terms of overcoming the major drawbacks of current 3D-ICs, including low process thermal budget, inter-tier signal delay, chip-overheating, and inter-tier electrical interference problems. Our holistic evaluation includes consideration of the electrical performance, thermal issues, and electromagnetic interference as well as attention to the synthesis methods necessary for low-temperature transfer-free 2D materials growth in M3D fabrication. Both in-plane and out-of-plane heat-dissipation in 3D-ICs made with 2D materials are evaluated and compared with those of bulk materials. Electrostatic and high-frequency electric-field simulations are conducted to assess the screening effect by graphene and effect of scaling down the inter-layer dielectric (ILD) thickness. Our analysis reveals for the first time that the 2D-based M3D integration can offer >ten-folds higher integration density compared with through-silicon-via (TSV)-based 3D integration, and >150% integration density improvement with respect to conventional M3D integration. Therefore, 2D materials provide a significantly better platform, with respect to bulk materials (such as Si, Ge, GaN), for realizing ultra-high-density M3D-ICs of ultimate thinness for next-generation electronics.

Total Ionizing Dose Effects and Proton-Induced Displacement Damage on MoS2-Interlayer-MoS2Tunneling Junctions

Tunneling-dominated charge transport is demonstrated in vertically stacked MoS2/interlayer/MoS2 heterostructures with Al2O3, hexagonal boron nitride (h-BN), and HfO2 dielectrics. All devices are highly resistant to 10-keV X-ray irradiation. Only small transient changes in X-ray-induced photocurrent are observed as a result of trap creation in the thin interlayer dielectric, with rapid passivation. Samples with Al2O3 and h-BN interlayer dielectrics show significant increases in conduction current during proton irradiation, due to displacement-damage-induced defects that lower the effective tunnel-barrier height. Density-functional-theory calculations provide insights into the pertinent defects. Devices with HfO2 interlayer dielectrics show great promise for use in radiation tolerant, ultimately scaled tunnel FETs.

Correlating Coefficient of Friction and Shear Force to Platen Motor Current in Tungsten and Interlayer Dielectric Chemical Mechanical Planarization at Highly Non-Steady-State Conditions

Correlations between shear force and platen motor current (PMC), as well as those between coefficient of friction (COF) and PMC were investigated for various tungsten and interlayer dielectric (ILD) chemical mechanical planarization (CMP) cases where the processes were highly non steady-state. We chose to initially focus on non-steady-state conditions because we believed the relationships among shear force, COF and platen motor current to be clearer as opposed to steady-state conditions. Shear force, normal force and PMC data were collected from twelve different Stribeck+ curves at an acquisition frequency of 1,000 Hz and analyzed in order to determine any emerging trends. For the 12 cases, involving 8 pre-polished blanket CVD tungsten and 4 silicon dioxide blanket wafers, it was discovered that PMC closely mirrored shear force as evidenced by a high average correlation coefficient (0.955) and coefficient of determination (0.916) obtained from all runs. For COF vs. PMC, the average correlation coefficient and coefficient of determination for all cases were 0.758 and 0.608, respectively. These average values were dragged down by 5 cases in which the dominant tribological mechanism was found to be “boundary lubrication” where COF changed minimally with pseudo-Sommerfeld number.

Low threshold room-temperature UV surface plasmon polariton lasers with ZnO nanowires on single-crystal aluminum films with Al2O3 interlayers.

ZnO is one of the most promising optical gain media and allows lasing in ZnO nanowires at room temperature. Plasmonic lasers are potentially useful in applications in biosensing, photonic circuits, and high-capacity signal processing. In this work, we combine ZnO nanowires and single-crystalline aluminum films to fabricate Fabry–Perot type surface plasmon polariton (SPP) lasers to overcome the diffraction limit of conventional optics. High quality ZnO nanowires were synthesized by a vapor phase transport process via catalyzed growth. The ZnO nanowires were placed on a single-crystalline Al film grown by molecular beam epitaxy with an interlayer Al2O3 deposited by atomic layer deposition. The plasmonic laser is of metal-oxide-semiconductor (MOS) structure, compatible with silicon device processing. An optimal thickness of atomic layer deposited Al2O3 layer can lead to a low lasing threshold, 6.27 MW cm−2, which is 3 times and 12 times lower than that of previous reports for ZnO/Al and Zno/Al2O3/Al plasmonic lasers, respectively, owing to low materials loss. Both the thickness and quality of insulating layers were found to critically influence the lasing threshold of the SPP nanolasers in the subwavelength regime. The simulation results also manifest the importance of the quality of the dielectric interlayer.

High‐Tg porous polyimide films with low dielectric constant derived from spiro‐(adamantane‐2,9′(2′,7′‐diamino)‐fluorene)

ABSTRACTPorous polyimide (PI) films with low dielectric constants and excellent thermal properties have been a pressing demand for the next generation of high‐performance, miniature, and ultrathin microelectronic devices. A series of novel porous PI films containing fluorenyl‐adamantane groups were prepared successfully via thermolysis of poly(ethylene glycol) (PEG) added in the PI matrix. The cross‐sectional morphologies of porous PI films showed closed pores with diameters ranging from 135 to 158 nm, which were uniform and regular in shape without interconnectivity. These porous PI films exhibited excellent thermal properties with a glass‐transition temperature at 376 °C whereas the 5% weight loss temperature in air excess of 405 °C due to enhanced rigidity afforded by fluorenyl‐adamantane groups. Accompanied by thermolysis content of PEG increasing from 0 to 20 wt %, the density of porous PI films decreased, and the corresponding porosity grew significantly from 0 to 11.48%. Depending on porosity, the dielectric constant and dielectric loss of porous PI films significantly declined from 2.89 to 2.37 and from 0.050 to 0.021, respectively. These excellent properties benefit the as‐prepared porous PI films for application as interlayer dielectrics, integrated circuit chips, or multichip modules in microelectronic fields. © 2018 Wiley Periodicals, Inc. J. Appl. Polym. Sci. 2019, 136, 47313.

Inkjet Printing of SiO2 Hollow Spheres/Polyimide Hybrid Films for Foldable Low-k ILD

We demonstrate inkjet printing as a viable method for flexible interlayer dielectrics (ILDs) films with a low dielectric constant, excellent mechanical characteristics, and thermal properties in foldable organic light emitting diodes (OLEDs). SiO2 hollow spheres (SHSs)/polyimide (PI) hybrid films were printed by SiO2 coated polystyrene (PS) ink and PI ink. The relative permittivity of the hybrid films decreased from 3.45 to 1.87. The thermally stable PI fims maintained their weight below 500 °C from the TGA result. The dielectric constant and current density retained their properties after 50,000 cycles of bending at a 1 mm bend radius. We propose that the inkjet printing of SHSs/PI hybrid films described herein is a promising approach for flexible ILDs in foldable OLEDs.

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

Slow plasmon-polaritons in a bilayer metallic structure revealed by the lower-energy resonances of surface-enhanced Raman scattering.

Apart from the main plasmon-polariton resonance of the surface-enhanced Raman scattering (SERS) occurring at 480 - 530 nm, an additional resonance was observed for substrates with two silver layers separated by a dielectric layer which support extra plasmon modes with decreased group velocities. The novel SERS resonance is shifted towards lower energies and has comparable amplitude, its exact energy position being determined by the thickness of the dielectric interlayer. The experimental findings provide a ground for the engineering of SERS-substrates with the spectral position of the additional resonance matched with the photon energy of the pump laser over a fairly wide range of laser wavelengths.

A Terahertz CMOS V-Shaped Patch Antenna with Defected Ground Structure.

In this paper, a V-shaped patch antenna with defected ground structure is proposed at terahertz to overcome the limited performance of a standard complementary metal-oxide semiconductor (CMOS) patch antenna consisting of several metal layers and very thin interdielectric layers. The proposed V-shaped patch with slots allows the increased radiation resistance and broadband performance. In addition, the patch resonating at different frequency from the V-shaped patch is stacked on the top to broaden the impedance-matching bandwidth. More importantly, the slots are formed in the ground plane, which is called the defected ground structure, to further increase the radiation resistance and thus improve the bandwidth and efficiency. It is verified from electromagnetic simulations that the leakage waves from the defected ground can enhance the antenna directivity and gain by coherently interfering with the topside radiation. The proposed on-chip antenna is fabricated using a standard 65 nm CMOS process. The on-wafer measurement shows very wide bandwidth in input reflection coefficient (<−10 dB), greater than 28.7% from 240 to >320 GHz. The measured peak gain was as high as 5.48 dBi at 295 GHz. To the best of the authors’ knowledge, these results belong to the best performance among the terahertz CMOS on-chip antennas without using additional components or processes such as dielectric resonators, lens, or substrate thinning.

Polystyrene/Ceria Core/Shell Abrasive Based Slurry for Highly Enhanced Oxide-Film Polishing Rate and Scratch-Less in Chemical-Mechanical-Planarization

The SiO2-film chemical-mechanical-polishing (CMP) is essential process for Shallow Trench Isolation (STI) and Inter Layer Dielectric (ILD) CMP. The key performance parameters are high polishing rate and scratch-less in SiO2-film CMP. In SiO2-film CMP, wet-ceria was widely used for scratch-less SiO2-film CMP. However, the wet-Ceria abrasive has crystalline sharp <100>, <100>, and <111> facet, which resulted in generating scratches on SiO2-film by stick and slip mechanism after SiO2 CMP, as shown in Fig.1. Thus the scratches induced by wet-ceria abrasives can be a major cause of poor device operation and yield drop in the memory device manufacturing. In our study, therefore, we designed a novel SiO2-film CMP slurry using the PS/ceria core/shell as an abrasive to enhance SiO2-film polishing rate and scratch-less after SiO2-film CMP. PS/ceria core/shell particles were synthesized, which are relatively soft and round by using polystyrene and ceria particles. Figure 2(a) shows the synthesis mechanism of PS/ceria core/shell, illustrating that Ce4+ ion was added in the PS of negative charge to form Ce4+ seed on the surface and grow it during 7 h with 70 ℃. The TEM image of the synthesized PS/ceria core/shell was shown in Fig. 2(b). First, we investigated the polishing rate of SiO2-film using PS/ceria core/shell abrasives. The polishing rate of SiO2-film was 564 Å/min when using PS/ceria core/shell and 350 Å/min when using wet-ceria as abrasives, as shown in Fig.3. This result means that the real contact area of PS/ceria core/shell is larger than that of 70 nm size wet-ceria. Second, we measured the surface roughness [root-mean-square (RMS) at 10 x 10-um scanning area] of SiO2-film and the surface defect such as scratch after CMP. The surface roughness of SiO2-film was 0.327 nm using wet-ceria and 0.202 nm using PS/ceria core/shell, respectively, as shown in Fig. 4(a). The number of scratch was 51-ea in 10-mm2 area and the deepest depth of scratch was 18 nm using 70 nm size wet ceria. However, the number of scratch was 10-ea in 10-mm2 area and the deepest depth of scratch was 2.3 nm using PS/ceria core/shell, as shown in Fig. 4(b). These results indicate that the hardness of PS/ceria core/shell is smaller than that of 70 nm size wet-ceria. In our presentation, we will review the mechanism for improving CMP performance such as high polishing rate, low surface roughness and scratch-less after CMP when using the PS/ceria core/shell abrasive based slurry. * This research was supported by the MOTIE(Ministry of Trade, Industry & Energy (10085643) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. This work was financially supported by the Brain Korea 21 Plus Program in 2018 and Research & Business Development Program Announcement funded by the MOTIE (N0002026). Figure 1

Compact optical 90° hybrid based on hybrid plasmonic multimode interferometer

This paper presents an optical 90° hybrid based on a general 4×4 multimode interferometer (MMI), which is realized on hybrid plasmonic waveguides (HPW). First, we analyze the propagation characteristics of multi-order hybrid plasmonic modes in the HPW-MMI, and reveal that the optimal positions of self-images would shift from the theoretical ones. By optimizing the thickness of the dielectric interlayer of the HPW structure, the width and length of the multimode section, and especially by adjusting the position of the input and output waveguides, this HPW hybrid shows a maximum phase error of 0.7°, a transmission imbalance of 0.6 dB, and CMRRs of below −20 dB at the wavelength of 1550 nm.