Itanium Research Articles

AN OVERVIEW OF B+ TREE PERFORMANCE

Over the years, difference in speed between Central Processing Units or CPUs and main memory has become so much that lots of applications, including DBMSs, spend a lot of time waiting for data to be fetched from main-memory. B+ trees have been observed poorly utilizing the cache memory, which isleading to the development of many cache-conscious indices. Earlier simulation models were used to study cache conscious indices, the trend has recently gone towards measuring performance on real computer architectures, which means the performance is measured on real systems, instead of simulation models. In this study, we study the performance of the pB+ tree on the Itanium 2 processor, focusing on various implementation options and their effect on the performance.

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Lowering supply voltage is one of the most effective approaches for improving the energy efficiency of microprocessors. Unfortunately, technology limitations, such as process variability and circuit aging, are forcing microprocessor designers to add larger voltage guardbands to their chips. This makes supply voltage increasingly difficult to scale with technology. This paper presents a new mechanism for dynamically reducing voltage margins while maintaining the chip operating frequency constant. Unlike previous approaches that rely on special hardware to detect and recover from timing violations caused by low-voltage execution, our solution is firmware-based and does not require additional hardware. Instead, it relies on error correction mechanisms already built into modern processors. The system dynamically reduces voltage margins and uses correctable error reports raised by the hardware to identify the lowest, safe operating voltage. The solution adapts to core-to-core variability by tailoring supply voltage to each core's safe operating level. In addition, it exploits variability in workload vulnerability to low voltage execution. The system was prototyped on an HP Integrity Server that uses Intel's Itanium 9560 processors. Evaluation using SPECjbb2005 and SPEC CPU2000 workloads shows core power savings ranging from 18% to 23%, with minimal performance impact.

A statistical performance model of the opteron processor

Cycle-accurate simulation is the dominant methodology for processor design space analysis and performance prediction. However, with the prevalence of multi-core, multi-threaded architectures, this method has become highly impractical as the sole means for design due to its extreme slowdowns. We have developed a statistical technique for modeling multicore processors that is based on Monte Carlo methods. Using this method, processor models of contemporary architectures can be developed and applied to performance prediction, bottleneck detection, and limited design space analysis. To date, we have accurately modeled the IBM Cell, the Intel Itanium, and the Sun Niagara 1 and Niagara 2 processors [23, 22, 8]. In this paper, we present a work in progress which is applying this methodology to an out-of-order execution processor. We present the initial single-core model and results for the AMD Barcelona (Opteron) processor.

The impact of IBM Cell technology on the programming paradigm in the context of computer systems for climate and weather models

AbstractThe call for ever‐increasing model resolutions and physical processes in climate and weather models demands a continual increase in computing power. The IBM Cell processor's order‐of‐magnitude peak performance increase over conventional processors makes it very attractive to fulfill this requirement. However, the Cell's characteristics, 256 kB local memory per SPE and the new low‐level communication mechanism, make it very challenging to port an application. As a trial, we selected the solar radiation component of the NASA GEOS‐5 climate model, which: (1) is representative of column‐physics components (half of the total computational time), (2) has an extremely high computational intensity: the ratio of computational load to main memory transfers, and (3) exhibits embarrassingly parallel column computations. In this paper, we converted the baseline code (single‐precision Fortran) to C and ported it to an IBM BladeCenter QS20. For performance, we manually SIMDize four independent columns and include several unrolling optimizations. Our results show that when compared with the baseline implementation running on one core of Intel's Xeon Woodcrest, Dempsey, and Itanium2, the Cell is approximately 8.8x, 11.6x, and 12.8x faster, respectively. Our preliminary analysis shows that the Cell can also accelerate the dynamics component (∼25% total computational time). We believe these dramatic performance improvements make the Cell processor very competitive as an accelerator. Copyright © 2009 John Wiley & Sons, Ltd.

The VOLSCAT package for electron and positron scattering of molecular targets: A new high throughput approach to cross-section and resonances computation

VOLSCAT is a computer program which implements the Single Center Expansion (SCE) method to solve the scattering equation for the elastic collision of electrons/positrons off molecular targets. The scattering potential needed is calculated by on-the-fly calls to the external SCELib library for molecular properties, recently ported to GPU computing environment and ClearSpeed platforms, and made available by means of an Application Program Interface (SCELib-API) which is also provided with the VOLSCAT package in a beta version. The result is a high throughput approach to the solution of the complex e − / e + -molecule scattering problem, with allows for intensive calculations both for the number of systems which can be studied and for their size. Accurate partial and total elastic cross sections are produced in output together with the associated eigenphase sums. Indirect scattering processes arising from the formation of temporary negative ions can also be analyzed through the computation of the resonances' parameters. Program summary Program title: VOLSCAT V1.0 Catalogue identifier: AEEW_v1_0 Program summary URL: http://cpc.cs.qub.ac.uk/summaries/AEEW_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 4 618 353 No. of bytes in distributed program, including test data, etc.: 120 307 536 Distribution format: tar.gz Programming language: Fortran90 Computer: All SMP platforms based on AIX, Linux and SUNOS operating systems over SPARC, POWER, Intel Itanium2, X86, em64t and Opteron processors Operating system: SUNOS, IBM AIX, Linux RedHat (Enterprise), Linux SuSE (SLES) Has the code been vectorized or parallelized?: Yes. The parallel version in the present release of the code is limited to the OpenMP calculation of the exchange potential V FEGE or V SCE . The number of OpenMP threads can then be set in the input script. RAM: For a typical (isolated) biomolecule (e.g. Cytosine or Ribose) a converged calculation would require from 320 MB up to 2.5 GB. Word size: 64 bits Classification: 16.5 External routines: LAPACK (dsyev, dgetri, dgetrf) ( http://www.netlib.org/lapack/) Nature of problem: In this set of codes an efficient procedure is implemented to calculate partial cross section for the scattering between an electron/positron and a molecular target as a function of the collision energies. Solution method: The scattering equations are derived in the framework of the Single Center Expansion (SCE) procedure which allows the reduction of the original three-dimensional problem to a radial (one-dimensional) equation through the expansion of the scattering potential and the system wavefunction in a set of symmetry-adapted (real) spherical harmonics. The local part of the electrostatic interaction between the charged projectile (electron/positron) and the molecular target is provided in input by the SCELib library, which also provides the correlation and polarization corrections for the short-range and long-range part, respectively, of the interaction. A proper Application Programming Interface (API) is used by VOLSCAT to load the energy-independent part of the potential while the non-local exchange contribution is approximated by a local form and calculated on the fly in the VOLSCAT run for each desired collision energy. The resulting SCE one-dimensional homogeneous scattering equation is rewritten in an integral form by means of the standard Green's function technique resulting in a set of Volterra coupled equations which are solved to give the phase shifts and cross sections for any desired impact energy in terms of the partial components defined by the irreducible representations of the symmetry point group to which the target molecule belongs. The total cross section can then be straightforwardly calculated by summing over all the partial cross sections produced in the output. By the Breit–Wigner analysis of the eigenphase sum produced as a function of the energy one can also get information on the location of possible resonance states arising in the collision process. Restrictions: Depending on the molecular system under study and on the operating conditions the program may or may not fit into available RAM memory. Additional comments: A beta version of SCELib-API is included in the distribution package. Running time: The execution time strongly depends on the molecular target description and on the hardware/OS chosen, it is directly proportional to the ( r , θ , φ ) grid size and to the number of angular basis functions used.

SCELib3.0: The new revision of SCELib, the parallel computational library of molecular properties in the Single Center Approach

SCELib3.0: The new revision of SCELib, the parallel computational library of molecular properties in the Single Center Approach

HPC global file system performance analysis using a scientific-application derived benchmark

With the exponential growth of high-fidelity sensor and simulated data, the scientific community is increasingly reliant on ultrascale HPC resources to handle its data analysis requirements. However, to use such extreme computing power effectively, the I/O components must be designed in a balanced fashion, as any architectural bottleneck will quickly render the platform intolerably inefficient. To understand I/O performance of data-intensive applications in realistic computational settings, we develop a lightweight, portable benchmark called MADbench2, which is derived directly from a large-scale cosmic microwave background (CMB) data analysis package. Our study represents one of the most comprehensive I/O analyses of modern parallel file systems, examining a broad range of system architectures and configurations, including Lustre on the Cray XT3, XT4, and Intel Itanium2 clusters; GPFS on IBM Power5 and AMD Opteron platforms; a BlueGene/P installation using GPFS and PVFS2 file systems; and CXFS on the SGI Altix3700. We present extensive synchronous I/O performance data comparing a number of key parameters including concurrency, POSIX- versus MPI-IO, and unique- versus shared-file accesses, using both the default environment as well as highly tuned I/O parameters. Finally, we explore the potential of asynchronous I/O and show that only the two of the nine evaluated systems benefited from MPI-2’s asynchronous MPI-IO. On those systems, experimental results indicate that the computational intensity required to hide I/O effectively is already close to the practical limit of BLAS3 calculations. Overall, our study quantifies vast differences in performance and functionality of parallel file systems across state-of-the-art platforms – showing I/O rates that vary up to 75× on the examined architectures – while providing system designers and computational scientists a lightweight tool for conducting further analysis.

Optimization and Performance Modeling of Stencil Computations on Modern Microprocessors

Stencil-based kernels constitute the core of many important scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due primarily to the disparity between processor and main memory speeds. In this paper, we explore the impact of trends in memory subsystems on a variety of stencil optimization techniques and develop performance models to analytically guide our optimizations. Our work targets cache reuse methodologies across single and multiple stencil sweeps, examining cache-aware algorithms as well as cache-oblivious techniques on the Intel Itanium2, AMD Opteron, and IBM Power5. Additionally, we consider stencil computations on the heterogeneous multicore design of the Cell processor, a machine with an explicitly managed memory hierarchy. Overall our work represents one of the most extensive analyses of stencil optimizations and performance modeling to date. Results demonstrate that recent trends in memory system organization have reduced the efficacy of traditional cache-blocking optimizations. We also show that a cache-aware implementation is significantly faster than a cache-oblivious approach, while the explicitly managed memory on Cell enables the highest overall efficiency: Cell attains 88% of algorithmic peak while the best competing cache-based processor achieves only 54% of algorithmic peak performance.

Solving linear-quadratic optimal control problems on parallel computers

We discuss a parallel library of efficient algorithms for the solution of linear-quadratic optimal control problems involving large-scale systems with state-space dimension up to 𝒪(104). We survey the numerical algorithms underlying the implementation of the chosen optimal control methods. The approaches considered here are based on invariant and deflating subspace techniques, and avoid the explicit solution of the associated algebraic Riccati equations in case of possible ill-conditioning. Still, our algorithms can also optionally compute the Riccati solution. The major computational task of finding spectral projectors onto the required invariant or deflating subspaces is implemented using iterative schemes for the sign and disk functions. Experimental results report the numerical accuracy and the parallel performance of our approach on a cluster of Intel Itanium-2 processors.

Perfmon2: a leap forward in performance monitoring

This paper describes the software component, perfmon2, that is about to be added to the Linux kernel as the standard interface to the Performance Monitoring Unit (PMU) on common processors, including x86 (AMD and Intel), Sun SPARC, MIPS, IBM Power and Intel Itanium. It also describes a set of tools for doing performance monitoring in practice and details how the CERN openlab team has participated in the testing and development of these tools.

Updating an LU Factorization with Pivoting

We show how to compute an LU factorization of a matrix when the factors of a leading principle submatrix are already known. The approach incorporates pivoting akin to partial pivoting, a strategy we call incremental pivoting . An implementation using the Formal Linear Algebra Methods Environment (FLAME) application programming interface (API) is described. Experimental results demonstrate practical numerical stability and high performance on an Intel Itanium2 processor-based server.

Construction of speculative optimization algorithms

In modern processors, instructions to perform operations are often produced before it becomes known that this is required. Such an expedient, which is called speculative execution, helps to reveal parallelism at the instruction level. In the EPIC architectures, the speculative execution is completely controlled by the compiler, which makes it possible to avoid using complex hardware mechanisms for supporting speculative instruction production. Moreover, the idea of the speculative execution can be used by the compiler in machine-independent optimizations. The paper describes a scheme of construction of the speculative optimization that is based on the selection of properties of the control flow and data flow that are important from the optimization standpoint and on the estimation of the probabilities of their fulfillment. The probabilities found are used for searching and constructing advantageous speculative and bookkeeping transformations. For optimizations that include only speculative movements of instructions upwards along the control flow graph, on the basis of the suggested scheme, a method has been developed that includes algorithms for finding probabilities of data and control dependences, for estimating benefit of speculative movements, and for constructing a recovery code. On the basis of this method, an algorithm for the speculative scheduling of instructions for the Intel Itanium architecture has been developed and implemented. Specific features of its implementation and experimental results are described.

Scientific Application Performance On Leading Scalar and Vector Supercomputering Platforms

The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end computing (HEC) platforms, primarily because of their generality, scalability, and cost effectiveness. However, the growing gap between sustained and peak performance for full-scale scientific applications on conventional supercomputers has become a major concern in high performance computing, requiring significantly larger systems and application scalability than implied by peak performance in order to achieve desired performance. The latest generation of custom-built parallel vector systems have the potential to address this issue for numerical algorithms with sufficient regularity in their computational structure. In this work we explore applications drawn from four areas: magnetic fusion (GTC), plasma physics (LB-MHD-3D), astrophysics (Cactus), and material science (PARATEC). We compare performance of the vector-based Cray X1, X1E, Earth Simulator, NEC SX-8, with performance of three leading commodity-based super-scalar platforms utilizing the IBM Power3, Intel Itanium2, and AMD Opteron processors. Our work makes several significant contributions: a new data-decomposition scheme for GTC that (for the first time) enables a breakthrough of the teraflop barrier; the introduction of a new three-dimensional lattice Boltzmann magneto-hydrodynamic implementation used to study the onset evolution of plasma turbulence that achieves over 26 Tflop/s on 4800 ES processors; the highest per processor performance (by far) achieved by the full-production version of the Cactus ADM-BSSN; and the largest PARATEC cell size atomistic simulation to date. Overall, results show that the vector architectures attain unprecedented aggregate performance across our application suite, demonstrating the tremendous potential of modern parallel vector systems.

The efficiency of application of dual-processor computers for the analysis of the three-dimensional second harmonic generation problem

The efficiency of application of dual-processor computers, various operating systems, and library functions adapted to the used processors for increasing the execution speed of a computer program used for solving a system of two 3D nonlinear Schrodinger equations is analyzed. The computation speeds obtained on computers with 32-bit and 64-bit processors are compared. It is shown that the use of all mentioned possibilities and the Intel Itanium 2 processor provides from to threefold to tenfold total saving of time, depending on the operating system and the computer type. Parallelization of the algorithm for different operating systems in combination with the use of a library adapted to the processor can increase the program’s execution speed by a factor of 1.5–3.

What is Itanium Memory Consistency from the Programmer's Point of View?

A programmer-centric model describes the memory consistency rules of amultiprocessor as a collection, one for each processor, of 'views' of instructions and some agreements between these views. It also requires the natural notion of validity: the value read from a shared memory location is the one that was most recently stored, according to a given view. This allows reasoning about programs at a non-operational level in the natural way, not obscured by the implementation details of the underlying architecture. In this paper, we formulate a programmer-centric description of the memory consistency model provided by the Itanium architecture. However, our definition is not tight. We provide two very similar definitions and show that the specification of the Itanium memory model lies between the two. These two definitions are motivated by slightly different implementations of load-acquire instructions. A further entertainment of a handful of other load-acquire rules leads us to question whether the specification of the Itanium memory order [Intel Corporation. A formal specification of the intel itanium processor family memory ordering. http://www.intel.com/, Oct 2002] is indeed faithful to the Itanium architecture intentions.

Scientific Computing Kernels on the Cell Processor

Scientific Computing Kernels on the Cell Processor Samuel Williams, John Shalf, Leonid Oliker Shoaib Kamil, Parry Husbands, Katherine Yelick Computational Research Division Lawrence Berkeley National Laboratory Berkeley, CA 94720 { swwilliams,jshalf,loliker,sakamil,pjrhusbands,kayelick } @lbl.gov ABSTRACT The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power de- mands has become of utmost concern to computational sci- entists. As a result, the high performance computing com- munity is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end com- puting systems. Our work contains several novel contribu- tions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil com- putations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the ac- curacy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell per- formance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different map- pings of the kernels and demonstrates a simple and effective programming model for Cell’s unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency. INTRODUCTION Over the last decade the HPC community has moved to- wards machines composed of commodity microprocessors as a strategy for tracking the tremendous growth in processor performance in that market. As frequency scaling slows and the power requirements of these mainstream processors con- tinue to grow, the HPC community is looking for alternative architectures that provide high performance on scientific ap- plications, yet have a healthy market outside the scientific community. In this work, we examine the potential of the recently-released STI Cell processor as a building block for future high-end computing systems, by investigating perfor- mance across several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil com- putations on regular grids, as well as 1D and 2D FFTs. Cell combines the considerable floating point resources re- quired for demanding numerical algorithms with a power- efficient software-controlled memory hierarchy. Despite its radical departure from previous mainstream/commodity pro- cessor designs, Cell is particularly compelling because it will be produced at such high volumes that it will be cost- competitive with commodity CPUs. The current implemen- tation of Cell is most often noted for its extremely high per- formance single-precision arithmetic, which is widely consid- ered insufficient for the majority of scientific applications. Although Cell’s peak double precision performance is still impressive relative to its commodity peers (˜14.6 Gflop/s @ 3.2GHz), we explore how modest hardware changes could significantly improve performance for computationally in- tensive double precision applications. This paper presents several novel results and expands our previous efforts [37]. We present quantitative performance data for scientific kernels that compares Cell performance to leading superscalar (AMD Opteron), VLIW (Intel Ita- nium2), and vector (Cray X1E) architectures. We believe this study examines the broadest array of scientific algo- rithms to date on Cell. We developed both analytical mod- els and lightweight simulators to predict kernel performance that we demonstrated to be accurate when compared against published Cell hardware results, as well as our own imple- mentations on a 3.2GHz Cell blade. Our work also explores the complexity of mapping several important scientific algo- rithms onto the Cell’s unique architecture in order to lever- age the large number of available functional units and the software-controlled memory. Additionally, we propose mod- est microarchitectural modifications that would increase the efficiency of double-precision arithmetic calculations com- pared with the current Cell implementation. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency. We exploit Cell’s heterogeneity not in computation, but in control and system support. Thus we conclude that Cell’s heterogeneous multi-core implementation is inherently better suited to the HPC environment than homogeneous commodity multicore

Scientific computing Kernels on the cell processor

In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end scientific computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key numerical kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. Next, we validate our model by comparing results against published hardware data, as well as our own Cell blade implementations. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different kernel implementations and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

Optimal register reassignment for register stack overflow minimization

Architectures with a register stack can implement efficient calling conventions. Using the overlapping of callers' and callees' registers, callers are able to pass parameters to callees without a memory stack. The most recent instance of a register stack can be found in the Intel Itanium architecture. A hardware component called the register stack engine (RSE) provides an illusion of an infinite-length register stack using a memory-backed process to handle overflow and underflow for a physically limited number of registers. Despite such hardware support, some applications suffer from the overhead required to handle register stack overflow and underflow. The memory latency associated with the overflow and underflow of a register stack can be reduced by generating multiple register allocation instructions within a procedure [Settle et al. 2003]. Live analysis is utilized to find a set of registers that are not required to keep their values across procedure boundaries. However, among those dead registers, only the registers that are consecutively located in a certain part of the register stack frame can be removed. We propose a compiler-supported register reassignment technique that reduces RSE overflow/underflow further. By reassigning registers based on live analysis, our technique forces as many dead registers to be removed as possible. We define the problem of optimal register reassignment, which minimizes interprocedural register stack heights considering multiple call sites within a procedure. We present how this problem is related to a path-finding problem in a graph called a sequence graph . We also propose an efficient heuristic algorithm for the problem. Finally, we present the measurement of effects of the proposed techniques on SPEC CINT2000 benchmark suite and the analysis of the results. The result shows that our approach reduces the RSE cycles by 6.4% and total cpu cycles by 1.7% on average.

Multimillion Atom Simulations of Dynamics of Oxidation of an Aluminum Nanoparticle and Nanoindentation on Ceramics

We have developed a first-principles-based hierarchical simulation framework, which seamlessly integrates (1) a quantum mechanical description based on the density functional theory (DFT), (2) multilevel molecular dynamics (MD) simulations based on a reactive force field (ReaxFF) that describes chemical reactions and polarization, a nonreactive force field that employs dynamic atomic charges, and an effective force field (EFF), and (3) an atomistically informed continuum model to reach macroscopic length scales. For scalable hierarchical simulations, we have developed parallel linear-scaling algorithms for (1) DFT calculation based on a divide-and-conquer algorithm on adaptive multigrids, (2) chemically reactive MD based on a fast ReaxFF (F-ReaxFF) algorithm, and (3) EFF-MD based on a space-time multiresolution MD (MRMD) algorithm. On 1920 Intel Itanium2 processors, we have demonstrated 1.4 million atom (0.12 trillion grid points) DFT, 0.56 billion atom F-ReaxFF, and 18.9 billion atom MRMD calculations, with parallel efficiency as high as 0.953. Through the use of these algorithms, multimillion atom MD simulations have been performed to study the oxidation of an aluminum nanoparticle. Structural and dynamic correlations in the oxide region are calculated as well as the evolution of charges, surface oxide thickness, diffusivities of atoms, and local stresses. In the microcanonical ensemble, the oxidizing reaction becomes explosive in both molecular and atomic oxygen environments, due to the enormous energy release associated with Al-O bonding. In the canonical ensemble, an amorphous oxide layer of a thickness of approximately 40 angstroms is formed after 466 ps, in good agreement with experiments. Simulations have been performed to study nanoindentation on crystalline, amorphous, and nanocrystalline silicon nitride and silicon carbide. Simulation on nanocrystalline silicon carbide reveals unusual deformation mechanisms in brittle nanophase materials, due to coexistence of brittle grains and soft amorphous-like grain boundary phases. Simulations predict a crossover from intergranular continuous deformation to intragrain discrete deformation at a critical indentation depth.

Performance comparison of data-reordering algorithms for sparse matrix–vector multiplication in edge-based unstructured grid computations

SUMMARY Several performance improvements for finite-element edge-based sparse matrix–vector multiplication algorithms on unstructured grids are presented and tested. Edge data structures for tetrahedral meshes and triangular interface elements are treated, focusing on nodal and edges renumbering strategies for improving processor and memory hierarchy use. Benchmark computations on Intel Itanium 2 and Pentium IV processors are performed. The results show performance improvements in CPU time ranging from 2 to 3. Copyright 2005 John Wiley & Sons, Ltd.