Integration Of Transistors Research Articles

(Invited) 3D Monolithic Integration in Flexible Organic Printed Transistors

Despite the significant enhancements in material properties such as carrier mobility, few attempts have been made to print organic integrated circuits (ICs). The relatively large size of printed features (typically 10 μm – 100 μm) have limited the implementation of organic ICs with reasonable transistor densities. To overcome the limitation, we introduce three-dimensional (3D) integration of inkjet-printed organic transistors and circuits. We fabricated a p-type organic field-effect transistor that is inkjet-printed on top of an n-type organic field-effect transistor with a shared gate joining the two transistors. Based on the common-gate transistor-on-transistor structure, a complementary inverter array is fabricated with a high static noise margin and reliable characteristics. We have further developed 3D integration of a dual-gate NAND technology fabricated by printing technique with a demonstration of flexible logic circuits. The vertical stacking of independent-gate controlled dual gate transistors offers enhanced on-current, lowered sub-threshold swing, increased device stability and density. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs, and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices

Molecularly selective nanoporous membrane-based wearable organic electrochemical device for noninvasive cortisol sensing.

Wearable biosensors have emerged as an alternative evolutionary development in the field of healthcare technology due to their potential to change conventional medical diagnostics and health monitoring. However, a number of critical technological challenges including selectivity, stability of (bio)recognition, efficient sample handling, invasiveness, and mechanical compliance to increase user comfort must still be overcome to successfully bring devices closer to commercial applications. We introduce the integration of an electrochemical transistor and a tailor-made synthetic and biomimetic polymeric membrane, which acts as a molecular memory layer facilitating the stable and selective molecular recognition of the human stress hormone cortisol. The sensor and a laser-patterned microcapillary channel array are integrated in a wearable sweat diagnostics platform, providing accurate sweat acquisition and precise sample delivery to the sensor interface. The integrated devices were successfully used with both ex situ methods using skin-like microfluidics and on human subjects with on-body real-sample analysis using a wearable sensor assembly.

Solution Processed Metal Oxide High-κ Dielectrics for Emerging Transistors and Circuits.

The electronic functionalities of metal oxides comprise conductors, semiconductors, and insulators. Metal oxides have attracted great interest for construction of large-area electronics, particularly thin-film transistors (TFTs), for their high optical transparency, excellent chemical and thermal stability, and mechanical tolerance. High-permittivity (κ) oxide dielectrics are a key component for achieving low-voltage and high-performance TFTs. With the expanding integration of complementary metal oxide semiconductor transistors, the replacement of SiO2 with high-κ oxide dielectrics has become urgently required, because their provided thicker layers suppress quantum mechanical tunneling. Toward low-cost devices, tremendous efforts have been devoted to vacuum-free, solution processable fabrication, such as spin coating, spray pyrolysis, and printing techniques. This review focuses on recent progress in solution processed high-κ oxide dielectrics and their applications to emerging TFTs. First, the history, basics, theories, and leakage current mechanisms of high-κ oxide dielectrics are presented, and the underlying mechanism for mobility enhancement over conventional SiO2 is outlined. Recent achievements of solution-processed high-κ oxide materials and their applications in TFTs are summarized and traditional coating methods and emerging printing techniques are introduced. Finally, low temperature approaches, e.g., ecofriendly water-induced, self-combustion reaction, and energy-assisted post treatments, for the realization of flexible electronics and circuits are discussed.

Silicon-on-insulator with hybrid orientations for heterogeneous integration of GaN on Si (100) substrate

Heterogeneous integration of materials pave a new way for the development of the microsystem with miniaturization and complex functionalities. Two types of hybrid silicon on insulator (SOI) structures, i.e., Si (100)-on-Si (111) and Si (111)-on-Si (100), were prepared by the smart-cut technique, which is consist of ion-slicing and wafer bonding. The precise calculation of the lattice strain of the transferred films without the epitaxial matching relationship to the substrate was demonstrated based on X-ray diffraction (XRD) measurements. The XRD and Raman measurement results suggest that the transferred films possess single crystalline quality. With a chemical mechanical polishing (CMP) process, the surface roughness of the transferred thin films can be reduced from 5.57 nm to 0.30 nm. The 4-inch GaN thin film epitaxially grown on the as-prepared hybrid SOI of Si (111)-on-Si (100) by metalorganic chemical vapor deposition (MOCVD) is of improved quality with a full width at half maximum (FWHM) of 672.54 arcsec extracted from the XRD rocking curve and small surface roughness of 0.40 nm. The wafer-scale GaN on Si (111)-on-Si (100) can serve as a potential platform for the one chip integration of GaN-based high electron mobility transistors (HEMT) or photonics with the Si (100)-based complementary metal oxide semiconductor (CMOS).

Solving the integration problem of one transistor one memristor architecture with a Bi-layer IGZO film through synchronous process

This study demonstrates the integration of a thin film transistor (TFT) and resistive random-access memory (RRAM) to form a one-transistor-one-resistor (1T1R) configuration. With the concept of the current conducting direction in RRAM and TFT, a triple-layer stack design of Pt/InGaZnO/Al2O3 is proposed for both the switching layer of RRAM and the channel layer of TFT. This proposal decreases the complexity of fabrication and the numbers of photomasks required. Also, the robust endurance and stable retention characteristics are exhibited by the 1T1R architecture for promising applications in memory-embedded flat panel displays.

Mapping Strain/Pressure with ZnO Nanowire Arrays By Piezotronic and Piezo-Phototronic Effect

Emulation of human senses via electronic means has long been a grand challenge in research of artificial intelligence as well as prosthetics, and is of pivotal importance for developing intelligently accessible and natural interfaces between human/environment and machine. Unlike other senses (seeing, hearing, smelling and tasting), capability of skin for touch sensing remains stubbornly difficult to be mimicked, which necessitates the development of large-scale pressure sensor arrays with high spatial-resolution, high-sensitivity and fast response. In this talk, we present a novel design of ZnO nanowire arrays, which can be used to directly record the strain distribution by piezotronic and piezo-phototronic effect. First, we have reported large-array three-dimensional (3D) circuitry integration of piezotronic transistors based on vertical zinc oxide nanowires as active taxel-addressable pressure/force-sensor matrix for tactile imaging with a high resolution of 100 μm1. Using the piezoelectric polarization charges created at metal-semiconductor interface under strain to gate/modulate transport process of local charge carriers, piezotronic effect has been applied to design independently addressable two-terminal transistor arrays, which convert mechanical stimuli applied on the devices into local electronic controlling signals. The device matrix has been demonstrated for achieving shape-adaptive high-resolution tactile imaging and self-powered, multi-dimensional active sensing. However, the signal of the piezotronic transistors array is the change of the resistance of each NWs, which can only be measured in a series way. That means such piezotronic transistors array can only mapping a static strain. Different with the electrical signal, the optical signal can be measured in a parallel way. And in our previous work, we have demonstrated how the piezo-phototronic effect can be effectively utilized to enhance the emission intensity of an n-ZnO/p-GaN NW LED. The emission light intensity and injection current at a fixed applied voltage has been enhanced by a factor of 17 and 4 after applying a 0.093% compressive strain, respectively. Here, we extend the single NW device to NW LEDs array, for pressure/force sensor arrays for mapping strain with a resolution as high as 2.7 μm. Such sensors are capable of recording spatial profiles of pressure distribution, and the tactile pixel area density of our device array is 6250000/cm2, which is much higher than the number of tactile sensors in recent reports (~ 6-27/cm2) and mechanoreceptors embedded in the human fingertip skins (~ 240/cm2). When the device is under pressure, the images unambiguously show that the change in LED intensity occurred apparently at the pixels that were being compressed by the molded pattern, while those were off the molded characters showed almost no change in LED intensity. Instead of using the cross-bar electrodes for sequential data output, the pressure image is read out in parallel for all of the pixels at a response and recovery time-resolution of 90 ms. This may be a major step toward digital imaging of mechanical signals by optical means, with potential applications in touch pad technology, personalized signatures, bio-imaging and optical MEMS. Furthermore, our recent studies achieve such piezo-phototronic effect induced strain mapping in a flexible n-ZnO NWs/p-polymer LEDs array system composed of PEDOT:PSS and patterned ZnO NWs with a spatial resolution of 7 μm for mapping of spatial pressure distributions. The emission intensity of the LED array sensor matrix is dominated by locally applied strains as indicated by piezo-phototronic effect. Therefore, spatial pressure distributions are immediately obtained by parallel-reading the illumination intensities of LED arrays based on electroluminescence working mechanism. A wide range of pressure measurements from 40 MPa to 100 MPa was achieved through controlling the growth conditions of ZnO nanowire array. Lastly, the piezo-phototronic effect was achieved on Si wafer based on a n-ZnO nanofilm/p-Si micropillar heterostructure (ZSH) LEDs array. White light emissions at room temperature, featuring with emission peaks in both visible and near-infrared regions were obtained. By applying a strain onto the top of the ZSH LEDs, the light emission intensity of ZSH LEDs array was enhanced as well by 120% under -0.05% compressive strains. A pressure map can be created by reading out in parallel the change of the electroluminescent intensities from all the pixels in the near future. This research not only introduce a novel approach to fabricate Si-based light-emitting components with high performances, but also may be a great step toward digital imaging of mechanical signals using optical means, having potential applications in artificial skin, touch pad technology, personalized signatures, bio-imaging and optical MEMS, and even and smart skin.

Sustainability-Oriented Evaluation and Optimization for MPSoC Task Allocation and Scheduling under Thermal and Energy Variations

Aiming at high performance, more and more Cyber-Physical Systems (CPSs) adopt Multiprocessor System-on-Chips (MPSoCs) as computation units. However, due to increasing integration of transistors on a die, the power densities together with performance variations of MPSoC chips have been increasing dramatically. Consequently, the MPSoC-based CPSs might become unsustainable and unreliable. Although various Task Allocation and Scheduling (TAS) heuristics have been proposed to minimize the hotspot time (i.e., duration of thermal emergency) and energy consumption of MPSoC designs, few of them can guarantee the highest performance yield under process variations without violating energy, thermal and timing constraints. To address these challenges, this paper proposes a novel energy- and thermal-aware TAS evaluation and optimization framework. Based on statistical model checking techniques, our approach enables accurate modeling and reasoning of the performance yield of real-time MPSoC designs under joint energy and thermal constraints. To enable system-level design space exploration, we propose a regression analysis-based method that can drastically reduce the overall exploration efforts. Experimental results show that our fully-automated approach can not only allow accurate sustainability-oriented reasoning of TAS solutions under specified thermal and energy constraints, but also enable the quick search of optimal TAS solutions on different MPSoC architectures with the highest performance yield.

Special Issue on Innovative SiC/GaN/Diamond Single-Crystal Substrates and Planarization Processing Technologies for the Next Generation ICT Society

Since the transistor was invented at Bell Laboratories in 1947 and the concept of the integrated circuit was presented by Jack Kilby of TI in 1958, devices using silicon semiconductors have been developed with tremendous drive. Today, ultrastructural, highly dense, and high-functional ULSI devices have become a reality. Accordingly, novel, three-dimensional devices that aim at multiple functions and high performance have been proposed, and novel materials have come into existence. As Artificial Intelligence (AI) has drawn increasing attention, the concept of “Singularity,” or singular technical point, has become a focus of great attention. Singularity is a prediction put forth by American futurist Ray Kurzweil, who said, “Singularity will come in 2045, when the speed of the evolution of technology will become infinite and Artificial Intelligence will exceed human intelligence.” This prediction is said to have its roots in “Moore’s law,” formulated by Intel founder Gordon Moore, which states that “the degree of integration of transistors doubles every year and a half.” The deep learning and self-learning functions of computers can be mentioned as significant driving factors behind the dramatic development of AI studies. The processing capacity of AI has increased exponentially owing to the evolution and combination of various technologies, and the speed of development of technology now far exceeds the biological limits of humankind. As a result, it is inevitable that “Singularity” will come to pass, and the technologies behind semiconductor devices contributing to the arrival of Singularity are expected to develop much further. In the process of such semiconductor development, silicon carbide (SiC), among other materials, came to be expected as the next-generation semiconductor in the 1950s, but it could not succeed significantly as a practical device. SiC also attracted attention as the material used in green and red light-emitting elements. In the 1990s, SiC came into the spotlight, along with gallium nitride (GaN) crystal and other materials, by being put into practical use as the material used in blue light-emitting diodes. Today, as the silicon (Si) as power devices have already approached the physical limits of the material, next-generation devices focus on semiconductor substrates such as SiC and GaN, which have performance indexes tens to thousands of times higher than the Si semiconductor. Especially, high-power devices and high-frequency devices have attracted special attention, because the use of semiconductor devices in the automotive and other fields has increased dramatically. Furthermore, the single-crystal substrate of semiconducting diamond is considered to be the ultimate semiconductor device, so this topic has been vigorously researched. The above-mentioned next-generation devices are called green devices because they could reduce power consumption and carbon dioxide emissions tremendously, leading to the realization of a low-carbon and energy-saving society. Such devices are utilized not only as high-power semiconductors and light-emitting semiconductors but also as various sensors, including gas sensors and UV sensors, as well as MEMS devices. Further application of such devices is expected in the future. To actually produce the high-performance and multifunctional green devices, it will be necessary to establish the technologies for device integration and the manufacturing process. An example would be the process of growing crystals that are larger in diameter and higher in quality. The substrate materials applied in such technologies, including SiC, GaN, and diamond, are known as ultra-hard-to-process materials: their extreme mechanical and chemical stability makes the general manufacturing process much more difficult. A breakthrough is needed to solve this problem. Many challenges must be overcome systematically to produce a high-performance green device, as the device to which such crystalline materials are applied will reduce power consumption and carbon dioxide emissions extremely effectively. This special issue focuses on manufacturing processes, including the planarization processing of every kind of hard-to-process crystal substrate, involved in producing green devices, sensors, etc. And the paper on the various applications of the device are published in this issue. This issue is expected to contribute to the establishment of a process for manufacturing green devices, which is an essential industrial strategy, as well as to future intensive studies in this field.

Integration of organic electrochemical transistors and immuno-affinity membranes for label-free detection of interleukin-6 in the physiological concentration range through antibody-antigen recognition.

We demonstrate the label-free and selective detection of interleukin-6 (IL-6), a key cell-signaling molecule in biology and medicine, by integrating an OECT with an immuno-affinity regenerated cellulose membrane. The objective of the membrane is to increase the local concentration of IL-6 at the sensing electrode and, thereby, enhance the device response for concentrations falling within the physiological concentration range of cytokines. The OECT gate electrode is functionalized with an oligo(ethylene glycol)-terminated self-assembled alkanethiolate monolayer (SAM) for both the immobilization of anti IL-6 antibodies and the inhibition of non-specific biomolecule binding. The OECT gate/electrolyte interface is exploited for the selective detection of IL-6 through the monitoring of antigen-antibody binding events occurring at the gate electrode.

Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs).

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an ION/IOFF ratio of more than 106 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

An innovative large scale integration of silicon nanowire-based field effect transistors

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Inverter circuits on freestanding flexible substrate using ZnO nanoparticles for cost-efficient electronics

Driven by the Internet of Things (IoT), flexible and transparent smart systems have been intensively researched by the scientific community and by several companies. This technology is already available for consumers in a wide range of innovative products, e.g., flexible displays, radio-frequency identification tags and wearable electronic skins which, for instance, collect and analyze data for medical applications. For these systems, thin-film transistors (TFTs) are the key elements responsible for the driving currents. Solution-based materials such as nanoparticle dispersions avail the fabrication on large-area substrates with high throughput processes. In this study, we discuss the integration of ZnO nanoparticle thin-film transistors and inverter circuits on freestanding polymeric substrates enclosing the main issues concerning the transfer of the integration process from a rigid substrate to a flexible one. The TFTs depict VON between −0.2 and 1V, ION/IOFF>104 and field-effect mobility >0.5cm2V−1s−1. Additionally, in order to enhance the transistors and inverters performance, an adaptation on the device configuration, from an inverted coplanar to an inverted staggered setup, was conducted and analyzed. By employing the inverted staggered setup a considerable increase in the contact quality between the semiconductor and the drain and source electrodes was observed. As the integrated devices depict electrical characteristics which enable the fabrication of electronic circuits for the low-cost sector, inverters were fabricated and characterized, evaluating the circuit’s gain as function of the applied supply voltage and circuit’s geometric ratio.

Top-Down Integration of Molybdenum Disulfide Transistors with Wafer-Scale Uniformity and Layer Controllability.

The lack of stable and efficient techniques to synthesize high-quality large-area thin films is one of the major bottlenecks for the real-world application of the 2D transition metal dichalcogenides. In this work, the growth of molybdenum disulfide (MoS2 ) on sapphire substrates by sulfurizing the MoO3 film deposited by atomic layer deposition (ALD) is reported. The advantages of the ALD method can be well inherited, and the synthesized MoS2 films exhibit excellent layer controllability, wafer-scale uniformity, and homogeneity. MoS2 films with desired thickness can be obtained by varying MoO3 ALD cycles. The atomic force microscope and Raman measurements demonstrate that the ALD-based MoS2 has good uniformity. Clear Raman shift as a function of the film thickness is observed. Field-effect transistor devices are fabricated through a transfer-free and top-down process. High On/Off current ratio (≈104 ) and medium-level electron mobilities (≈0.76 cm2 V-1 s-1 for monolayer, and 5.9 cm2 V-1 s-1 for four-layer) are obtained. The work opens up an attractive approach to realize the application of wafer-scale 2D materials in integrated circuits and systems.

A New Digital OptoElectronic Switch (DOES) Laser

A new laser structure is introduced which is unique in its potential for the optoelectronic integration of lasers and transistors. The laser is based on the combination of conjugate quantum well modulation doped interfaces, such that n-type and p-type inversion channels are available. Overall, the electrical behaviour of the laser is that of a thyristor with the cw operation of the laser being obtained in the low resistance on state. In this paper, the laser is analyzed on the basis of no-k selection to develop the appropriate rate equations. The $I$ – $V$ relations of thyristor are then developed and combined with the optical rate equations of the quantum wells to predict the threshold voltage. Then, the threshold current, the electrical efficiency of each quantum well set, and the overall slope efficiency of the laser are obtained. The results are compared with the corresponding p-i-n laser with the same photon lifetime. In a following paper, the first demonstration of the laser is reported.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance–voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Guest Editors’ Introduction: Computing in the Dark Silicon Era

In the Post-dennard’s scaling era of nanoscale CMOS devices, due to the slowdown of the supply voltage scaling, high integration of transistors per unit area leads to escalated trends of (local) power density and thermal profiles. Coupled with the physical limits imposed by device packaging and cooling technology on the peak power and peak power density, this results in the so-called “dark silicon problem.” That is, a significant amount of computation, communication, and memory resources of an on-chip system cannot simultaneously be powered-on (at the peak performance level) for a given thermal design power (TDP) constraint and thus must stay “dark” (i.e., power-gated) or “dim” (i.e., in low-power states). The emergence of dark silicon introduces several new challenges on the design, architecture, and test communities concerning various design abstractions, for instance, how to best utilize the abundance of (potentially dark) transistors, both in terms of design time provisioning and runtime management, so as to improve quality metrics (such as performance and reliability) within peak power and thermal constraints.

Chip-by-chip configurable interconnection using digital printing techniques

Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results.

Monolithic integration of InGaAs n-FETs and lasers on Ge substrate.

We report the first monolithic integration of InGaAs channel field-effect transistors with InGaAs/GaAs multiple quantum wells (MQWs) lasers on a common platform, achieving a milestone in the path of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers used for realizing transistors and lasers were grown epitaxially on the Ge substrate using molecular beam epitaxy (MBE). A Si-CMOS compatible process was developed to realize InGaAs n-FETs with subthreshold swing SS of 93 mV/decade, ION/IOFF ratio of more than 4 orders of magnitude with very low off-state leakage current, and a peak effective mobility of more than 2000 cm2/V·s. In addition, fabrication process uses a low overall processing temperature (≤ 400 °C) to maintain the high quality of the InGaAs/GaAs MQWs for the laser. Room temperature electrically-pumped lasers with a lasing wavelength of 1.03 µm and a linewidth of less than 1.7 nm were realized.

Energy minimization for on-line real-time scheduling with reliability awareness

Proposed closed form formulas to quantify static and dynamic system reliability.Proposed an energy efficient on-line algorithm under reliability constraint.Theoretically analyzed the performance of the proposed algorithm.The proposed algorithms significantly outperform the existing related work. Display Omitted Under current development of semiconductor technology, there is an exponential increase in transistor density on a single processing chip. This aggressive transistor integration significantly boosts the computing performance. However, it also results in a power explosion, which immediately decreases the system reliability. Moreover, some well-known power/energy reduction techniques, i.e. Dynamic Voltage and Frequency Scaling (DVFS), can cause adverse impact on system reliability. How to effectively manage the power/energy consumption, meanwhile keep the system reliability under control, is critical for the design of high performance computing systems. In this paper, we present an online power management approach to minimize the energy consumption for single processor real-time scheduling under reliability constraint. We formally prove that the proposed algorithm can guarantee the system reliability requirement. Our simulation results show that, by exploiting the run-time dynamics, the proposed approach can achieve more energy savings over previous work under reliability constraint.

Wideband millimetre‐wave CMOS power amplifier using transistor‐based inductive source degeneration and specially shielded transformer

This study presents integration of transistor based inductive source degeneration and specially shielded transformer into a millimetre-wave power amplifier (mm-wave PA) operating at wideband. A new configuration of high Q distributed inductor is devised and embedded in CMOS transistor source to enhance stability, maximum stable gain and bandwidth of mm-wave CMOS PAs. The source inductance selection is conveniently investigated by the proposed admittance matrix condensation. In power splitting and combining part, a novel X-shape pattern-ground shielding is inserted in high turn ratio transformer to ameliorate wideband matching. Based on these techniques, a fully differential mm-wave PA was implemented in 65 nm low-power CMOS with 0.25 mm2 core area. The measurement results show that its differential drive gain and common mode rejection ratio are above 10 and 26 dB, respectively, in a wide frequency range of 41 to 61 GHz, while the power added efficiency (PAE) is still above 10.8% at 46–62 GHz. This CMOS PA also achieves 11.9 dBm output referred 1-dB compression point (P 1 dB) and 15.2 dBm saturated power (P sat) with 12.4% peak PAE.