Silicon-based electronic-photonic integrated circuit (ePIC) technology enables a high degree of integration of optoelectronic sub-systems for optical communications. There are basically two approaches for merging photonics with electronics, hybrid assembly or monolithic integration. In hybrid integration approaches, electronic-only chips are combined with photonic-only chips after their separate fabrication [1]. Advantage is here that a mutual interference of photonic and electronic device fabrication can easily be avoided which is a more difficult task for most monolithic integration approaches. On the other hand, monolithic integration of photonic devices such as detectors and modulators in the frontend-of-line (FEOL) of a Si-based integrated circuit technology allows for shortest possible interconnects between photonics and electronics from which high-speed performance of electronic-photonic integrated circuits can greatly benefit. Moreover, monolithic electronic-photonic integration leads to shrinking form-factors and reduced assembly. Monolithic integration of Si photonics has been pursued for some time, chiefly on base of CMOS technologies [2, 3]. Looking beyond 100G systems, baud-rates exceeding 50GBd are needed for 400G transceivers, requiring very fast driving electronics. High-speed transistors are therefore a prerequisite for high-performance ePIC technology. Already today, SiGe bipolar or BiCMOS technologies are frequently deployed for broadband applications in high-speed discrete photonics. A key device figure of merit is the product of transit frequency and breakdown voltage (fT × BV) in which state-of-the-art SiGe heterojunction bipolar transistors (HBTs) outperform scaled MOS transistors. In result, SiGe HBTs are often preferred over CMOS for high-speed analog circuits. Although waveguide-based optics leads to lower form-factors compared to discrete solutions, there are limits to downsizing of integrated photonic devices because of the wavelength of light and the available index contrast. This puts constraints on the reduction of voltage swing required to drive photonic devices such as modulators. In practice, the required voltage swing remains comparable to discrete solutions. On the other hand, complex real-time mixed signal systems requiring large digital cores are typically implemented in highly scaled CMOS technologies that provide only a limited output voltage swing. Integrating Si photonics with SiGe HBT technology is therefore an excellent match for high-speed A/D or D/A interfaces. SiGe-HBT-based ePIC technology enables direct driving of integrated photonic devices by high-speed digital electronics such as advanced signal processing. Here, we will give an overview about IHP’s work in ePIC technology development under use of different SiGe BiCMOS baseline processes. Main focus is on “Photonic BiCMOS”, a new monolithic ePIC technology which combines high-performance BiCMOS technology with high-speed photonic devices for electronic-photonic sub-modules for next generation communication networks. We will describe the main features of this technology, including an overview of offered photonic and electronic devices. Examples of demonstrator circuits fabricated in a first generation of the new technology, comprising 200GHz SiGe HBTs and 30GHz Ge photodiodes, are also presented. Among these circuits are a 40Gbps monolithically integrated linear receiver [4] and a monolithically integrated segmented driver and Mach-Zehnder modulator with 13 dB extinction ratio at 28 Gbps [5]. We will also present our work to integrate a new Ge photodiode with 70GHz bandwidth and to improve the bipolar transistor performance to enable the fabrication of integrated receivers and transmitters with strongly increased optical line rates [6, 7]. In a second part of the talk we will demonstrate the potential of SiGe BiCMOS as the ‘electronics supplier’ for the hybrid integration approach, using IHP’s 0.13µm BiCMOS process SG13S offering HBTs with 240/320GHz fT/fmax. [1] F. Boeuf et al., “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s Applications,” in 2013 IEEE International Electron Devices Meeting (IEDM), pp. 353-356 [2] S. Assefa et al., “A 90nm CMOS integrated nano-photonics technology for 25Gbps WDM optical communications applications,” in 2012 IEEE International Electron Devices Meeting (IEDM), pp. 809-811 [3] R. Meade et al., “Integration of silicon photonics in bulk CMOS,” 2014 Symposium on VLSI Technology Digest of Technical Papers, DOI:10.1109/VLSIT.2014.6894427 [4] A. Awny et al., “A 40Gb/s monolithically integrated linear photonic receiver in a 0.25μm BiCMOS SiGe:C Technology,” IEEE Microwave and Wireless Components Letters, 25 (2015), 7, 469-471 [5] P. Rito et al., “A Monolithically Integrated Segmented Driver and Modulator in 0.25 μm SiGe:C BiCMOS with 13 dB Extinction Ratio at 28 Gb/s,” in press [6] D. Knoll et al., “High-performance photonic BiCMOS Process for the fabrication of high-bandwidth electronic-photonic integrated circuits,” in 2015 IEEE International Electron Devices Meeting (IEDM), pp. 402-405 [7] S. Lischke et al., “Photonic BiCMOS technology – Enabler for Si-based, monolithically integrated transceivers towards 400 G,” in press
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Open Access
Jan 1, 2017
Irina Semykina + 3
