Integration Of Microelectromechanical Systems Research Articles

Interactive Design of MEMS Varactors With High Accuracy and Application in an Ultralow Noise MEMS-Based RF VCO

The monolithic integration of microelectromechanical systems (MEMS) varactors into the backend of line metal stack of a state of the art semiconductor process is an attractive alternative to the field effect transistor or bipolar transistor varactors for continuous frequency tuning of ultralow phase noise voltage-controlled oscillators (VCOs). An efficient design of MEMS varactors according to application-specific demands requires a deep insight into the electromechanical and electromagnetic (EM) device properties and an accurate prediction of the varactor phase noise contribution to the overall phase noise of the MEMS-based VCO. Generally, MEMS varactors are designed using a combination of finite-element method and EM softwares. Due to the large computational and time effort, the required deep insight into the MEMS device is hard to achieve. This paper presents interactive design methodologies to predict the electromechanical, EM, and the phase noise properties of a MEMS varactor with high accuracy. These methodologies are verified by fabricated MEMS varactors and an experimental MEMS-based VCO with continuous frequency tuning.

(Invited) How to Integrate MEMS on Foundry-Fabricated CMOS Backplanes

A large variety of new applications for Internet of Things (IoT), Industrie 4.0 and other consumer products are pushing volume and manufacturing of microelectromechanical systems (MEMS) into a new phase. Due to massive use of these sensors and actuators in mobile and industrial applications smaller systems combined with low power consumption and higher versatility are required. MEMS are transducers that sense or control physical, chemical or optical quantities creating devices for applications in the area of 3D-motion tracking, pressure sensing, light shaping or detection of irradiation. The combination of MEMS with an application specific integrated circuit (ASIC) based on CMOS technology enables the entire system to interact with outside world. These ASICs are providing required features such as analog-to-digital conversion, amplification, filtering, information processing and storage as well as communication to the outside world. There are different solutions available to combine MEMS with customized CMOS circuits. One choice known as system-in-package (SiP) is the manufacturing of MEMS and CMOS on separate wafers and its subsequent integration in a multi-chip module using interposer/ rewiring technologies. Key advatanges of this technique are high flexibility, high modularity and a complete decoupled manufacturing of CMOS and MEMS. This enables a rapid development and leads to low development costs. And, there is no impact of different sizes between CMOS and MEMS chip. In order to enhance the integration density, to drive system feature size down, to suppress potential parasitic capacitances and to reduce power consumption an integrated manufacturing on the same substrate is a must and known as system-on-chip (SoC) solution. On one hand this approach can be still realized by a multi-wafer processing and a final integration using bonding technologies. This technology is often named as heterogeneous integration. Key advantage of multi-wafer technology is the possibility to use high-performance MEMS materials such as monocrystalline silicon as actuation/sensing material and its integration on CMOS wafers. Disadvantages are the required alignment accuracies when using a metallic bond or limitation for integration densities when using via-last approach. A more consistent way is a complete monolithic integration of MEMS on CMOS substrates. Especially when large transducer arrays are required (e.g. bolometers, micro-mirror arrays, CMUT arrays) a monolithic integration of MEMS on CMOS is the best solution. All advantages are now on hand – high integration densities, low parasitic capacitances and an effective usage of CMOS area. Fraunhofer IPMS applies surface and bulk micromachining technologies for the integration of MEMS on customized CMOS backplanes. To reduce development costs and time-to-market IPMS combines standard CMOS processes offered from CMOS foundries with a subsequent integration of MEMS part in our MEMS fab. Due to the application specific design of the CMOS backplane this concept allows a perfect match between ASIC and MEMS functionalities. In a typical project flow CMOS and MEMS will be manufactured and tested in parallel to shorten development time. After ASIC design is finished it will be tested using Multi- Project- Wafer run (MPW) in a CMOS foundry. Using these MPW runs a complete characterization of CMOS functionality can be realized in an early project state at low costs. Parallel to CMOS testing an entire process development of MEMS part can be done on passive devices in our MEMS fab. If CMOS and MEMS characterization is completed the MEMS part will be monolithically integrated on these customized CMOS backplanes. But there are still some challenges for the integration of MEMS on foundry fabricated CMOS backplanes, e.g.: Modifications of last CMOS/ interconnect/ ILD layers to realize an appropriate interface to MEMS Clarification of PCM (process control monitoring) test environment, depth of test structures and possible arising contamination issues In-chip surface topology after interconnect processing to define necessary actions to achieve required planarity for further processing Tuning mix-and-match lithography to achieve high overlay accuracies (Picture 1: Reached overlay accuracy between last 0,18µm CMOS and first MEMS layer of about 30- 40nm after correction step using i-line stepper) Required chip design features when using sacrificial layer technology IPMS offers a wide range of surface and bulk micromachining technologies which are particularly suitable for the fabrication of sensors and actuators on pre-fabricated CMOS wafers using monolithic integration. Especially surface micromachining using inorganic sacrificial layer technology allows the realization of rather complex MEMS structures on CMOS backplanes. Based on examples such as spatial light modulators (SLM) and capacitive micromachined ultrasonic transducers (CMUT) we will present solutions for the integration of surface micromachined MEMS on customized CMOS substrates. Figure 1

Inertial Impaction on MEMS Balance Chips for Real-Time Air Quality Monitoring

This paper reports on integration of microelectromechanical systems (MEMS) balance chips with aerosol inertial impactors for real-time monitoring of airborne particulate matter. Cascade inertial impactors have been extensively used for sampling and size separation of micro to nano-size airborne particles since they were first used in 1945. To introduce the real-time measurement capability to such tools, herein, MEMS resonator chips are employed as their impaction substrates. Dual-plate thermal-piezoresistive resonators (TPRs), that are shown to operate as promising mass balances, are integrated within a two-stage custom made aerosol impactor capable of size segregating particles down to a few tens of nanometers. Unlike cantilever-based microbalances or resonators operating in their bulk mode, TPRs provide uniform mass sensitivity over a big portion of their surface area. Upon deposition of airborne particles on the resonant sensors, the mass loading on each sensor and as a result the mass concentrations of size-segregated particles is measured in real-time. The air quality of different environments, including a class 10,000 cleanroom, was analyzed and monitored via the real-time impactor over a four day period. Comparison of the results with those of an optical particle counter demonstrates a clear correlation between the system response and the expected particle counts. Compared to existing optical particle counters, the proposed system offers the added advantage of detecting sub-100nm particles.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

Thermal Stresses of TSVs With Silicon Post Conductors and Polymer Insulators

Due to the advantages of ease of fabrication, low cost, and potential high reliability, through-silicon-vias (TSVs) using low-resistivity silicon posts as conductors and circular polymer liners as insulators have been developed for 3-D integration of microelectromechanical systems and microsensors. However, the large coefficients of thermal expansion (CTEs) of polymers lead to significant thermal stresses, which may cause silicon cracks. This paper reports the fabrication, thermal stress simulation, and thermal tests of a silicon TSV using benzocyclobutene (BCB) as the insulator. Silicon TSVs with high-aspect-ratio BCB liners have been fabricated by developing a vacuum-assisted filling method to achieve void-free BCB insulators. Finite-element method (FEM) is employed to simulate the thermal stresses caused by the mismatch in the CTE between silicon and BCB. High-temperature curing experiments show that crack in silicon substrates and silicon posts occurs on TSVs with specific dimensions. By correlating the results of FEM simulations and crack tests, the critical stress that causes silicon cracks is revealed, and design guidelines are proposed to achieve crack-free silicon TSVs.

A novel piezoresistive polymer nanocomposite MEMS accelerometer

A novel polymer MEMS (micro electro mechanical systems) accelerometer with photo-patternable polymer nanocomposite as a piezoresistor is presented in this work. Polymer MEMS Accelerometer with beam thicknesses of 3.3 µm and embedded nanocomposite piezoresistive layer having a gauge factor of 90 were fabricated. The photosensitive nanocomposite samples were prepared and characterized for analyzing the mechanical and electrical properties and thereby ensuring proper process parameters for incorporating the piezoresistive layer into the polymer MEMS accelerometer. The microfabrication process flow and unit processes followed are extremely low cost with process temperatures below 100 °C. This also opens up a new possibility for easy integration of such polymer MEMS with CMOS (complementary metal oxide semiconductor) devices and circuits. The fabricated devices were characterized using laser Doppler vibrometer (LDV) and the devices exhibited a resonant frequency of 10.8 kHz and a response sensitivity of 280 nm g−1 at resonance. The main focus of this paper is on the SU-8/CB nanocomposite piezoresistive MEMS accelerometer technology development which covers the material and the fabrication aspects of these devices. CoventorWare FEA analysis performed using the extracted material properties from the experimental characterization which are in close agreement to performance parameters of the fabricated devices is also discussed. The simulated piezoresistive polymer MEMS devices showed an acceleration sensitivity of 126 nm g−1 and 82 ppm of ΔR/R per 1 g of acceleration.

Wafer-Level Vacuum Packaging by Thermocompression Bonding Using Silver after Fly-Cut Planarization

With the development of micro-electromechanical systems (MEMS), the integration of MEMS and large scale integrated (LSI) circuits together with hermetic packaging is getting more important for the reduction of device footprint and the improvement of performance. Wafer bonding technology is a good choice for such integration because it allows separate design and fabrication of MEMS and LSI. As a kind of wafer bonding, thermocompression bonding can realize electric interconnection as well as hermetic sealing with a smaller bond frame and still keeps sufficient bonding strength. The thermocompression bonding based on metals, Au, Al and Cu is well known. However, Cu needs pretreatments for oxide removal; Al requires high temperature and pressure which may cause damage to temperature–sensitive devices such as LSI. Au can be bonded at lower temperature with minimal surface pretreatments. However, thermocompression bonding using thin Au film cannot achieve vacuum sealing for micro-structured or non-flat wafers such as MEMS. Our previous work solved most of these problems using electroplated Au bonding frames after fly-cut planarization. However, for lower cost, Ag is proposed which is much cheaper and shows superior thermal and electrical conductivity. Whereas, the oxidation affinity of Ag may cause bonding problems related to a surface oxide layer. The diffusion of Ag into Si is also concerned for deteriorating device characteristics. In this study, we developed a novel inexpensive hermetic thermocompression bonding method using electroplated Ag bonding frames planarized by fly cutting. A barrier layer was used to block the Ag diffusion into a Si substrate during the bonding process. Extremely high shear strength and vacuum sealing were demonstrated at relatively low bonding temperature and bonding pressure. Usually minority carrier lifetime in LSI would be severely reduced due to the contamination of metal atoms. In order to avoid the diffusion of Ag atoms from the bonding areas into a Si substrate during the bonding process, a titanium nitride (TiN) barrier layer was adopted because of its excellent barrier property in conjunction with good thermal stability and low contact resistance. A layered structure (20nm Ti/ 100nm TiN/ 20nmTi/ 100nmAg) was deposited on Si substrate by sputtering at room temperature. This test sample was heated up to the bonding temperature, held for 1 h. Secondary ion mass spectroscopy (SIMS) was carried out through stacked layers. No detectable Ag atom concentration was found in the Si substrate (Fig 1), suggesting that the diffusion was stopped by TiN. Next, we verified the possibility of Ag for thermocompression bonding. A Si substrate was coated with the stacked layer mentioned above. Then the Ag frames of 39μm width and 10μm height were electroplated using photoresist mold. On one substrate, 64 dies were fabricated. Subsequently the bump frames were cut to 4.3μm in height by fly cutting with a diamond bit. The planarization step played a decisive role in our method. Generally the electroplated surface was rough. However after planarization, even on non-flat wafers, Ag bonding frame surface became smooth to establish enough contact surface for sufficient atom diffusion. Additionally under the shear strain of the diamond bit, small grain size was obtained which improved grain boundary diffusion. Moreover, native surface oxide or any other surface contamination was removed. The substrate with the planarized electroplated Ag frames and another Si substrate with sputter deposited Ag thin film pads were treated by Ar plasma and bonded in vacuum at 350~400℃ with a loading pressure of 54MPa. After the bonded wafer was diced into dies, die-shear tests were conducted to evaluate the shear strength. The achieved mean shear strength was up to 200 MPa. The samples fractured across the bonding material and in no case at the bonding interface. The lateral expansion of bonding frames due to pressure was less than 5%. From the cross-sectional scanning electron microscopy (SEM) of the bonded area, there was no visible bonding interface anymore (Fig 2). This suggested the newly formed oxide after planarization didn’t affect the bonding significantly. The thin oxide layer probably diffused into the bulk through grain boundaries. Additionally, vacuum sealing was successfully demonstrated by the deflection of Si thin diaphragms fabricated through an SOI wafer due to pressure difference across the diaphragms. After bonding process, the membrane’s clear deflection was observed at atmosphere and confirmed by topography measurement system (Fig 3). The proposed process using the planarized electroplated Ag frames was useful for both wafer-level heterogeneous integration and hermetic packaging and versatile for various microsystems. Figure 1

Monolithically Integrated Microelectromechanical Systems for On-Chip Strain Engineering of Quantum Dots.

Elastic strain fields based on single crystal piezoelectric elements represent an effective way for engineering the quantum dot (QD) emission with unrivaled precision and technological relevance. However, pioneering researches in this direction were mainly based on bulk piezoelectric substrates, which prevent the development of chip-scale devices. Here, we present a monolithically integrated Microelectromechanical systems (MEMS) device with great potential for on-chip quantum photonic applications. High-quality epitaxial PMN-PT thin films have been grown on SrTiO3 buffered Si and show excellent piezoelectric responses. Dense arrays of MEMS with small footprints are then fabricated based on these films, forming an on-chip strain tuning platform. After transferring the QD-containing nanomembranes onto these MEMS, the nonclassical emissions (e.g., single photons) from single QDs can be engineered by the strain fields. We envision that the strain tunable QD sources on the individually addressable and monolithically integrated MEMS pave the way toward complex quantum photonic applications on chip.

Stacked Integration of MEMS on LSI.

Two stacked integration methods have been developed to enable advanced microsystems of microelectromechanical systems (MEMS) on large scale integration (LSI). One is a wafer level transfer of MEMS fabricated on a carrier wafer to a LSI wafer. The other is the use of electrical interconnections using through-Si vias from the structure of a MEMS wafer on a LSI wafer. The wafer level transfer methods are categorized to film transfer, device transfer connectivity last, and immediate connectivity at device transfer. Applications of these transfer methods are film bulk acoustic resonator (FBAR) on LSI, lead zirconate titanate (Pb(Zr,Ti)O3) (PZT) MEMS switch on LSI, and surface acoustic wave (SAW) resonators on LSI using respective methods. A selective transfer process was developed for multiple SAW filters on LSI. Tactile sensors and active matrix electron emitters for massive parallel electron beam lithography were developed using the through-Si vias.

3-D Integration of MEMS and CMOS Using Electroless Plated Nickel Through-MEMS-Vias

Three-dimensional integration of microelectromechanical systems (MEMS) and CMOS is able to achieve hetero-integrated microsystems with high performance, small size, low cost, and multiple functions. This paper reports a 3-D integration method using wafer transfer technology and electroless Ni plating with a noncontact induction (ENPNI) technique. Wafer transfer technology based on adhesive bonding and wafer thinning allows stacked integration of MEMS on top of CMOS. To address the challenge in fabricating through-MEMS-vias (TMVs) with small diameters, ENPNI has been developed to fabricate Ni TMVs as both the mechanical supports for suspended MEMS and the electrical connects between MEMS and CMOS. High-density MEMS arrays and CMOS circuits are integrated to demonstrate the feasibility of the 3-D integration method, and thermal cycling and mechanical vibration are performed to evaluate the reliability. Experimental results show that the 3-D integration processes do not exert distinct influences on MEMS arrays and CMOS circuits, and the integrated systems have good yield, uniformity, and reliability. The capability of ENPNI in the fabrication of small TMVs enables 3-D integration of high-density MEMS arrays and CMOS circuits, such as micromirror arrays, infrared focal planes, acoustic sensor arrays, radiation sensor arrays, and so on.

A flexible Li-ion battery with design towards electrodes electrical insulation

The application of micro electromechanical systems (MEMS) technology in several consumer electronics leads to the development of micro/nano power sources with high power and MEMS integration possibility. This work presents the fabrication of a flexible solid-state Li-ion battery (LIB) (~2.1 μm thick) with a design towards electrodes electrical insulation, using conventional, low cost and compatible MEMS fabrication processes. Kapton® substrate provides flexibility to the battery. E-beam deposited 300 nm thick Ge anode was coupled with LiCoO2/LiPON (cathode/solid-state electrolyte) in a battery system. LiCoO2 and LiPON films were deposited by RF-sputtering with a power source of 120 W and 100 W, respectively. LiCoO2 film was annealed at 400 °C after deposition. The new design includes Si3N4 and LiPO thin-films, providing electrode electrical insulation and a battery chemical stability safeguard, respectively. Microstructure and battery performance were investigated by scanning electron microscopy, electric resistivity and electrochemical measurements (open circuit potential, charge/discharge cycles and electrochemical impedance spectroscopy). A rechargeable thin-film and lightweight flexible LIB using MEMS processing compatible materials and techniques is reported.

Direct Wafer Bonding of SiC-SiC by SAB for Monolithic Integration of SiC MEMS and Electronics

Although the monolithic integration of silicon carbide (SiC) Micro-Electro-Mechanical Systems (MEMS) and SiC electronics is very promising, it is still very challenging due to the absence of suitable bulk machining technology of SiC. In this research, wafer bonding was proposed to assist the monolithic integration of SiC MEMS and SiC electronics by the formation of a suspended epitaxial SiC membrane. However, currently, SiC-SiC wafer bonding is still very difficult, especially for its direct wafer bonding. Surface activated bonding (SAB) method was applied to realize the direct wafer bonding of SiC-SiC at room temperature. The bonding energy of ∼1.4 J/m2 was obtained without orientation dependence. Correspondingly, the tensile strength of bonding interface is ∼12.2 MPa and could be improved by rapid thermal annealing to the values higher than 21.6 MPa. The bonding mechanisms were investigated through Monte Carlo simulation, interface analysis by transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDX), and in-situ analysis on the activated SiC surfaces by X-ray photoelectron spectroscopy (XPS).

(Keynote) Heterogeneous Integration of MEMS by Adhesive Bonding

Technology called microsystems or MEMS (micro electro mechanical systems) has been developed and applied as value added devices for systems. It is based on semiconductor microfabrication integrating not only circuits but also sensors, actuators and microstructures. MEMS as switches and filters fabricated on CMOS LSI are needed for future multi-band wireless systems, in which good mechanical properties or piezoelectric materials are required for the MEMS and state of the art for the LSI. Such heterogeneous integration can be performed by transferring MEMS devices fabricated on a carrier wafer to a LSI wafer by adhesive bonding (Figure). Wafer level selective transfer from one carrier wafer to multiple target wafers are needed for cost-effective integration of different size chips. The selective transfer technology was applied to multiple SAW (surface acoustic wave) resonators on LSI and tunable SAW filter having variable ferroelectric capacitor. Distributed tactile sensors are needed on the skin of robots to ensure their safety in nursing care robots. A tactile sensor network acquires sensing data from each tactile sensor element by autonomous data transmission (event driven). Capacitive tactile force sensors were formed on a communication LSI by adhesive bonding. An electron emitter array integrated with a 100×100 active-matrix driving LSI has been developed using the adhesive bonding. Massive parallel EB (electron beam) exposure systems for maskless lithography (digital fabrication of LSI) are under development. A nc (nanocrystalline)-Si emitter consists of cascaded tunnel junctions can be controlled at low voltage (10V). Resist patterning by the emitted electron was successfully confirmed. Amperometric biosensor in which 20×20 boron doped diamond electrode array are formed on LSI using the adhesive bonding. Distribution of chemicals like neurotransmitter can be detected owing to a wide potential window of the diamond electrode. Cost effective development is required for micro systems because they are versatile and not standardized. A hands-on access fabrication facility in our University is reuse of a production line for power transistor and donated equipments. Companies can easily access and utilize for their prototyping or small-volume production. It is equipped with 4 and 6 inch facilities. The users are charged depending on their amount of usage. They can access a lot of technology and know-how accumulated and can be assisted by skilled engineers. More than 150 companies are using this facility and it is allowed to sell produced small volume devices. Figure 1

Integrating MEMS and ICs

The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than-Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed. Combining micrometer-sized movable components and electronic devices adds functionality to integrated circuits. Microelectromechanical systems (MEMS) are flexible transducers that can measure acceleration or the presence of chemicals, to give just two examples. Andreas C. Fischer and colleagues from the KTH Royal Institute of Technology in Sweden review both traditional and emerging approaches forplacing MEMS on the same platform as the electronics needed to process the electrical signals they produce, thus producing smaller and cheaper components. Such approaches include creating the MEMS and electronics on separate substrates and then combining them, or developing fabrication processes that are able to define both types of device on the same substrate. The researchers conclude that the most cost-effective solution depends on the specific application.

Investigation of fused silica glass etching using C4F8/Ar inductively coupled plasmas for through glass via (TGV) applications

Through glass via (TGV) technology is considered to be a cost effective enabler for the integration of micro electromechanical systems and radio frequency devices. Inductively coupled plasma and Bosch etching process comprise one of the most pervasive methods for through silicon via (TSV) formation. Unfortunately an equivalent process for glass etching remains elusive. In this paper, the influence of plasma etching for fused silica glass were investigated to find the best tradeoff between etch rate and profile of TGVs. The process parameters including bias power, gas flow rate, ratio of etching gases and reaction chamber pressure using Ar/C4F8 inductively coupled plasmas were studied. The etching results show that all these three parameters have a significant impact on the etch rate. Furthermore, the adjustment including total flow rate and ratio of Ar/C4F8 and chamber pressure can be used to control the via profile. Constant fused silica glass etch rate greater than 1 μm/min was obtained when chiller temperature was 40 °C with etching time of 60 min. The profile angle of TGVs with nearly 90° was also achieved.

Deep submicron parallel scanning probe lithography using two‐degree‐of‐freedom microelectromechanical systems actuators with integrated nanotips

A new enabling technology for low-cost high throughput parallel scanning probe nanolithography is presented. Monolithic integration of microelectromechanical systems (MEMS) actuators with two-dimensional probe arrays as well as preliminary results in the simultaneous generation of multiple submicron patterns using such structures is reported. Two-degree-of-freedom electrothermal MEMS positioning structures integrated with nanoscale probe-tips are used to perform parallel scanning probe nanolithography circumventing the main deficiency of tip-based nanolithography, that is, low throughput. Simultaneous generation of multiple patterns scratched into 800 nm thick photoresist and 200 nm thick gold layers has been successfully demonstrated. Scratch marks as narrow and as long as ∼50 and 27 µm, respectively, have been generated in the X and Y directions using two different microactuator structures carrying 10 and 64 nanotips.

Research on design and firing performance of Si-based detonator

For the chip integration of MEMS (micro-electromechanical system) safety and arming device, a miniature detonator needs to be developed to reduce the weight and volume of explosive train. A Si-based micro-detonator is designed and fabricated, which meets the requirement of MEMS safety and arming device. The firing sensitivity of micro-detonator is tested according to GJB/z377A-94 sensitivity test methods: Langlie. The function time of micro-detonator is measured using wire probe and photoelectric transducer. The result shows the average firing voltage is 6.4 V when the discharge capacitance of firing electro-circuit is 33 μF. And the average function time is 5.48 μs. The firing energy actually utilized by Si-based micro-detonator is explored.

Cavity‐first approach for microelectromechanical system–CMOS monolithic integration

Presented is a cavity-first approach for producing released microelectromechanical system (MEMS) structures from the front side of a silicon on insulator (SOI) wafer. This approach shows excellent process compatibilities to CMOS and is significantly valuable to MEMS–CMOS monolithic integration. In this approach, prior to metal layer deposition and other components fabrication, which are easily damaged by vapour-phase hydrofluoric (HF) acid, release holes with a diameter of a few micrometres were created in the active silicon layer, and the cavities were formed after removing the underneath SiO2 box layer by vapour-phase HF etching. An amorphous fluoropolymer thin film was then successfully introduced to refill those release holes without entering into the cavities, after which the wafer can be fabricated by standard process with negligible surface fluctuation. Finally, MEMS structures were released from the front side of the wafer by inductively coupled plasma reactive ion etching (ICP-RIE). This approach enables monolithic integration of MEMS with CMOS circuits on SOI wafers with easy-package capability, eliminates the requirements on device release by wet chemical etching or ICP-RIE from the backside of the wafer and reduces the risk of device damage by vapour-phase HF etching. This approach also excels others in simplicity and high yields with better thickness uniformity and less residual stress in a MEMS structure.

(Invited) MEMS and Photonics Module Integration into SiGe BiCMOS Technology for More than Moore Functional Diversification

The “More Than Moore” approach is targeting on diversification by combining different technologies based on a reasonable scaling level. Here, SiGe BiCMOS technology acts as the baseline process for the integration of modules increasing the functionality and by this way enlarging the spectrum for embedded system applications. In this paper we focus on the monolithic integration approach of MEMS (micro-electro-mechanical systems) into the back-end-of-line (BEOL) of the Si process, and of optical components to combine electronics and photonics (Si Photonics).

A Post-Complementary Metal Oxide Semiconductor Formation Process of High-Adhesiveness SU-8 Structures for Reliable Fabrication of Integrated Microelectromechanical System Sensors

In this study, a post CMOS reliable formation process for high-aspect-ratio SU-8 structures on integrated circuits is newly proposed. Enhancement of SU-8 adhesiveness is realized by forming a thin SU-8 layer (called an adhesive layer) over the surface of the circuit before the SU-8 structures are formed. Improvement of adhesion of thick SU-8 structures is very important to guaranty the reliability of MEMS microsensors. The negative effect of the adhesive SU-8 layer on the mechanical properties of silicon movable structures has been estimated and discussed with simple analytical formulae. Also, the effect of the adhesive layer on the silicon substrate has been demonstrated with test structure patterns. On the basis of the developed technique, a tactile sensor device has been successfully fabricated as an example of the application of this technique.