Integrated Circuit Fabrication Process Research Articles

Theoretical Understanding of Electromigration-Related Surface Diffusion and Current-Induced Force in Ag-Pd Systems.

Electromigration, as a common reason for interconnect failure, is becoming increasingly important in the ongoing decrease in the integrated circuit manufacturing process. A study is being carried out utilizing the ab initio calculational method to gain a deeper understanding of electromigration, with a focus on the atom diffusion process in the Ag-Pd alloy system, a commonly used interconnect material. We begin by establishing that the primary mechanism of diffusion is step-edge diffusion on the (111) surface. Following this, we examine the current-induced force exerted on the migrating Ag atom. The Pd substitutional defect reveals an effect that increases the energy barrier of diffusion and decreases the current-induced force that powers the directional migration.

DeepSEM-Net: Enhancing SEM defect analysis in semiconductor manufacturing with a dual-branch CNN-Transformer architecture

Due to the increasing complexity of modern semiconductor integrated circuit fabrication processes, various defects may occur at each process step, leading to a semiconductor integrated circuit yield loss as well as reliability problems. This study introduces DeepSEM-Net, a novel dual-branch architecture that harmoniously integrates Convolutional Neural Networks (CNN) with Transformers. This innovative approach significantly enhances defect classification and precise segmentation in Scanning Electron Microscope (SEM) defect images, crucial for semiconductor manufacturing processes. DeepSEM-Net consists of a classification branch, which synergizes CNN and Transformers for robust global feature extraction, and a segmentation branch, which incorporates a Pyramid Attention module to meticulously recalibrate and exploit the feature map, thereby enriching the segmentation quality. A semi-supervised defect analysis system based on this model markedly reduces manual inspection efforts and is adept at operating in both simultaneous and sequential classification-segmentation modes. Rigorously tested on a diverse dataset from a real 12-inch wafer fab, DeepSEM-Net not only demonstrated a commendable classification accuracy of 97.25% on a 5-class dataset and a segmentation IoU of 84.40% but also exhibited remarkable resilience against the introduction of new defect classes in an unbalanced dataset. The dual-branch strategy of DeepSEM-Net, thus, significantly elevates the efficiency and reliability of SEM defect image analysis, offering a substantial leap forward in addressing yield loss and ensuring the reliability of semiconductor products.

MAG-PUFs: Authenticating IoT devices via electromagnetic physical unclonable functions and deep learning

The challenge of authenticating Internet of Things (IoT) devices, particularly in low-cost deployments with constrained nodes that struggle with dynamic re-keying solutions, renders these devices susceptible to various attacks. This paper introduces a robust alternative mitigation strategy based on Physical-Layer Authentication (PLA), which leverages the intrinsic physical layer characteristics of IoT devices. These unique imperfections, stemming from the manufacturing process of IoT electronic integrated circuits (ICs), are difficult to replicate or falsify and vary with each function executed by the IoT device. We propose a novel lightweight authentication scheme, MAG-PUFs, that uses the unintentional Electromagnetic (EM) emissions from IoT devices as Physical Unclonable Functions (PUFs). MAG-PUFs operate by collecting these unintentional EM emissions during the execution of pre-defined reference functions by the IoT devices. The authentication is achieved by matching these emissions with profiles recorded at the time of enrollment, using state-of-the-art Deep Learning (DL) approaches such as Neural Networks (NN) and Autoencoders. Notably, MAG-PUFs offer compelling advantages: (i) it preserves privacy, as it does not require direct access to the IoT devices; and, (ii) it provides unique flexibility, permitting the selection of numerous and varied reference functions. We rigorously evaluated MAG-PUFs using 25 Arduino devices and a diverse set of 325 reference function classes. Employing a DL framework, we achieved a minimum authentication F1-Score of 0.99. Furthermore, the scheme’s efficacy in detecting impostor EM emissions was also affirmed, achieving a minimum F1-Score of 0.99. We also compared our solution to other solutions in the literature, showing its remarkable performance. Finally, we discussed code obfuscation techniques and the impact of Radio Frequency (RF) interference on the IoT authentication process.

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

A fine-grained detection method for gate-level hardware Trojan based on bidirectional Graph Neural Networks

Due to technical barriers and economic costs, malicious circuits, known as hardware Trojans, are easily implanted in the complicated integrated circuit design and manufacturing process, which can lead to many disastrous consequences, such as denial of service, information leakage, performance degradation, etc. Research on how to detecting hardware Trojans has grown into a significantly open issue over the past decade. While, for very large scale integrated circuits, numerous new challenges deserve our full attention, including golden-free chip reference, automatic feature engineering, hardware Trojan localization, and scalable framework. In response to the above challenges, a fine-grained gate-level hardware Trojan detection approach is proposed in this paper, named GateDet, from improving earlier circuit graph modeling to developing a detection framework based on Bidirectional Graph Convolution Networks with a timely information fusion strategy. GateDet achieves automatic feature circuit extraction and further overcomes the original neighborhood limitation of Bidirectional Graph Convolution Network. Moreover, for large-scale training, it comprehensively considers the problems of sample imbalance and boundary network, and develops a circuit directed graph sampling method based on GraphSAINT, which improves the training performance of the directed graph framework. From experiments, GateDet shows high scalability on 24 benchmarks of TrustHub. It could be used to learn about adaptive structural feature extraction for different Trojans simultaneously. Compared to the existing gate-level detections, the fine-grained results of GateDet are more accurate and can be used to track suspicious structures, reducing manual review.

Anti-crosstalk absolute phase retrieval method for microscopic fringe projection profilometry using temporal frequency-division multiplexing.

In microscopic fringe projection profilometry (MFPP), the traditional absolute phase retrieval method using composite frequency fringe has the shortcomings of low accuracy and poor robustness due to mutual crosstalk of harmonic from the different channels of frequency-division multiplexing. In this study, an absolute phase retrieval method that avoids the inter-channel crosstalk is proposed. By introducing guard bands to accommodate the frequency channels corresponding to the second harmonic that dominate the high order harmonics, the aliasing between the second harmonic and the fundamental is eliminated. Consequently, phase maps without crosstalk can be demodulated using appropriate phase-shifting algorithms. The proposed method is well-suited for high-precision three-dimensional shape measurement scenarios in many fields such as integrated circuit manufacturing process control and micro-electro-mechanical system quality inspection. The experiment results demonstrate that the anti-crosstalk method is effective and can realize three-dimensional reconstruction for discontinuous planar surface and spherical surface.

The role of ammonium citrate and dodecyl pyridinium chloride on chemical mechanical polishing relevant to SiO2 dielectric layer

Silicon dioxide films are widely utilized in integrated circuit manufacturing for their excellent properties, including applications in shallow trench isolation and interlayer dielectrics. Chemical mechanical polishing (CMP) has a pivotal part in achieving material planarization across integrated circuit manufacturing process. This study delves into the mechanisms of ammonium citrate and dodecyl pyridinium chloride in the CMP of silicon dioxide dielectric layers, alongside optimizing the concentration ratios of the slurry components. The incorporation of ammonium citrate effectively mitigates electrostatic repulsion between the abrasive and the wafer surface, thereby augmenting the mechanical interactions during polishing. The introduction of dodecyl pyridinium chloride further enhances material removal rates while concurrently reducing surface roughness. Notably, employing the slurry with the optimized composition ratios yields a notable reduction in surface defects after CMP. Extensive characterization techniques, including X-ray photoelectron spectroscopy and scanning electron microscope, were devoted to elucidate the mechanisms of the additives and assess the stability of the slurry. This study substantiates that the incorporation of ammonium citrate and dodecyl pyridinium chloride in the slurry not only sustains a high material removal rate but also achieves superior outcomes in terms of lower wafer surface roughness and diminished wafer surface defects.

Direct Application of Carbon Nanotubes (CNTs) Grown by Chemical Vapor Deposition (CVD) for Integrated Circuits (ICs) Interconnection: Challenges and Developments.

With the continuous shrinkage of integrated circuit (IC) dimensions, traditional copper interconnect technology is gradually unable to meet the requirements for performance improvement. Carbon nanotubes have gained widespread attention and research as a potential alternative to copper, due to their excellent electrical and mechanical properties. Among various methods for producing carbon nanotubes, chemical vapor deposition (CVD) has the advantages of mild reaction conditions, low cost, and simple reaction operations, making it the most promising approach to achieve compatibility with integrated circuit manufacturing processes. Combined with through silicon via (TSV), direct application of CVD-grown carbon nanotubes in IC interconnects can be achieved. In this article, based on the above background, we focus on discussing some of the main challenges and developments in the application of CVD-grown carbon nanotubes in IC interconnects, including low-temperature CVD, metallicity enrichment, and contact resistance.

Analysis and design of algorithms for the manufacturing process of integrated circuits

The stage of transporting semiconductor chips from the wafer to the support strip is crucial in the integrated circuit manufacturing process. This process can be modeled as a combinatorial optimization problem where the objective is to reduce the total distance the robotic arm must travel to pick up each chip and place it in its corresponding position within the support structure. This problem is of the pick-and-place type and is NPhard. The (approximate) solution proposals of state-of-the-art methods include rulebased approaches, genetic algorithms, and reinforcement learning. In the present work, one of these methods is analyzed, which models the problem as one of binary integer programming and proposes a genetic algorithm. Based on this analysis, we proposedand evaluated other methods, including a greedy algorithm and a genetic algorithm that improve the state-of-the-art results for test cases usually used in the literature. Additionally, the results obtained from a new ILP model for this problem indicate that the genetic algorithm results are very close to the optimal values.

Mechanical and optical properties of amorphous silicon nitride-based films prepared by electron cyclotron resonance plasma-enhanced chemical vapor deposition

Silicon nitride (SiNx) based films have been recognized as essential dielectric films in the microelectronics and optoelectronics industry due to their desirable properties, such as high electrical insulation, excellent thermal stability, and compatibility with integrated circuit fabrication processes. They are also a potential candidate for fabricating wavelength-selective reflective coatings and surface passivation layers in building-integrated photovoltaics technologies. SiNx-based films are one of the popular choices for antireflective coatings in photovoltaics as well. Recently, SiNx and oxynitride (SiOyNx) based thin film optical filters have been explored to provide distinct color rendering to solar-charged electrical vehicles. Since solar cells have a lifespan of many years and the coating surfaces are substantial, it is essential to produce films with controlled optical and mechanical properties and maintain mechanical integrity against corrosion and wear. This study aims to design a deposition process and optimize minimal parameters for stable plasma conditions during multilayer deposition of SiNx and SiOyNx films using an electron cyclotron resonance plasma-enhanced chemical vapor deposition reactor with SiH4/N2/O2/Ar precursor mixtures at 120 °C. The primary goal was to investigate the influence of gas flow adjustments on the optical and mechanical properties, specifically targeting the refractive index and mechanical properties of the films. We measured the refractive index and the absorption of the films using variable angle spectroscopic ellipsometry. Then, we evaluated the mechanical residual stress ex situ using the wafer curvature measurement method. We have determined the elastic modulus and the hardness of the films using nanoindentation. The experimental results have shown a significant dependence of the optical and mechanical properties on the deposition parameters. To investigate the factors contributing to the intrinsic mechanical stress and to better understand SiNx film degradation mechanisms, we have studied the effect of postdeposition thermal cycling on the properties of the films. Several thermal-cycling experiments from room temperature to 400 °C were performed on different SiNx films, and the results showed an irreversible variation of the mechanical stress toward the tensile stresses caused by delamination of the films, while the refractive index remained unchanged.

Effects of grinding-induced surface topography on the material removal mechanism of silicon chemical mechanical polishing

Ultra-precision thinning technology using workpiece self-rotational grinding followed by chemical mechanical polishing (CMP) is extensively applied in the integrated circuit manufacturing process, which enables to obtain large size ultra-thin silicon wafers with high material removal rate and low damage layer thickness. However, an in-depth understanding of the influence caused by ground surface topography on material removal mechanism in silicon CMP process has not been revealed yet. This work systematically investigates the contact characteristics of the wafer-pad interface and corrosion behaviors of the ground silicon wafer immersed in polishing solution. Firstly, some silicon wafers are ground using different wheels and subsequently polished. The material removal depth during the whole CMP process is measured. Then, the intrinsic model of polishing pad is determined via mechanical property tests. A finite element method is adopted to evaluate the contact status, displacement distortion and stress distribution at the contact region between pad and ground wafer surface. Moreover, the chemical reaction mechanism between ground silicon wafer and polishing solution is revealed by utilizing X-ray photoelectron spectroscopy and electrochemical analysis. The influence of wafer surface topography on corrosion resistance in CMP process is illustrated. Finally, corresponding experimental results are explained from an atomic scale by a ReaxFF reactive molecular dynamics simulation model. This presented study demonstrates the corrosion promotion principle of ground silicon wafer in CMP process.

Recent Progress and Applications of HfO2-Based Ferroelectric Memory

The discovery of ferroelectricity in hafnium oxide (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) based thin films in 2011 renewed the interest in ferroelectrics. These new ferroelectrics possess completely different crystal morphology with conventional perovskite ferroelectrics, and present more robust ferroelectric properties upon aggressive scaling and compatibility with standard integrated circuit fabrication processes. In this article, we give a brief introduction to the conventional ferroelectric memories, then review the basic properties, recent progress, and memory applications of these HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectrics.

ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment

The electronics supply chain has adapted into a global process over the past two decades to support the cost of process optimization. As the semiconductor industry has transitioned from a vertical to the horizontal business model, the perceived vulnerability of integrated circuit (IC) design, and fabrication has grown dramatically. Design intellectual property (IP) is the defining characteristic of most fabless design houses and integrated device manufacturers (IDMs) within the supply chain, and as such, holds significant value for market competitiveness, and in some cases, national security. Malicious insiders threaten the confidentiality of this proprietary technology. To prevent IP piracy, we redefine the modern threat landscape by considering nearly every individual in the IC design and fabrication process untrusted. Therefore, we propose a novel framework to assure confidential electronic design against insider threats, termed ACED-IT, that enables maintaining the confidentiality of the design when it traverses through different design stages (e.g., RTL/Gate-level to GDSII). ACED-IT integrates encryption, logic locking, novel temporary-inserted logic elements (TILEs), access controls, and action logging, to protect the design IP from insider threats originating from any entity in the process. ACED-IT is compatible with the current industry development flow and provides all engineers with the tools to complete their roles. The proposed ACED-IT framework is demonstrated across various benchmarks and analyzed for security. Benchmarks processed using ACED-IT incurred negligible overhead across parameters such as power, area, timing, and test coverage after functional recovery, and provided a brute force attack complexity to recover the original design exceeding that of AES-256.

Economic and embodied energy analysis of integrated circuit manufacturing processes

Integrated circuits (ICs) are the fundamental microelectronic building blocks of typical information and communication technology (ICT) devices such as laptops and smartphone. With the emergence of faster and cheaper low-power ICs for the growing ICT market, there is a limited information on their manufacturing energy and economic impacts owing to the lack of recurrent upgradation of proprietary IC manufacturing process data. Economic and life cycle energy assessments (LCAs) of IC manufacturing and assembly processes were conducted using the latest bill of materials (BOM) manufacturing data in a state-of-the-art IC manufacturing cost software tool developed by IC Knowledge, LLC. IC manufacturing cost was estimated to be $1.00-$5.00/cm2; the high-end cost represents the most advanced 3D NAND IC technology with the Wafer Level Chip Scale Package cost of $4/cm2. Total cumulative energy demand (CED) estimates of IC manufacturing using the OpenLCA software ranged from 9 to 38 MJ/cm2 or 56–235 BJ/month with the largest share (~ 75%) from on-site energy. The IC manufacturing CED is projected to increase with the progress in IC technology node, which has increased by more than two times for technology node evolution from 110 to 14 nm. Furthermore, the representative detailed BOM data were considered to reduce the CED uncertainties of the estimated standard deviation of 35%− 42%.

Integrated on-site collection and off-site analysis of airborne molecular contamination in cleanrooms for integrated circuit manufacturing processes

Both long-term on-site collection and off-site analysis methods were conducted to investigate airborne molecular contaminants (AMCs) in a semiconductor wafer cleanroom. The removal efficiency of SO2 and NO2 for chemical filters on a make-up air unit (MAU) in the cleanroom is approximately 50%, though this value does not meet the removal efficiency mentioned in the GB 36306 standard. The removal efficiencies of SO2, H2S, NO, NO2, NH3, and TVOC were approximately 76.5%, 50.9%, 83.5%, 99.3%, 94.8%, and 97.1% after the fan filter unit (FFU) was equipped with a chemical filter. AMCs mainly include benzene, toluene, ethylbenzene, xylene (BTEX), alkanes and alkenes, though BTEX accounts for 77% of the total. VOC concentrations in cleanrooms fitted with FFU chemical filters and where the process equipment was not in operation were found to be lower than those at domestic residences and slightly higher than those found in commercial aircraft cabin air. The daily average TVOC concentrations were negatively correlated with temperature (R2 = 0.46, p < 0.01) and positively correlated with humidity (R2 = 0.26, p < 0.01). The daily average NH3 concentrations were negatively correlated with T (R2 = 0.19, p < 0.05) and positively correlated with RH (R2 = 0.18, p < 0.01). Dibutyl phthalate (DBP) and dioctyl phthalate/diethylhexyl phthalate (DOP/DEHP) were detected in the new sealing joint strips in the HEPA filters. Phthalates and organophosphates were not detected in the new filter papers.

Non‐parametric local capability indices for industrial planar manufacts: An application to the etching phase in the microelectronic industry

AbstractProcess capability indices are routinely used to estimate the mean‐variability performance of industrial products with respect to both targets and specification limits. However, when the target variable is defined over a planar surface of a manufact, it is relevant to assess the capability of the production process locally, that is, at any spatial location of the surface, in particular if the manufact has to be split into pieces to obtain single production items. In this article, focusing on the specification introduced by Clements [Qual Prog., 22, 95–100], we suggest an approach based on additive quantile models to estimate, in a Bayesian paradigm, the index locally. We demonstrate its use in the context of the etching phase of the integrated circuit fabrication process. Since capability of etching processes is typically assessed for batches of wafers, we also propose two algorithms based on resampling to perform local capability analysis at the lot level.

Technology theme mining of integrated circuit manufacturing industry chain based on patents

Excavate and compare the technical themes of IC manufacturing industry chain of domestic and foreign patents, so as to objectively and comprehensively reveal the technical themes and differences of IC manufacturing in domestic and foreign, hoping to provide valuable reference for domestic IC manufacturing. Based on the integrated circuit manufacturing process, established the patent retrieval formula of each process and retrieved the patent data. Through TF-IDF algorithm and LDA model to mine the technical topics of domestic and foreign patents on the basis of self-built thesaurus and stop-words list, and summarized mining results. Through the analysis of results, it is found that the technical topics of integrated circuit manufacturing in domestic and foreign have similarities and differences, and the upper concept is strong, but the technical topics are more detailed of foreign patents.

An Alternative to Compound Semiconductors Using a Si-Based IR Detector

Though infrared (IR) photodetection is popular, it faces several problems. First, the main materials, compound semiconductors, require high temperature, low pressure, and high energy consumption facilities. Second, compound semiconductor elements are rare on earth. Third, compound semiconductors are difficult to integrate with Si-based integrated circuit (IC) manufacturing process. To overcome these problems, we utilized a Si-based Schottky junction and internal photoemission to break the detection limit of a Si photodetector. The spectral detection limit extends from 1100 nm, the bandgap wavelength of Si, to ca. 1600 nm, the Schottky barrier wavelength of the metal/Si junction. The Schottky junction is composed by Ag and n-type Si through simple thermal evaporation. The light incident direction, metal thickness, and device temperature were analyzed. As a result, under normal temperature and pressure, the Schottky barrier height of the Ag/Si junction is 0.742 eV. The detection limit is 1670 nm. If the 1550-nm laser is a detected light source illuminating from the metal film, the responsivity is 0.02122 mA/W. If the same detected light source illuminates from the Si substrate, the responsivity improves to 0.04567 mA/W due to the light absorption enhancement. Furthermore, if the metal thickness is increased to 100 nm, the responsivity increases to 1.242 mA/W, which is about 585.3% of the original value. In addition, the influence of the temperature on the electric properties of the devices indicates that a Ag/Si Schottky device could be a candidate for temperature detection.

Effects of COVID-19 on a CMOS fabrication course: An integrated design experience.

In the CMOS fabrication course described herein, the lecture component provides the theoretical background for semiconductor materials and integrated circuit fabrication processes. The laboratory component provides the hands‐on experience required to fabricate and electrically characterize CMOS circuits in a one‐semester format. A strong semiconductor device process design thread is achieved in the course by integrating the laboratory experience and process simulation/modeling and theoretical calculations. The risks associated with the COVID‐19 pandemic have forced significant course modifications. The lecture is switched to a remote learning format, including pre‐recorded content and weekly advanced Q&A sessions. The laboratory provides both in‐person and remote sessions. Approved social distancing and cleaning protocols are practiced in the facility for in‐person learning. Complementary remote learning resources are made available to all the students such as pre‐recorded laboratory instructions, live video‐based laboratory sessions, and web‐based supplementary information. Compared to pre‐pandemic semesters, the average students' GPA of the pandemic period has increased, attributed to larger and archived volumes of instructional material. Overall student comments related to course changes necessitated by the pandemic are mixed with both positive and negative feedback.

Physical Unclonable Function (PUF)-Based Sustainable Cybersecurity

The articles in this special issue focus on physical unclonable funtion (PUF)-based systainable cybersecurity. The articles investigate the potential use of physically unclonable functions (PUFs) as a hardware security approach for sustainable cybersecurity. PUFs are a class of circuits that use the inherent variations in the integrated circuit manufacturing process to create unique and unclonable IDs.1 PUF has the potential to seal multiple types of vulnerabilities for sustainable cybersecurity specifically in the security classes of authentication, nonrepudiation, and privacy.