Integrated Circuit Design Research Articles

Exceptional Absorption in a Deep‐Subwavelength Plasmonic Film

AbstractIn the realm of photonic integrated circuit design, on‐chip absorbers are imperative for preventing signal degradation caused by unintended stray photons, which induce signal crosstalk and operational errors. An ideal on‐chip optical absorber is expected to have a superior absorption capability across a wide range of frequencies while maintaining a minimal footprint. However, widely employed optical thin‐film absorbers suffer from limited absorption due to inherent refractive index mismatches and short light‐matter interaction lengths. Here a ≈45‐nm thin metalayer is demonstrated that exhibits uniformly high absorption over a broad wavelength range from 350 nm to 4.5 µm in a wide range of incident angles up to over 60 degrees. The metalayer's performance notably exceeds the absorption predicted by standard plane‐wave optics theories, potentially attributing to the Anderson localization effect. Integration of such a deep‐subwavelength metalayer absorber into photonic circuits will facilitate the creation of highly efficient photonic chips, propelling the advancement of optical communication and computing.

Meta-atoms: From Metamaterials to Metachips.

Electromagnetic (EM) metamaterials represent a cutting-edge field that achieves anomalously macroscopic properties through artificial design and arrangement of microstructure arrays to freely manipulate EM fields and waves in desired ways. The unit cell of a microstructure array is also called a meta-atom, which can construct effective medium parameters that do not exist in traditional materials or are difficult to realize with traditional technologies. By deep integration with digital information, the meta-atom is evolved to a digital meta-atom, leading to the emergence of information metamaterials. Information metamaterials break the inherent barriers between the EM and digital domains, providing a physical platform for controlling EM waves and modulating digital information simultaneously. The concepts of meta-atoms and metamaterials are also introduced to high-frequency integrated circuit designs to address issues that cannot be solved by traditional methods, since lumped-parameter models become unsustainable at microscopic scales. By incorporating several meta-atoms to form a metachip, precise manipulation of the EM field distribution can be achieved at microscopic scales. In this perspective, we summarize the physical connotations and main classifications of meta-atoms and briefly discuss their future development trends. Through this article, we hope to draw more research attention to explore the potential values of meta-atoms, thereby opening up a broader stage for the in-depth development of metamaterials.

A framework for hardware trojan detection based on contrastive learning

With the rapid development of the semiconductor industry, Hardware Trojans (HT) as a kind of malicious function that can be implanted at will in all processes of integrated circuit design, manufacturing, and deployment have become a great threat in the field of hardware security. Side-channel analysis is widely used in the detection of HT due to its high efficiency, non-contact nature, and accuracy. In this paper, we propose a framework for HT detection based on contrastive learning using power consumption information in unsupervised or weakly supervised scenarios. First, the framework augments the data, such as creatively using a one-dimensional discrete chaotic mapping to disturb the data to achieve data augmentation to improve the generalization capabilities of the model. Second, the model representation is learned by comparing the similarities and differences between samples, freeing it from the dependence on labels. Finally, the detection of HT is accomplished more efficiently by categorizing the side information during circuit operation through the backbone network. Experiments on data from nine different public HTs show that the proposed method exhibits better generalization capabilities using the same network model within a comparative learning framework. The model trained on the dataset of small Trojan T100 has a detection efficiency advantage of up to 44% in detecting large Trojans, while the model trained on the dataset of large Trojan T2100 has a detection efficiency advantage of up to 10% in detecting small Trojans. The results in data imbalanced and noisy environments also show that the contrastive learning framework in this paper can better fulfill the requirements of detecting unknown HT in unsupervised or weakly supervised scenarios.

A surface potential analysis method and I–V model of AlGaN/GaN high-electron mobility transistors incorporating the two lowest subbands

An analysis method for the surface potential model and current–voltage model of AlGaN/GaN high-electron mobility transistors (HEMTs) is proposed. In this paper, the two lowest subbands E0 and E1 in the triangular electron potential well are incorporated into this model, which can preferably reflect the electronic structure and carrier transport mechanism of HEMTs. Then, the proposed method of compound-proximity algorithm overcomes the bottleneck of the compromise between the accuracy and efficiency of GaN HEMTs’ physics-based model. Additionally, the self-heating effect is introduced into the current model, which can effectively reflect the degradation of output characteristics caused by the increase in the device temperature. The results of numerical simulations, experiments, and our model are compared across a wide range of operating regimes for HEMTs to demonstrate the validity of AlGaN/GaN HEMTs’ modeling. This modeling method offers a fresh research approach for AlGaN/GaN HEMT modeling and paves a novel path toward overcoming the technical hurdles in advanced process integrated circuit design associated with Electronic Design Automation tools.

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort

Hardware Trojans (HTs) are a longstanding threat to secure computation. Among different threat models, it is the fabrication-time insertion of additional malicious logic directly into the layout of integrated circuits (ICs) that constitutes the most versatile, yet challenging scenario, for both attackers and defenders.Here, we present a large-scale, first-of-its-kind community effort through red-versus-blue teaming that thoroughly explores this threat. Four independently competing blue teams of 23 IC designers in total had to analyze and fix vulnerabilities of representative IC layouts at the pre-silicon stage, whereas a red team of 3 experts in hardware security and IC design continuously pushed the boundaries of these defense efforts through different HTs and novel insertion techniques. Importantly, we find that, despite the blue teams’ commendable design efforts, even highly-optimized layouts retained at least some exploitable vulnerabilities.Our effort follows a real-world setting for a modern 7nm technology node and industrygrade tooling for IC design, all embedded into a fully-automated and extensible benchmarking framework. To ensure the relevance of this work, strict rules that adhere to real-world requirements for IC design and manufacturing were postulated by the organizers. For example, not a single violation for timing and design-rule checks were allowed for defense techniques. Besides, in an advancement over prior art, neither red nor blue teams were allowed to use any so-called fillers and spares for trivial attack or defense approaches.Finally, we release all methods and artifacts: the representative IC layouts and HTs, the devised attack and defense techniques, the evaluation metrics and setup, the technology setup and commercial-grade reference flow for IC design, the encompassing benchmarking framework, and all best results. This full release enables the community to continue exploring this important challenge for hardware security, in particular to focus on the urgent need for further advancements in defense strategies.

An ultra-wideband current-reused LNA MMIC with negative feedback and adaptive bias networks

Abstract An ultra-wideband current-reused low-noise amplifier (LNA) monolithic microwave integrated circuit design is presented in this letter. Negative feedback networks are employed at both stages of the proposed LNA to expand bandwidth. Furthermore, source adaptive bias networks is designed in the first stage and combined with a current-reused construction to acquire a compact chip size and maintain low power consumption. Then, the validation of design theory is implemented by employing a 0.15-µm gallium arsenide pseudomorphic high-electron-mobility transistor process. The measured results show that the proposed LNA achieves a small signal gain of 15.5–17.8 dB, a noise figure of 3–3.65 dB, and an output 1 dB compression point (OP1 dB) of 14.5–15.5 dBm from the target bandwidth of 2–18 GHz. In addition, the fabricated LNA consumes 220 mW from a 5 V supply and occupies a chip area of 1.2 × 1.5 mm2.

Four-element LC-baluns for power matching arbitrary impedances

Abstract Six four-element balun topologies are introduced that enable complex impedance matching in addition to common-mode rejection. Design equations for these topologies are presented. Three of these networks are universal, while the other three are capable of performing only specific impedance transformations. Examples of these networks were designed and fabricated along with a traditional lattice balun network for an operating frequency of 300 MHz. These networks were verified through extensive electromagnetic simulations and by measuring the fabricated networks. The fabricated novel network examples were able to achieve common-mode rejection ratios above 20 dB, power wave reflection coefficients below −20 dB, and insertion losses of approximately 0.1 dB; these results were similar to or better than the performance of the fabricated traditional lattice balun. The design example networks also provided power matching and low insertion loss over a greater bandwidth compared to the fabricated traditional network. These networks will allow for the footprints of lumped-element balun circuitry to be reduced, which is particularly useful in integrated circuit design. These topologies are also expected to further increase radio-frequency (RF) circuit design flexibility by offering more alternative realizations.

Mutual advancement: How integrated circuits interact with artificial intelligence

Abstract. Integrated circuits and artificial intelligence complement each other. On one hand, the continuous optimization of electron and photon accelerators can reduce the energy consumption of artificial intelligence algorithms and adapt them to edge computing, thereby promoting the development of artificial intelligence. On the other hand, artificial intelligence not only assists in troubleshooting and optimizing of integrated circuits, but also automates the design of integrated circuits, making them more convenient and efficient. The interactive relationship between integrated circuits and artificial intelligence is presented through qualitative analysis and literature review in this paper. The mutual influence of these two technologies creates new breakthroughs and possibilities for the development of science and technology. However, while photonic artificial intelligence accelerators are suitable for high-speed neural networks, their current development is not yet mature due to the high cost, complex manufacturing process, and environmental disturbances. Additionally, artificial intelligence algorithms for integrated circuits design lack sufficient high-quality data for training due to the secrecy of integrated circuit parameters. Thus it requires a long time to train and perfect these algorithms.

Fault classification in Digital to Analog Converter using machine learning

ABSTRACT The cost of manufacturing Integrated Circuit (IC) is affected strongly by the test time, cost of test equipment and test procedure development. Mixed Signal Integration in an IC has analog circuits and digital circuits both combined in a single die. Combining both analog circuits and digital circuits leads to sophisticated high functionality design. The cost for testing those analog circuit parts are mostly dominated in total cost of testing a Mixed Signal IC. Considerable efforts are invested by IC manufacturers to minimise production costs in the design and testing of mixed signal IC. Classification and distinguishing catastrophic faults of analog integrated circuits are gaining importance in recent days in order to reduce IC test cost. In this work, Back Propagation Neural Network (BPNN) and Random Forest are used to classify the faults in Digital-to-Analog Converters (DACs). Performance comparison of BPNN and Random Forest is made based on their fault classification efficiency in which BPNN classifies the fault with 98.1% accuracy, Random Forest classifies the fault with 98.8% accuracy.

Analysis of Gain Enhancement Techniques in Integrated Circuit Design

Abstract. Today, the size of semiconductor devices is still decreasing, which makes the circuit more integrated, faster computing speed, and lower power consumption. But for a single transistor, some performance degrades. One of the important properties is voltage gain, which must be compensated with some special methods in the design. This paper will focus on the discussion and analysis of four methods, which are able to improve the voltage gain. These are cascode amplifier, cascade amplifier, gain boosting, and bootstrapping. In this letter, their respective advantages and disadvantages will be discussed. Furthermore current applications and possible external development of these methods are also important part of this paper. In this part, the discussion will be further expanded and summarized on the basis of previous studies. Hopefully, these studies can help others gain a more comprehensive understanding of these technologies and provide a theoretical basis for future high-performance analog integrated operational amplifier research and design.

The Application of Secondary Effects in Optimizing Analog Circuits

Abstract. This study delves into the application of secondary effects, specifically body effect, channel length modulation effect, and subthreshold conduction effect, in the optimization of analog integrated circuits. The research highlights the critical role these effects play in modern circuit design, especially as device dimensions continue to shrink. Through a systematic analysis, the study presents key strategies for mitigating these effects to enhance circuit performance, reliability, and power efficiency. Notably, the implementation of a transient BD scheme in partially analog-assisted D-LDOs (Digital Low Dropout Regulators) has shown a performance improvement of over 10% compared to schemes without this enhancement, while also significantly reducing total coupling. Techniques such as DIBL effect compensation have proven effective in reducing load sensitivity and power consumption. This study provide valuable insights and practical approaches for the design and optimization of high-performance, energy-efficient electronic systems, making a significant contribution to the field of integrated circuit design.

Legal Regulation of Integrated Circuit Design Protection in Light of the Saudi Law

Legal Regulation of Integrated Circuit Design Protection in Light of the Saudi Law

Closing the Gap between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors

The design of integrated circuits in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices and interconnections on the layout, a design task that has stubbornly defied all automation attempts. In this paper, one limitative factor is identified that must be addressed to finally push automation tools into the analog integrated circuit design flow: accurate assessment of post-layout performance degradation. For this purpose, a performance-driven placement generator highly integrated with off-the-shelf tools already adopted by circuit/layout designers, i.e., circuit simulator, verification tools (layout-versus-schematic) and layout extractor, is proposed. Toward maximum post-layout accuracy, this generator promotes an exhaustive simulation-based synthesis, extracting, simulating and verifying the post-layout functional behavior of every candidate floorplan. Additionally, to bypass the time-consuming extractions/simulations and accelerate synthesis, novel post-layout performance regressors based on different highly accurate machine learning techniques are also being developed. The data used to train them can be directly and conveniently acquired from previous precise post-placement simulations. Experimental results over two analog circuit structures show that a set of performance regressors based on tree-based models, while operating on compressed design spaces, allow for the speeding up of synthesis by more than 20×, which represents a step toward an efficient fully automatic performance-driven analog integrated circuit design flow.

AI-Driven DRC Routing Convergence in IC Design : A Paradigm Shift in Semiconductor Development

This article explores the transformative impact of Artificial Intelligence (AI) on Integrated Circuit (IC) design, particularly in Design Rule Checking (DRC) and routing convergence. As semiconductor technology advances to smaller nodes, traditional design methodologies struggle with increasing complexity, time-to-market pressures, and stringent manufacturing constraints. Integrating AI-driven approaches offers promising solutions, dramatically reducing design cycles, improving yield, and enabling continued scaling. The article discusses the challenges of modern IC design, the critical role of DRC, and the AI revolution in routing optimization. It examines the benefits of AI-driven DRC routing convergence, including reduced time-to-market, improved design quality, cost reduction, enhanced scalability, and adaptability to new processes. Finally, it addresses current challenges and future research directions in this rapidly evolving field.

Flexible modular strategy for tailored, human–machine fusion wearable electronics

Over the past three decades, the field of wearable electronics has experienced significant growth, with future developments expected to lead to more seamless integration and a profound symbiosis between humans and electronic systems. However, current developments in wearable technology are constrained by traditional integrated circuit (IC) design paradigms and a limited range of form factors, predominantly manifesting as watches, glasses, and rings with fixed functionalities and performance capabilities. This study proposes a modular design method that leverages flexible electronics for tailoring wearable devices according to specific needs. This approach disperses and reinterprets the integrated device forms through the guidance of human body morphology and conformal design principles. The functional units within these wearable devices are constructed as physically isolated, flexible modules within a robust bus structure. These modules can be easily integrated using magnetic attachments and connectors, which allows for the creation of unconventional wearable devices with customised functionalities and forms. To validate this approach, a series of flexible functional modules were designed and prototyped. Demonstrations of some of these integrated wearable forms, including watches, headbands, and gloves, highlight the versatility of this approach. These devices can be rapidly assembled with selected flexible modules capable of monitoring vital signs, such as heart rate, peripheral capillary oxygen saturation (SpO2), barometric pressure, humidity, and temperature. The results suggest that the proposed modular method holds significant potential for advancing the development of future human–machine fusion wearable electronics.

A Research of the Integrated Circuit Design and Optimization

With the scientific and technical revolution going on, integrated circuit has been playing a vital role in our daily life ever since. In IC (Integrated circuit) design and manufacturing, layout of the integrated circuit determines its success or failure. However, the constantly decreasing characteristic size and progressive process bring about some new issues. That is why in post-Moore’s Law period, the design and optimization of layouts deserves attention of the whole industry. A properly designed and optimized layout not only results in better performance while using, but also cut out the cost of manufacture. In this paper, the methodology of integrated circuit layout design and optimization are discussed. For design, the author presented the whole flow of how the layout is generated and principles in integrated circuit design. For optimization, two approaches are analyzed. One is shorting out the critical area. Based on critical area theory and methodology of image processing, layouts can be improved in configuration. The method discussed here makes a modification on the previous way to make the optimization more accurate and efficient. The other method is inserting auxiliary polysilicon, which can counteract the impact of channel length change of MOSFETs and focus error as a unavoidable result of the process improvement.

SiGe high-frequency pulse-width modulation for low-noise applications

This paper details the first-known experimental observation of pulse-width modulation at 100 MHz using silicon-germanium HBT technology. By performing pulse-width modulation (PWM) at a higher frequency, undesired harmonic-components—which are interpreted as noise—are likewise raised to higher frequencies. In doing so, the noise generated by the PWM controller can be raised to frequencies at which it is no longer relevant. Noise-free operation is guaranteed below the operating frequency of the PWM controller, so long as the semiconductor technology supports high-frequency waveform generation. Such capability is readily provided by modern silicon-germanium HBT technology. The paper also provides an integrated-circuit design with additional flexibility for the end user, with simulated performance results.

Application of Multi-Input Multi-Output Brain-Computer Interface in Cognitive Assessment for Alzheimer’s Disease

This research aims to augment human cognitive abilities, particularly memory function, through the development of innovative prosthetics. The hippocampus, a crucial brain region involved in memory encoding and recall, has been the focal point of numerous studies seeking to develop prosthetics that can restore or enhance memory function in individuals with impairments such as Alzheimer’s disease. This review examines two studies that delve into the development and application of hippocampal neural prosthetics, highlighting the potential of these prosthetics to revolutionize the treatment of memory impairments. One study utilized static neural stimulation patterns to enhance memory for specific information content, while another developed a nonlinear Multiple Input Multiple Output (MIMO) dynamic model to predict and stimulate neural activity patterns during memory encoding. Both studies demonstrated significant improvements in memory performance. Additionally, this paper discusses the clinical significance and application prospects of hippocampal neural prosthetics, including the potential for implantable prosthetics and the widespread applicability of MIMO stimulation. Furthermore, the paper explores advanced modeling and classification techniques for neural ensembles and visual memory decoding, including Volterra-type hierarchical modeling, optimal multi-unit stimulation patterns, and a sparse classification model for decoding visual memories. Finally, the paper presents the implementation and evaluation of neural prosthesis systems, including an application-specific integrated circuit (ASIC) design for a hippocampal prosthesis and a high-performance, scalable system architecture for real-time estimation of neural activity. These advancements hold promise for future research and applications in neural prosthetics for memory enhancement.

Reliable Synchronous and Asynchronous Counter Design in QCA

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures.

Analysis and Design of an SiC CMOS Three-Channel DC-DC Synchronous Buck Converter for High-Temperature Applications

In this study, we present the design, simulation, and implementation of a DC-DC synchronous buck converter utilizing IISB’s 2 μm 4H-silicon carbide (SiC) complementary metal–oxide–semiconductor (CMOS) technology. The converter is designed to meet the demands of modern integrated circuits, particularly in the field of integrated power management. The SiC technology offers enhanced performance and reliability at high temperatures, making it especially suitable for applications that operate in these conditions, including automotive systems, and aerospace, among others. The power transistors and gate drivers are fully integrated on-chip, optimizing efficiency and minimizing footprint. Additionally, the study contributes to the understanding of SiC technology and its application in integrated circuit design. Simulation results demonstrate a peak efficiency of 86.6% at 120 mA load current and 84.8% at 300 mA load current, showing the converter performance under different operating conditions. Furthermore, at high temperatures (295 °C), the converter achieves an efficiency of 89.6%, demonstrating its robustness and versatility in extreme environments. These findings contribute to the advancement of integrated circuit design and facilitate advancements in more efficient and robust power management solutions.