Failure Analysis Of Integrated Circuits Research Articles

How Many Microscopies Does It Take to Get to the Root Cause of the Fail? Sample Prep, Imaging, and In-Situ Analysis for Integrated Circuit Failure Analysis at the 14nm Node

How Many Microscopies Does It Take to Get to the Root Cause of the Fail? Sample Prep, Imaging, and In-Situ Analysis for Integrated Circuit Failure Analysis at the 14nm Node

Integrated circuit failure analysis and reliability prediction based on physics of failure

It is difficult to obtain the failure data of actual prototype to support reliability analysis because the development stage has been shortened drastically and the traditional reliability tests are gradually unaffordable under the market pressure. In this paper, a reliability simulation based on physics of failure is proposed to test the reliability of a CPU circuit board, in which the digital model of the circuit board, Computational Fluid Dynamics (CFD) method and Finite Element Analysis (FEA) are used synthetically to perform the analysis. The failure points of the circuit board are analyzed and the failure distribution is obtained by fitting the simulation data, so the life can be predicted by Monte Carlo simulation. Moreover, some improvement measures and suggestions can be supplied based on the failure mechanism of the circuit board to improve its inherent reliability. Comparing with the traditional methods, the method of reliability simulation prediction based on physics of failure has the advantages of fast, accurate, economical, efficient and can identify more detailed failure information.

Fault localization in a 3D test assembly using voltage contrast imaging

As 3D-integration continues its acceptance as a next generation advanced packaging technology, characterization techniques regarding fault identification and localization require adaptation for the various geometries utilized. A particular challenge for 3D-stacked integrated circuit (IC) structures is the difficulty in cross-sectional fault localization using common techniques such as cleaving and focused ion beam (FIB) milling that are routinely used for planar IC failure analysis but are incompatible with the material removal challenges associated with multi-tier 3D-IC structures. The work presented here demonstrates the use of voltage contrast imaging in conjunction with backside chip thinning to gain access to and precisely identify inter-layer faults within a three-dimensional (3D) bonded, electrically testable stack structure. Subsequent cross-sectional TEM analysis performed on identified electrical continuity faults confirmed the lack of contact at fault locations between opposing Cu bonding structures which was attributed to particle contamination from the fabrication process. Several test samples did however exhibit sufficient contact and bonding which was evident by the self-diffusion of Cu across the bonding interface.

IC Failure Analysis Due to Charged Board Events by Measurements and Modeling of Discharging Currents Through IC Pins

Commercial integrated circuits (ICs) were assembled on several practical printed circuit board (PCB) structures, and the discharging currents through individual pins of the IC induced by charged board events (CBE) were measured using shielded Rogowski coils. The overall CBE measurement setup was modeled and validated using circuit simulations. The structures of PCBs and a test ground plane were effectively modeled using a multilayered finite-difference method. Electrostatic discharge protection circuits in the IC were also modeled as behavioral circuit models. From the measurement and modeling of the CBE discharging currents at the IC pins, IC failure mechanisms were analyzed according to PCB structure, decoupling capacitor, and discharging points. Several strategies for IC protection against CBE risks were also obtained.

A review of the technology and process on integrated circuits failure analysis applied in communications products

The failure analysis of integrated circuits plays a very important role in the improvement of the reliability in communications products. This paper intends to mainly introduce the failure analysis technology and process of integrated circuits applied in the communication products. There are many technologies for failure analysis, include optical microscopic analysis, infrared microscopic analysis, acoustic microscopy analysis, liquid crystal hot spot detection technology, optical microscopic analysis technology, micro analysis technology, electrical measurement, microprobe technology, chemical etching technology and ion etching technology. The integrated circuit failure analysis depends on the accurate confirmation and analysis of chip failure mode, the search of the root failure cause, the summary of failure mechanism and the implement of the improvement measures. Through the failure analysis, the reliability of integrated circuit and rate of good products can improve.

Leakage current study and relevant defect localization in integrated circuit failure analysis

The purpose of integrated circuit (IC) failure analysis (FA) is to find and to explain failure root cause and mechanism, which helps IC designer and manufacturer to improve design and process. Leakage current presence within circuit is the main failure root cause among the FA cases, although the leakage currents within different circuits can stimulate a variety of IC failure modes. It is significant to study the leakage currents within ICs and to localize relevant defects quickly and accurately by the combination of some complementary FA techniques. However, it is difficult to identify the original leakage current from the consequential leakage currents and to locate the relevant defect.In this paper, we explain the shape and location of a photon emission spot induced by an original leakage current is different from the one induced by a consequential leakage current. In a general case, and not only in this photon emission spot case, a method is elaborated to identify the original leakage current from the consequential leakage currents and to exactly locate the relevant defect by the combination of some complementary FA techniques. Some other functional failure cases will be studied to demonstrate adaptation and interest of this general method.

Benefits of field failure distribution modeling to the failure analysis

The automotive components are newly subjected to safety requirements that are defined in particular by the ISO26262 standard. Meanwhile, customers request risk assessments or prediction studies on the number of failures expected in the field. These requirements from the ISO26262 standard and from customers lead component manufacturers to study new methods of failure rate estimation, in particular from field results. In this article, field failure distribution modeling with a typical Weibull model and its benefits for integrated circuit failure analysis are presented. Three case studies are detailed, in which the results obtained by the field modeling allowed to discriminate a failure by its Weibull parameters, to study the influence of application on the failure occurrence and the possibility to predict a quality crisis.

Physical analysis of breakdown in high-κ/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)

In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-κ materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in high-κ/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing “design for reliability” (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22 nm and 15 nm. Hf-based high-κ materials in conjunction with various gate electrode technologies will be used as main examples while other potential high-κ gate materials such as cerium oxide (CeO 2) will also be demonstrated to further illustrate the concept of DFR.

Integrated circuit failure analysis using physical ion sputtering

A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed.

Combining Refractive Solid Immersion Lens and Pulsed Laser-Induced Technique for Integrated Circuit Failure Analysis

Abstract The best spatial resolution that can be achieved with far-field optical fault localization techniques is around 20 times larger than the critical defect size at the 45 nm technology node. There is also a limit on the laser power that can be safely used on 45 nm devices, which further compromises fault localization precision. In this article, the authors explain how they overcome these limitations using pulsed laser-induced imaging techniques and a refractive solid immersion lens. Two case studies show how the combination of pulsed-laser scanning optical microscopy and a solid immersion lens improves localization precision and detection sensitivity.

Location of current carrying failure sites in integrated circuits by magnetic force microscopy at large probe-to-sample separation

In integrated circuit failure analysis excessive current flow is often used to indicate the presence of faulty devices. By imaging the magnetic field produced by current flowing in integrated circuit conductors, these faulty devices can be located. Fault location by magnetic field imaging can be problematic as the devices are often buried under several layers of dielectrics and conductors that are up to several microns thick. In this paper we present a new technique for fault location based on magnetic force imaging of the magnetic field. By subtracting magnetic force images acquired at different probe-to-sample distances, the effects due to background, and probe geometry can be eliminated. We demonstrate that this method is capable of locating current carrying failure sites in model circuits with sub-micrometer uncertainty. We show how the technique can be used to map current paths in the presence of interfering currents on power supply and ground lines.

Effect of physical defect on shmoos in CMOS DSM technologies

Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.

Automatic integrated circuit die positioning in the scanning electron microscope.

In scanning electron microscope (SEM)-based integrated circuit (IC) failure analysis, there is often a need for manual location of a prespecified failure site in several ICs. Such a procedure is both tedious and time consuming. This paper presents a new vision-based die positioning system that can automatically locate a specified failure site without the need for a high-accuracy specimen stage. Depending on the appearance of the desired failure site, the system applies either image registration or feature tracking to locate the site. Experiments performed on a variety of IC samples show that the system is able to locate the failure site accurately, even in the presence of unfavorable conditions such as IC sample rotation and repetitive IC patterns.

Location of Current Carrying Faults in Integrated Circuits by Magnetic Force Microscopy

ABSTRACTIn Integrated Circuits failure analysis excessive power supply current flowing into the IC is often used to indicate the presence of a faulty device. Location of these faulty devices can be problematic as the devices are often buried under several layers of conducting interconnect. By imaging the magnetic field produced by current flowing in an IC a faulty device can be located. In this paper we present experimental results on imaging current-carrying faults on integrated circuits using Magnetic force microscopy. We have experimentally determined that MFM is capable of measuring currents as small as 1 to 10 microampere on ICs in a 30 Hz bandwidth. We have carried out modeling calculations comparing the simulation results with experimental results using realistic MFM tip geometry. From these results we have devised a method to accurately locate the position of the internal current carrying faults from MFM images with micrometer uncertainty.

Absolute quantitative time resolved voltage measurements on 1 μm conducting lines of integrated circuits via electric force microscope-(EFM-) testing

This paper reports on a novel EFM-testing system for absolute quantitative voltage measurements. It shows improved performance data enabling quantitative EFM-testing within today's integrated circuits (ICs) for the first time. This novel testing system is opening new possibilities of IC internal function and failure analysis due to submicrometer spatial and some tens of nanoseconds time resolution limits in combination with high sensitivity of some tens of millivolt.

Application of the atomic force microscope to integrated circuit failure analysis

In IC research centers over the past two years, the Atomic Force Microscope (AFM) has become a fairly common tool. Nondestructive imaging with nanometer resolution on uncoated samples in ambient conditions is proving to have a wide range of applications in IC research. Also, during this same period important advances have been made in scanning probe microscopy, particularly relating to atomic force probes. AFM technology has now found acceptance in IC manufacturing as well as research. These new advances include: large sample (full wafer) capability, sharper probe tips capable of measuring sidewalls as steep as 15 degrees from the vertical, noncontact topography measurements, frictional-force measurements, and cross-section analysis. True three-dimensional nanometer-scale metrology can now be applied to process control and failure analysis. Some uses and applications to semiconductors are (1) surface roughness measurment of polished silicon wafers for gate oxide performance improvements, (2) surface roughness of deposited layers, (3) grain-size measurement, (4) depth measurement for etcher control, (5) step-height measurement, (6) gate-oxide integrity, (7) deposited layer integrity over lines, (8) monitoring the effectiveness of cleaning steps, (9) cross-section imaging, (10) high-resolution imaging for process inspection, (11) planarization quality, (12) phase-shift mask development, (13) chrome photomasks — defect imaging and sizing, line-edge quality, (14) defect imaging and sizing, and (15) spin-on glass cure and pore-size process studies

Application of the atomic force microscope to integrated circuit reliability and failure analysis : Mark R. Rodgers. IEEE/IRPS, 250 (1991)

Application of the atomic force microscope to integrated circuit reliability and failure analysis : Mark R. Rodgers. IEEE/IRPS, 250 (1991)

TEM sample preparation with focused ion beams

The continuing reduction in the sizes of features of interest for integrated circuit failure analysis requires greater precision in transmission electron microscopy (TEM) sample preparation. With minimum feature sizes approaching 0.5 μm, the mere finding of such a feature at a polished edge, let alone preparing a TEM sample containing it becomes a formidable task. The required substantial thinning also increases the risk of loss of what may be a unique sample.We present in this paper a technique that allows localized thinning of cross-sectional TEM samples using a focused ion beam (FIB) machine. Standard preparation techniques are used to make a cross-sectional TEM sample that would otherwise be too thick to be very useful for TEM analysis. This sample is then placed in the FIB machine, which is used as a micromachining tool. No special surface preparation is necessary and the secondary electron signal generated by the ion beam provides an image that can be used to locate the feature of interest.

Logic-state measurement for passivated integrated circuits using multistroboscopic sampling

To measure the logic state of passivated integrated circuits (ICs) using an e-beam tester, we have devised voltage measurement and logic thresholding techniques to reduce the heavy e-beam dosage required in very long test sequences. These techniques make measurement stable by reducing both the e-beam dosage and measurement time without compromising a reliability. It takes 30 s to measure logic states of a 16 K-step-length test sequence at a probe point. Measurement is estimated as stable up to 200 K steps for passivated ICs, sufficient for the practical failure analysis of complex logic ICs.

4961812 Etch-back apparatus for integrated circuit failure analysis

4961812 Etch-back apparatus for integrated circuit failure analysis