Fault localization in a 3D test assembly using voltage contrast imaging

Abstract

As 3D-integration continues its acceptance as a next generation advanced packaging technology, characterization techniques regarding fault identification and localization require adaptation for the various geometries utilized. A particular challenge for 3D-stacked integrated circuit (IC) structures is the difficulty in cross-sectional fault localization using common techniques such as cleaving and focused ion beam (FIB) milling that are routinely used for planar IC failure analysis but are incompatible with the material removal challenges associated with multi-tier 3D-IC structures. The work presented here demonstrates the use of voltage contrast imaging in conjunction with backside chip thinning to gain access to and precisely identify inter-layer faults within a three-dimensional (3D) bonded, electrically testable stack structure. Subsequent cross-sectional TEM analysis performed on identified electrical continuity faults confirmed the lack of contact at fault locations between opposing Cu bonding structures which was attributed to particle contamination from the fabrication process. Several test samples did however exhibit sufficient contact and bonding which was evident by the self-diffusion of Cu across the bonding interface.