Logic-state measurement for passivated integrated circuits using multistroboscopic sampling

Abstract

To measure the logic state of passivated integrated circuits (ICs) using an e-beam tester, we have devised voltage measurement and logic thresholding techniques to reduce the heavy e-beam dosage required in very long test sequences. These techniques make measurement stable by reducing both the e-beam dosage and measurement time without compromising a reliability. It takes 30 s to measure logic states of a 16 K-step-length test sequence at a probe point. Measurement is estimated as stable up to 200 K steps for passivated ICs, sufficient for the practical failure analysis of complex logic ICs.