Integrated Circuit Applications Research Articles

The camera and readout for the Trinity Demonstrator and the EUSO-SPB2 Cherenkov telescope

We developed a modular silicon photomultiplier camera to detect Earth-skimming PeV to EeV tau neutrinos with the imaging atmospheric Cherenkov technique. We built two cameras, a 256-pixel camera for the Trinity Demonstrator located on Frisco Peak, Utah, and a 512-pixel camera for the Extreme Universe Observatory on a Super-Pressure Balloon II (EUSO-SPB2) Cherenkov Telescope. The front-end electronics are based on the Multipurpose Integrated Circuit (eMUSIC) Application Specific Integrated Circuits (ASICs), and the camera signals are sampled and digitized with the 100MS/s and 12-bit ASIC for General Electronics for TPC (AGET) system. Both cameras are liquid-cooled. We detail the camera concept and the results from characterizing the SiPMs, bench testing, and calibrating the two cameras.

Efficient design of a reversible 2-to-4 decoder in quantum-dot cellular automata using Toffoli gates

This research presents an optimized design of a 2-to-4 decoder in Quantum-dot Cellular Automata (QCA) using a new formula developed from the Reversible. The proposed QCA decoder architecture employs 112 cells and occupies an area of 0.13μm², achieving a significant reduction in size compared to previous designs. The circuit is designed using a single-layer approach, enhancing its efficiency and minimizing power dissipation. Simulation results using the QCA Designer simulator version 2.0.3 demonstrate the enhanced functionality of the suggested decoder in regard to functionality and also efficiency, making it a promising candidate for future nanoscale integrated circuit applications.

Investigation of width-to-length ratio on the performance of ZnO transistors and inverters

Abstract Oxide transistors have attracted considerable attention in the field of integrated circuits. In this work, ZnO transistors were fabricated using atomic layer deposition process, with various width-to-length (W/L) ratios of 100/10 μm, 50/10 μm, 20/5 μm, 10/5 μm, and 10/10 μm. Among them, the ZnO transistor with a W/L ratio of 10/10 μm demonstrated superior electrical performance, including a field-effect mobility of 37.65 cm²V-1s-1, a subthreshold swing of 112.50 mV/decade, and a turn-on voltage of -0.50 V. Additionally, n-type ZnO transistors were used to design inverter circuits, where the voltage gain was found to be inversely correlated with the W/L ratio of the load transistor. A maximum voltage gain of 59.33 V/V was achieved at a supply voltage of 5 V using a load transistor with a W/L ratio of 10/5 μm. These results indicate that ZnO transistors, with optimized design, offer promising performance for future integrated circuit applications.

Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application

The gate-all-around (GAA) structure avoids the problems inherent in miniaturizing field-effect transistors (FETs), such as off-state leakage current and short-channel effects. Among GAA structures, vertical GAA (VGAA) structures are expected as promising building blocks for future three-dimensional integrated circuit applications. The vertical III-V nanowires (NWs) on Si are expected as the fast channel materials for the VGAA structures on Si platforms. Thus, the combination of the VGAA structure with III-V NWs on Si significantly enhances on-state current while maintaining good gate controllability under low supply voltage. In addition, III-V NWs/Si tunnel junctions, which are formed by the direct integration of vertical III-V NWs on Si, can be utilized as VGAA tunnel FETs (TFETs) for low-power switch. Here we report on direct integration of vertical InGaAs NWs on silicon-on-insulator (SOI) substrates by selective-area growth and demonstrations of InGaAs NW-channel VGAA transistors (FETs and TFETs) on SOI.

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Tunnel field-effect transistors (TFETs) are expected to be used as a next-generation low-voltage switching device. The TFETs can lower the subthreshold slope (SS) below the physical limit (SS = 60 mV/dec at room temperature) in conventional MOSFETs. Here we demonstrated InAs nanowire (NW)/Si heterojunction vertical gate-all-around (VGAA) TFETs on silicon-on-insulator (SOI) (111) substrates toward vertical integrated circuit applications. The vertical InAs NW channels were grown by selective-area growth on thin SOI(111) substrates.

High‐Performance, Single‐Component Ambipolar Organic Electrochemical Transistors with Balanced n/p‐Type Properties for Inverter and Biosensor Applications

AbstractAmbipolar organic electrochemical transistors (OECTs) with a single organic mixed ionic‐electronic conductor (OMIEC) have unique advantages by reducing fabrication complexity and cost in complementary logic circuit and bioelectronic applications. However, the design and synthesis of high‐performance ambipolar OMIECs for efficient transport and coupling both cation/anion and electron/hole remain challenging. Herein, a donor–acceptor (D–A)‐typed ambipolar OMIEC polymer (DHF‐gTT) is presented, whose superior ambipolarity stems from the concurrent oligoethyleneglycol‐functionalized D/A units that facilitates cation/anion injection and transport. Additionally, the fluorination of acceptor unit improves both hole/electron transports due to the fully‐locked backbone and promotes electron injection by down‐shifting molecular energy levels. Consequently, DHF‐gTT‐based OECTs achieve balanced figure‐of‐merit (µC*) for both p‐type and n‐type operations (12.4–14.6 F cm−1 V−1 s−1), setting new benchmarks for ambipolar OECTs, in terms of n‐type µC* and electron/hole mobilities. Such ambipolar OECTs enable the inverter to achieve a record‐high gain (102 V/V) and associated n‐type and p‐type molecular detectors to offer real‐time and highly sensitive detection of histamine and hydrogen peroxide detection, respectively. These results indicate the effectiveness of judicious molecular design on achieving high‐performance ambipolar OMIECs, allowing the state‐of‐the‐art single‐component ambipolar OECTs for both highly integrated logic circuit and bioelectronic applications.

Optimizing Integrated Circuit Applications with Digital IIR Filtering Architectures

Optimizing Integrated Circuit Applications with Digital IIR Filtering Architectures

Two-Dimensional Semiconductors for State-of-the-Art Complementary Field-Effect Transistors and Integrated Circuits.

As the trajectory of transistor scaling defined by Moore's law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities.

Photonic topological phase transition induced by material phase transition.

Photonic topological insulators (PTIs) have been proposed as an analogy to topological insulators in electronic systems. In particular, two-dimensional PTIs have gained attention for the integrated circuit applications. However, controlling the topological phase after fabrication is difficult because the photonic topology requires the built-in specific structures. This study experimentally demonstrates the band inversion in two-dimensional PTI induced by the phase transition of deliberately designed nanopatterns of a phase change material, Ge2Sb2Te5 (GST), which indicates the first observation of the photonic topological phase transition in two-dimensional PTI with changes in the Chern number. This approach allows us to directly alter the topological invariants, which is achieved by symmetry-breaking perturbation through GST nanopatterns with different symmetry from original PTI. The success of our scheme is attributed to the ultrafine lithographic alignment technologies of GST nanopatterns. These results demonstrate how to control photonic topological properties in a reconfigurable manner, providing insight into the possibilities for reconfigurable photonic processing circuits.

Preparation Of Carbon Nanotube Transistors and Their Applications in Integrated Circuits

Preparation Of Carbon Nanotube Transistors and Their Applications in Integrated Circuits

Electric Field-Manipulated Optical Chirality in Ferroelectric Vortex Domains.

Manipulating optical chirality via electric fields has garnered considerable attention in the realm of both fundamental physics and practical applications. Chiral ferroelectrics, characterized by their inherent optical chirality and switchable spontaneous polarization, are emerging as a promising platform for electronic-photonic integrated circuits applications. Unlike organics with chiral carbon centers, integrating chirality into technologically mature inorganic ferroelectrics has posed a long-standing challenge. Here, the successful introduction of chirality is reported into self-assembly La-doped BiFeO3 nanoislands, which exhibit ferroelectric vortex domains. By employing synergistic experimental techniques with piezoresponse force microscopy and nonlinear optical second-harmonic generation probes, a clear correlation between chirality and polarization configuration within these ferroelectric nanoislands is established. Furthermore, the deterministic control of ferroelectric vortex domains and chirality is demonstrated by applying electric fields, enabling reversible and nonvolatile generation and elimination of optically chiral signals. These findings significantly expand the repertoire of field-controllable chiral systems and lay the groundwork for the development of innovative ferroelectric optoelectronic devices.

Quantization Conductance of InSb Quantum-Well Two-Dimensional Electron Gas Using Novel Spilt Gate Structures

Electron transport behaviour in InSb semiconductor significantly changes when the conduction is restricted to two-dimensions. Semiconductor materials are an effective tools to characterize the electron transport in this aspect because the energy separation between transverse modes in a low-dimensional semiconductor device are always inversely proportional to the effective mass, in the same way as for sub-bands in a parabolic potential. Therefore, in this article, a range of novel device geometries were designed, fabricated and characterized to investigate ballistic transport of electrons in low-dimensional InSb structures using surface gated devices to restrict the degrees of freedom (dimensionality) of the active conducting channel. In this framework, designs of gates (i.e., line, loop and solid discussed later) have been used over a range of gate dimensions. Consistent measurement of quantised conductance would be promising for both low power electronics and low temperature transport physics where split gates are typically used for charge sensing. This article presents an experimental results of quantization conductance obtained for the range geometries of novel gates, and some model consideration of the implications of the material choice. Furthermore, the etching techniques (wet and dry) exhibited a significant decrease of ohmic contact resistance from around 35kΩ to only roughly 250Ω at room temperature. Interestingly a possible 0.7 anomaly conduction was observed with a loop gate structure. This work showed perfectly that the two-dimensional electron gases can be formed in narrow gap InSb QWs which makes this configuration device promising candidate for topological quantum computing and next generation integrated circuit applications. Keywords: Quantization conductance, InSb QW, 2DEG, spilt gate structure, ballistic transport.

Site-Selective Synthesis of Bilayer Graphene on Cu Substrates Using Titanium as a Carbon Diffusion Barrier.

Chemical vapor deposition (CVD) is a widely used method for graphene synthesis, but it struggles to produce large-area uniform bilayer graphene (BLG). This study introduces a novel approach to meet the demands of large-scale integrated circuit applications, challenging the conventional reliance on uniform BLG over extensive areas. We developed a unique method involving the direct growth of bilayer graphene arrays (BLGA) on Cu foil substrates using patterned titanium (Ti) as a diffusion barrier. The use of the Ti layer can effectively control carbon atom diffusion through the Cu foil without altering the growth conditions or compromising the graphene quality, thereby showcasing its versatility. The approach allows for targeted BLG growth and achieved a yield of 100% for a 10 × 10 BLG units array. Then a 10 × 10 BLG memristor array was fabricated, and a yield of 96% was achieved. The performances of these devices show good uniformity, evidenced by the set voltages concentrated around 4 V, and a high resistance state (HRS) to low resistance state (LRS) ratio predominantly around 107, reflecting the spatial uniformity of the prepared BLGA. This study provides insight into the BLG growth mechanism and opens new possibilities for BLG-based electronics.

Simulation of 2D ReS2/WSe2 based complementary field-effect transistors towards 1 nm technology node

Advanced Integrated Circuit technology demands high-performance channel materials and innovative device architectures to sustain the scaling of field-effect transistors. In this study, we simulate the electrical performance of rhenium disulfide and tungsten diselenide nanosheet FETs (NSFETs) with gate lengths ranging from 12 nm to 8 nm using Technology Computer-Aided Design method. The simulated high performance including 393 μA/μm on-state current and over 105 on/off ratio can meet the criteria for integrated circuit applications in the 1 nm technology node. Complementary FET (CFET) simulations are conducted through the vertical stacking of ReS2 and WSe2 NSFETs, exhibiting a small parasitic capacitance of 1.0 fF/μm, and notable noise margin (>235 mV) at different process corners. The construction and performance simulation of Static Random-Access Memory (SRAM) is realized through CFET interconnection, involving the calculation of read current and read/write noise margin. This research offers a forward-looking analysis of performance metrics for future 2D materials-based NSFETs, CFETs, and SRAMs.

Design of 3D printable boehmite alumina/thermally exfoliated reduced graphene oxide-based polymeric nanocomposites with high dielectric constant, mechanical and thermomechanical performance

In this study, melt-blending was employed to blend 80 wt% poly(lactic acid) and 20 wt% poly(ε-caprolactone) (80 %PLA/20 %PCL) with boehmite alumina-thermally exfoliated reduced graphene oxide (BA-TERGO) as nanofillers. Herein, we present a novel synergy effect of BA/TERGO particles on improving the dielectric constant while maintaining dielectric loss at lower magnitudes. Also, improving the thermomechanical properties of tough PLA/PCL nanocomposite through the incorporation of a dual-filer system strategy. Consequently, remarkable increase in dielectric constant was achieved for BA-TERGO/blend nanocomposite. In particular, the blend exhibited dielectric constant of about 2.91, while the BA-TERGO/blend nanocomposite exhibited dielectric constant of about 4.93 at a frequency of 2.0 ×106 Hz and a temperature of 190 ºC. On the other hand, tensile modulus of the BA-TERGO/blend nanocomposite increased from 1908.5 MPa to 2505.2 MPa and the tensile strength increased from 70.48 MPa to 96.3 MPa when compared to that of the neat blend. BA-blend and BA-TERGO/blend nanocomposites provided the improved storage modulus and thermal stability. This finding renders PLA-based biodegradable materials suitable for tough 3D printable material with potential for integrated circuits applications.

Active manipulation for Goos-Hänchen shift of guided-wave via a metasurface of silicon-nanoscale semi-spheres on SOI waveguide

Goos-Hänchen shift of total internal reflection (TIR) is the light beam movement without external driving, so envisioned to have potential manipulation of optical beams. In this article, with a silicon-on-insulator (SOI) waveguide corner structure, a variable equivalent permittivity of guided wave is modelled, and then the equivalent electric polarizabilities and the Goos-Hänchen shift of guided wave are modelled. Consequently, with a 2.0-µm SOI waveguide corner structure and an abrupt phase change of ∼0.5π caused by a vertically inserted metasurface of nanoscale semi-spheres having a 450-nm radius can reach the GH shifts of 2.1 µm for TE- and TM-mode, respectively, which are verified by both the FDTD simulation results of 1.93 µm with a reflectivity of about 62% and the experimental results of 2.0 µm with ∼60%. Therefore, this work has efficiently modelled the optical feature response of semi-sphere metasurface to guided wave and the active manipulation for the GH shifts of guided-wave, opening more opportunities to develop the new functionalities and devices for Si-based photonic integrated circuit (PIC) applications.

Polar Bloch points in strained ferroelectric films

Topological domain structures have drawn great attention as they have potential applications in future electronic devices. As an important concept linking the quantum and classical magnetism, a magnetic Bloch point, predicted in 1960s but not observed directly so far, is a singular point around which magnetization vectors orient to nearly all directions. Here we show polar Bloch points in tensile-strained ultrathin ferroelectric PbTiO3 films, which are alternatively visualized by phase-field simulations and aberration-corrected scanning transmission electron microscopic imaging. The phase-field simulations indicate local steady-state negative capacitance around the Bloch points. The observation of polar Bloch points and their emergent properties consequently implies novel applications in future integrated circuits and low power electronic devices.

Thinning Solution‐proceed 2D Te for p‐ and n‐channel Junction Field Effect Transistor with High Mobility and Ideal Subthreshold Slope

AbstractTwo‐dimensional non‐layered tellurene (Te) can serve as a promising candidate in transistor applications because of its high carrier mobility and air stability. However, it is still quite challenging in aspect of ultra‐thin channel and gate‐control ability in conventional metal‐oxide‐semiconductor field‐effect transistor architecture. This work proposes a facile thinning strategy for solution‐proceed Te flakes and fabricates a junction field‐effect transistor (JFET) architecture, that has well addressed the above‐mentioned two issues. Through a mild oxidative thinning process, the post‐growth Te flakes are thinned from bulk to few‐layer, guaranteeing the highly efficient electrostatic doping as a transistor channel. Then, a four‐terminal JFET‐based on p‐Te and n‐ReS2 is designed, achieving a multifunctional integration of rectification diode, p‐ and n‐channel transistor in one single device. By accessing different contact scheme, the ReS2/Te p‐n diode is explored with a rectification ratio of 103, the p‐channel JFET exhibits a high hole mobility of 317.6 cm2V−1s−1, ideal low subthreshold swing of 84 mV dec−1. While the n‐channel JFET is obtained with electron mobility of 67.6 cm2 V−1s−1 and SS of 229 mV dec−1. Both p‐ and n‐channel devices showcase clear saturation characteristic with ultra‐small pinch‐off voltage (≈0.4 V), which is crucial for low‐power logical and integrated circuit applications.

Two-dimensional molybdenum ditelluride waveguide-integrated near-infrared photodetector

Low-cost, small-sized, and easy integrated high-performance photodetectors for photonics are still the bottleneck of photonic integrated circuits applications and have attracted increasing attention. The tunable narrow bandgap of two-dimensional (2D) layered molybdenum ditelluride (MoTe2) from ∼0.83 to ∼1.1 eV makes it one of the ideal candidates for near-infrared (NIR) photodetectors. Herein, we demonstrate an excellent waveguide-integrated NIR photodetector by transferring mechanically exfoliated 2D MoTe2 onto a silicon nitride (Si3N4) waveguide. The photoconductive photodetector exhibits excellent responsivity (R), detectivity (D*), and external quantum efficiency at 1550 nm and 50 mV, which are 41.9 A W−1, 16.2 × 1010 Jones, and 3360%, respectively. These optoelectronic performances are 10.2 times higher than those of the free-space device, revealing that the photoresponse of photodetectors can be enhanced due to the presence of waveguide. Moreover, the photodetector also exhibits competitive performances over a broad wavelength range from 800 to 1000 nm with a high R of 15.4 A W−1 and a large D* of 59.6 × 109 Jones. Overall, these results provide an alternative and prospective strategy for high-performance on-chip broadband NIR photodetectors.

Prospects for silicon being replaced by other materials in integratedcircuit applications

Currently, silicon is the most widely used semiconductor material. However, in recent years, the development of integrated circuits has encountered more and more limitations, among which the physical characteristics of single-crystal silicon materials are an important reason. With the expansion of integrated circuit scale and the continuous reduction of manufacturing processes, silicon has gradually reached its physical limit. At the same time, silicon has a higher calorific value and a higher performance loss. Therefore, people are actively seeking alternatives to silicon in integrated circuits. This paper reviews the characteristics of three new semiconductor materials, graphene, silicon carbide, gallium nitride, and current research on their applications. Silicon carbide and gallium nitride materials have shown outstanding performance in power-integrated circuits, while graphene has many applications. However, they still have many defects before being used on a large scale. In short, in integrated circuit applications, when new materials replace silicon, many problems remain to be solved.