Integer Arithmetic Research Articles

A Very Lightweight Encryption Method Based on Multiple Substitution Tables

We present a very lightweight encryption method based on multiple substitution tables. The method does not use sophisticated integer arithmetic and is therefore suitable for small embedded systems and other applications using simple processing elements. Plain text is encrypted one byte at a time. Each byte is replaced by the substitution element in the current table, and the plain text byte also determines the table to be used for the next byte. Encrypting and decrypting one byte involves only a table look-up, no arithmetic or bit manipulation. The same plain text byte has very small probability of being encrypted the same way twice in a row. We also present additional techniques for making the method secure against attacks when used in applications where the messages may have special or restricted forms.

The Solution of some 100-city Travelling Salesman Problems

A simplex-based FORTRAN code, working entirely in integer arithmetic, has been developed for the exact solution of travelling-salesman problems. The code adds tour-barring constraints as they are found to be violated. It deals with fractional solutions by adding two-matching constraints and as a last resort by ‘Gomory’ cutting plane constraints of the Method of Integer Forms. Most of the calculations are carried out on only a subset of the variables, with only occasional passes through the whole set of possible variables. Computational experience on some 100-city problems is reported.

A Depth-First Iterative Algorithm for the Conjugate Pair Fast Fourier Transform

The Split-Radix Fast Fourier Transform has the same low arithmetic complexity as the related Conjugate Pair Fast Fourier Transform. Both transforms have an irregular datapath structure which is straightforwardly expressed only in recursive forms. Furthermore, the conjugate pair variant has a complicated input indexing pattern which requires existing iterative implementations to rely on precomputed tables. It however allows optimization of the memory bandwidth as it requires a single twiddle factor load per radix-4 butterfly. In existing algorithms, this comes at the cost of using additional precomputed tables or performing recursive function calls. In this paper we present two novel approaches that handle both the butterfly scheduling and the input index generation of the Conjugate Pair Fast Fourier Transform. The proposed algorithm is cache-friendly because it is depth-first, non-recursive and does not rely on precomputed index tables. In order to achieve this, we relate the butterfly execution pattern of the Split-Radix and Conjugate Pair FFTs to the binary carry sequence. Based on this finding, we describe how common integer arithmetic and bitwise operations can be used to perform input reordering and depth-first traversal of the transform datapath with O(1) space complexity.

A Finite Precision Implementation of an Image Encryption Scheme Based on DNA Encoding and Binarized Chaotic Cores

Under finite precision implementation, one dimensional (1D) chaotic maps suffer from limited number of control parameters and converged periodicity, making them unsuitable for hardware based ciphering systems despite their simple implementation and low hardware cost. This paper first discusses the limited periodicity of 1D maps under fixed point precision representation, then, presents an image encryption algorithm based on DNA encoding and two specially configured binarized chaotic cores. The function of both cores is to perform the confusion and diffusion stages of the image by generating pseudo random numbers with excellent cryptographic properties. DNA encoding adds an extra layer of security to the algorithm by converting both the image and the chaotic stream to DNA sequences using specific DNA encoding rule. Initial values of both chaotic cores are image dependent based on a calculated hamming distance. These initial condition and the utilized DNA rules composes the overall secret key of the system with a total length of 336 bits. On the condition that all calculations involved in the scheme are based on binary integer arithmetic, all performed security analysis subjected to the scheme proved that the system could withstand known attacks with excellent encryption properties.

Private blockchain-based access control mechanism for unauthorized UAV detection and mitigation in Internet of Drones environment

Drones, which are also known as Unmanned Aerial Vehicles (UAVs), are very useful in delivering the packages, and real-time object detection and tracking with minimal human interference. However, there may be several security threats in such an environment, for instance, a malicious user can spy unauthorized drones, transfer malicious packages, or even damage the network reliability that can have direct impact on drones control. This may lead to a potential threat for people, governments, and business sectors. To deal with these issues, in this paper, we propose a novel access control scheme for unauthorized UAV detection and mitigation in an Internet of Drones (IoD) environment, called ACSUD-IoD. With the help of the blockchain-based solution incorporated in ACSUD-IoD, the transactional data having both the normal secure data from a drone (UAV) to the Ground Station Server (GSS) and the abnormal (suspected) data for detection of unauthorized UAVs by the GSS are stored in private blockchain, that are authentic and genuine. As a result, the Big data analytics can be performed on the authenticated transactional data stored in the blockchain. Through the detailed security analysis including formal security under the broadly-accepted Real-Or-Random (ROR) model, formal security verification using the widely-applied Automated Validation of Internet Security Protocols and Applications (AVISPA) tool and non-mathematical security analysis show the robustness of the proposed scheme against a number of potential attacks needed in an IoD environment. The testbed experiments for various cryptographic primitives using the broadly-accepted Multiprecision Integer and Rational Arithmetic Cryptographic Library (MIRACL) have been performed under both server and Raspberry PI 3 configurations. Furthermore, a detailed comparative analysis among the proposed scheme and other existing competing schemes shows the efficacy and more robustness as compared to the existing schemes. Finally, the blockchain-based practical demonstration shows the effectiveness of the proposed scheme.

The Choice of Sampling Frequency and Optimal Method of Signals Digital Processing in Problems of a Random Loading Process Treating to Assess Durability

Theoretical and practical issues of digital information processing in the problems of load assessment in the evaluation of durability are considered. Due to the specifics of the problem under consideration, in which the precise definition of the extremum values and their sequence is of paramount importance, a number of generally accepted recommendations are unacceptable. For example, the Kotelnikov theorem, which was originally proposed in relation to the problems of estimating the frequency composition of the process, can lead to significant errors. It is shown that the requirements for the analysis of random loading processes for the further purpose of assessing the durability, due to their specificity, are in contradiction with this indication, namely, when choosing a frequency according to this rule, it is very likely to make an error, and not into the safe side. It was also considered the digital filtering of hardware data. Alternative approaches to the selection of extrema of the random process are analyzed: (1) direct hardware selection of extrema and (2) discretization by the method of level crossings. The latter approach has an optimal algorithm for selecting extrema allowing selecting the extremes of the random process with less cost and greater accuracy. The natural transition to integer arithmetic allows to optimize this algorithm even more. The model and real examples demonstrate the gain in terms of speed and memory, which ultimately will help to increase the reliability of the information necessary to assess the durability. The savings in memory and performance will allow longer implementations to be processed, which ultimately allows for a more accurate estimate of the durability at the production stage and for the estimation of the residual life.

Formal Verification of Spacecraft Control Programs

Verification of correctness of control programs is an essential task in the development of space electronics; it is difficult and typically outweighs design and programming tasks in terms of development hours. This article presents a verification approach designed to help spacecraft engineers reduce the effort required for formal verification of low-level control programs executed on custom hardware. The verification approach is demonstrated on an industrial case study. We present a REDuced instruction set for Fixed-point and INteger arithmetic (REDFIN), a processing core used in space missions, and its formal semantics expressed using the proposed metalanguage for state transformers, followed by examples of verification of simple control programs.

On the design of biometric-based user authentication protocol in smart city environment

Among the security services, like authentication, access control, key management and intrusion detection, user authentication is very much needed for a smart city environment because an external authorized user may require the real time data to be accessed directly from the deployed Internet of Things (IoT) enabled smart devices. Using the established session key between the user and an access smart device though mutual authentication and key agreement process, the real time data can be securely accessed. To deal with this issue, we propose a new user authentication scheme in smart city environment using three factors of a legal registered user (mobile device, password and biometrics). The proposed scheme is shown to be robust against a number of potential attacks needed in an IoT-based smart city deployment. The simulation study for formal security verification using the widely-accepted “Automated Validation of Internet Security Protocols and Applications (AVISPA)” tool demonstrates that the proposed scheme is also secure. Furthermore, experiments on various cryptographic primitives have been carried out using “MIRACL Cryptographic SDK: Multiprecision Integer and Rational Arithmetic Cryptographic Library” under both server and Raspberry PI 3 settings. Finally, a comprehensive comparative analysis shows the effectiveness and better security of the proposed scheme as compared with other state of art user authentication schemes.

SMT encodings for Resource-Constrained Project Scheduling Problems

The Resource-Constrained Project Scheduling Problem (RCPSP) is a paradigmatic scheduling problem where the activities of a project have to be scheduled while respecting a combination of precedence and resource constraints. Precedence constraints are relations between two activities stating that one cannot start until the other has ended, and resource constraints bound the amount of resources used by activities running simultaneously. Many generalizations of the RCPSP have been proposed in the literature, including multiple execution modes for the activities (MRCPSP), or time varying resource availabilities and demands (RCPSP/t).In this work we present Satisfiability Modulo Theories (SMT) formulations to solve the RCPSP, as well as its two variants MRCPSP and RCPSP/t. Although it is really natural to formulate resource constraints of RCPSP-like problems using the linear integer arithmetic (LIA) theory, we show how, by exploiting the information provided by the precedence relations, we can obtain compact and efficient encodings of resource constraints to Boolean Satisfiability (SAT) formulas. Using these SAT encodings instead of the LIA ones, turns to be crucial regarding efficiency. The method is adapted to encode resource constraints for the other two considered variants. In this adaptation, the method exploits not only precedences, but multiple execution modes or time varying resource availabilities and demands. Our experimental results show that the proposed encodings are more efficient than existing state-of-the-art exact solving techniques for the studied problems.

Competition Report: CHC-COMP-20

CHC-COMP-20 is the third competition of solvers for Constrained Horn Clauses. In this year, 9 solvers participated at the competition, and were evaluated in four separate tracks on problems in linear integer arithmetic, linear real arithmetic, and arrays. The competition was run in the first week of May 2020 using the StarExec computing cluster. This report gives an overview of the competition design, explains the organisation of the competition, and presents the competition results.

Deep Learning Frameworks for Rapid Gram Stain Image Data Interpretation: Protocol for a Retrospective Data Analysis.

BackgroundIn recent years, remarkable progress has been made in deep learning technology and successful use cases have been introduced in the medical domain. However, not many studies have considered high-performance computing to fully appreciate the capability of deep learning technology.ObjectiveThis paper aims to design a solution to accelerate an automated Gram stain image interpretation by means of a deep learning framework without additional hardware resources.MethodsWe will apply and evaluate 3 methodologies, namely fine-tuning, an integer arithmetic–only framework, and hyperparameter tuning.ResultsThe choice of pretrained models and the ideal setting for layer tuning and hyperparameter tuning will be determined. These results will provide an empirical yet reproducible guideline for those who consider a rapid deep learning solution for Gram stain image interpretation. The results are planned to be announced in the first quarter of 2021.ConclusionsMaking a balanced decision between modeling performance and computational performance is the key for a successful deep learning solution. Otherwise, highly accurate but slow deep learning solutions can add value to routine care.International Registered Report Identifier (IRRID)DERR1-10.2196/16843

Arithmetic integer additive set-valued graphs: a creative review

For a non-empty ground set X, finite or infinite, the set-valuation or set-labeling of a given graph G is an injective function f: V(G) → P(X), where P(X) is the power set of the set X. A set-indexer of a graph G is an injective set-valued function f: V(G) → P(X) such that the function f∗ : E(G) → P(X)−{Φ} defined by f∗(uv) = f(u)∗f(v) for every uv∈E(G) is also injective, where ∗ is a binary operation on sets. Let N0 be the set of all non-negative integers and P(N0) is its power set. An integer additive set-labeling (IASL) of a graph G is an injective function f: V(G) → P(N0) such that the induced function f+: E(G) → P(N0) is defined by f+(uv) = f(u) + f(v), where f(u) + f(v) is the sumset of the sets f(u) and f(v). An IASL f of a graph G is said to be an integer additive set-indexer (IASI) of G if the induced function f+ is also injective. In this paper, we critically and creatively review the concepts and properties of a particular type integer additive set-valuation, called arithmetic integer additive set-valuation of graphs.

CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices

Low-precision integer arithmetic is a necessary ingredient for enabling Deep Learning inference on tiny and resource-constrained IoT edge devices. This brief presents CMix-NN, a flexible open-sourceCMix-NN is available at https://github.com/EEESlab/CMix-NN . mixed low-precision (independent tensors quantization of weight and activations at 8, 4, 2 bits) inference library for low bitwidth Quantized Networks. CMix-NN efficiently supports both Per-Layer and Per-Channel quantization strategies of weights and activations. Thanks to CMix-NN, we deploy on an STM32H7 microcontroller a set of Mobilenet family networks with the largest input resolutions ( $224\times 224$ ) and higher accuracies (up to 68% Top1) when compressed with a mixed low precision technique, achieving up to +8% accuracy improvement concerning any other published solution for MCU devices.

Fast Approximations of Activation Functions in Deep Neural Networks when using Posit Arithmetic.

With increasing real-time constraints being put on the use of Deep Neural Networks (DNNs) by real-time scenarios, there is the need to review information representation. A very challenging path is to employ an encoding that allows a fast processing and hardware-friendly representation of information. Among the proposed alternatives to the IEEE 754 standard regarding floating point representation of real numbers, the recently introduced Posit format has been theoretically proven to be really promising in satisfying the mentioned requirements. However, with the absence of proper hardware support for this novel type, this evaluation can be conducted only through a software emulation. While waiting for the widespread availability of the Posit Processing Units (the equivalent of the Floating Point Unit (FPU)), we can already exploit the Posit representation and the currently available Arithmetic-Logic Unit (ALU) to speed up DNNs by manipulating the low-level bit string representations of Posits. As a first step, in this paper, we present new arithmetic properties of the Posit number system with a focus on the configuration with 0 exponent bits. In particular, we propose a new class of Posit operators called L1 operators, which consists of fast and approximated versions of existing arithmetic operations or functions (e.g., hyperbolic tangent (TANH) and extended linear unit (ELU)) only using integer arithmetic. These operators introduce very interesting properties and results: (i) faster evaluation than the exact counterpart with a negligible accuracy degradation; (ii) an efficient ALU emulation of a number of Posits operations; and (iii) the possibility to vectorize operations in Posits, using existing ALU vectorized operations (such as the scalable vector extension of ARM CPUs or advanced vector extensions on Intel CPUs). As a second step, we test the proposed activation function on Posit-based DNNs, showing how 16-bit down to 10-bit Posits represent an exact replacement for 32-bit floats while 8-bit Posits could be an interesting alternative to 32-bit floats since their performances are a bit lower but their high speed and low storage properties are very appealing (leading to a lower bandwidth demand and more cache-friendly code). Finally, we point out how small Posits (i.e., up to 14 bits long) are very interesting while PPUs become widespread, since Posit operations can be tabulated in a very efficient way (see details in the text).

An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform

In the past years, several QRS complex (Q, R and S wave) detecting algorithms have been implemented in software, but they are not applicable for real-time operation due to their mathematical complexity. Hence, this paper focuses on developing an algorithm which enables detection of QRS complex in real time. Here, Integer Haar Wavelet Transform is employed which is used for the purpose of filtering ECG signal and detecting the R-peak frequency of QRS complex. Various blocks of the proposed architecture are implemented in a Digilent Nexys 4 double data rate field-programmable gate array board with only 501 flip-flops and 557 look-up tables utilized which makes it suitable for directly installing it into medical equipment or further developing a smart internet of things system for bio-medical applications. To make the designed system more generic, several similar blocks or components have been used. At first, the principle of using wavelet to detect QRS complex is explored theoretically and accordingly used for developing our system. An efficient hardware architecture is implemented incorporating many simplifications, a significant one being approximation of floating point arithmetic to integer arithmetic, required for wavelets. The architecture of the designed system is represented with demonstration in behavioral simulation as well as hardware testing. In the end, the system is analyzed and results are obtained with an error percentage in RR interval computation of less than 1.4% and QRS detection accuracy of 98.76%. The proposed architecture is also synthesized using 130 nm technology which produces 0.717% of leakage power. The developed architecture can be used for analysis of other bio-medical signals where the operation of wavelet transform in hardware is required.

Information-Optimum Approximate Message Passing for Quantized Massive MIMO Detection

We propose an information-optimum approximate message passing (AMP) for quantized massive multi-input multi-output (MIMO) signal detection. A well-known strategy for realizing low-complexity and high-accuracy massive multi-user detection (MUD) is AMP-based belief propagation (BP). However, when internal operations are conducted with double-precision arithmetic, large memory occupancy and severe processing delay are inevitable in the actual massive MIMO implementation. To address this issue, we replace all operations with a simple look-up table (LUT) search where all messages exchanged between each iteration process are unsigned integers. That is, the proposed signal detection is performed using only simple integer arithmetic. The LUT is designed offline using an information-bottleneck (IB) method, and the probability distribution of messages at each iteration step is required for determining the quantization threshold tracked by discrete density evolution (DDE). Computer simulations demonstrate the validity of the IB LUT-based AMP in terms of bit error rate (BER) performance and memory occupancy. The proposed method allows quantizing the AMP detector with fewer bits while maintaining similar performances, such as that of a typical AMP with double-precision.

Arithmetic integer additive set-valued graphs: a creative review

Arithmetic integer additive set-valued graphs: a creative review

A Hardware-Friendly Hyperspectral Lossy Compressor for Next-Generation Space-Grade Field Programmable Gate Arrays

The increment in the data rate of the new-generation hyperspectral sensors is making more critical the necessity of lossy compression solutions able to achieve higher compression ratios (CRs). In this paper, a transform-based lossy compressor, namely lossy compression algorithm for hyperspectral image systems (HW-HyperLCA), is proposed as a modification of the original HyperLCA, specifically designed for being executed into space-grade field programmable gate array (FPGA) devices. The HW-HyperLCA compressor can be totally executed using integer arithmetic, using different levels of precision that can be adapted for achieving the best relation between compression performance and computational burden. The experiments carried out in this paper demonstrate that the HW-HyperLCA compressor is able to compress the hyperspectral images to less than 1 bit per pixel per band with low distortions (more than 40 dB of signal-to-noise ratio) while the performed complexity analysis demonstrates that it can be efficiently executed into space-grade FPGAs using very few computational resources and good results in terms of maximum clock frequency can be obtained.

A Quantized CNN-Based Microfluidic Lensless-Sensing Mobile Blood-Acquisition and Analysis System.

This paper proposes a microfluidic lensless-sensing mobile blood-acquisition and analysis system. For a better tradeoff between accuracy and hardware cost, an integer-only quantization algorithm is proposed. Compared with floating-point inference, the proposed quantization algorithm makes a tradeoff that enables miniaturization while maintaining high accuracy. The quantization algorithm allows the convolutional neural network (CNN) inference to be carried out using integer arithmetic and facilitates hardware implementation with area and power savings. A dual configuration register group structure is also proposed to reduce the interval idle time between every neural network layer in order to improve the CNN processing efficiency. We designed a CNN accelerator architecture for the integer-only quantization algorithm and the dual configuration register group and implemented them in field-programmable gate arrays (FPGA). A microfluidic chip and mobile lensless sensing cell image acquisition device were also developed, then combined with the CNN accelerator to build the mobile lensless microfluidic blood image-acquisition and analysis prototype system. We applied the cell segmentation and cell classification CNN in the system and the classification accuracy reached 98.44%. Compared with the floating-point method, the accuracy dropped by only 0.56%, but the area decreased by 45%. When the system is implemented with the maximum frequency of 100 MHz in the FPGA, a classification speed of 17.9 frames per second (fps) can be obtained. The results show that the quantized CNN microfluidic lensless-sensing blood-acquisition and analysis system fully meets the needs of current portable medical devices, and is conducive to promoting the transformation of artificial intelligence (AI)-based blood cell acquisition and analysis work from large servers to portable cell analysis devices, facilitating rapid early analysis of diseases.

ECLES: A general method for local editing of parameters with linear constraints

SummaryWe describe ECLES (Editing by Constrained LEast Squares), a general method for interactive local editing of objects that are defined by a list of parameters subject to a set of linear or affine constraints. The method is intended for situations where each edit action affects only a small set of the parameters; some of which (the “anchors”) are to be set to new given values, whereas the rest (the “derived” ones) are to be modified so as to preserve the constraints. We use exact integer arithmetic in order to reliably determine solvability, to detect and eliminate redundancies in the set of constraints, and to ensure that the solution exactly satisfies the constraints. We also use constrained least squares to choose a suitable solution when the constraints allow multiple solutions. Unlike the usual finite element approach, the method allows editing of any set of anchors with any sufficiently large set of derived parameters. As an example of application, we show how the method can be used to edit smooth ( ) deformations of geometric mesh models.